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gpio: zx: make use of raw_spinlock variants

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The zx gpio driver currently implements an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.

Signed-off-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Julia Cartwright 2017-03-09 10:21:58 -06:00 committed by Linus Walleij
parent a0a584f0e9
commit 8c41ab4f05
1 changed files with 12 additions and 12 deletions
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24
drivers/gpio/gpio-zx.c
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@ -41,7 +41,7 @@
#define ZX_GPIO_NR 16 #define ZX_GPIO_NR 16
struct zx_gpio { struct zx_gpio {
spinlock_t lock; raw_spinlock_t lock;
void __iomem *base; void __iomem *base;
struct gpio_chip gc; struct gpio_chip gc;
@ -56,11 +56,11 @@ static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
if (offset >= gc->ngpio) if (offset >= gc->ngpio)
return -EINVAL; return -EINVAL;
spin_lock_irqsave(&chip->lock, flags); raw_spin_lock_irqsave(&chip->lock, flags);
gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
gpiodir &= ~BIT(offset); gpiodir &= ~BIT(offset);
writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
spin_unlock_irqrestore(&chip->lock, flags); raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0; return 0;
} }
@ -75,7 +75,7 @@ static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
if (offset >= gc->ngpio) if (offset >= gc->ngpio)
return -EINVAL; return -EINVAL;
spin_lock_irqsave(&chip->lock, flags); raw_spin_lock_irqsave(&chip->lock, flags);
gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
gpiodir |= BIT(offset); gpiodir |= BIT(offset);
writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
@ -84,7 +84,7 @@ static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
else else
writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
spin_unlock_irqrestore(&chip->lock, flags); raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0; return 0;
} }
@ -118,7 +118,7 @@ static int zx_irq_type(struct irq_data *d, unsigned trigger)
if (offset < 0 || offset >= ZX_GPIO_NR) if (offset < 0 || offset >= ZX_GPIO_NR)
return -EINVAL; return -EINVAL;
spin_lock_irqsave(&chip->lock, flags); raw_spin_lock_irqsave(&chip->lock, flags);
gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV); gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE); gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
@ -151,7 +151,7 @@ static int zx_irq_type(struct irq_data *d, unsigned trigger)
writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP); writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN); writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV); writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
spin_unlock_irqrestore(&chip->lock, flags); raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0; return 0;
} }
@ -184,12 +184,12 @@ static void zx_irq_mask(struct irq_data *d)
u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
u16 gpioie; u16 gpioie;
spin_lock(&chip->lock); raw_spin_lock(&chip->lock);
gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask; gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask; gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
spin_unlock(&chip->lock); raw_spin_unlock(&chip->lock);
} }
static void zx_irq_unmask(struct irq_data *d) static void zx_irq_unmask(struct irq_data *d)
@ -199,12 +199,12 @@ static void zx_irq_unmask(struct irq_data *d)
u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
u16 gpioie; u16 gpioie;
spin_lock(&chip->lock); raw_spin_lock(&chip->lock);
gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask; gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask; gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
spin_unlock(&chip->lock); raw_spin_unlock(&chip->lock);
} }
static struct irq_chip zx_irqchip = { static struct irq_chip zx_irqchip = {
@ -230,7 +230,7 @@ static int zx_gpio_probe(struct platform_device *pdev)
if (IS_ERR(chip->base)) if (IS_ERR(chip->base))
return PTR_ERR(chip->base); return PTR_ERR(chip->base);
spin_lock_init(&chip->lock); raw_spin_lock_init(&chip->lock);
if (of_property_read_bool(dev->of_node, "gpio-ranges")) { if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
chip->gc.request = gpiochip_generic_request; chip->gc.request = gpiochip_generic_request;
chip->gc.free = gpiochip_generic_free; chip->gc.free = gpiochip_generic_free;