net: phy: add qca8081 cdt feature
To perform CDT of qca8081 phy: 1. disable hibernation. 2. force phy working in MDI mode. 3. force phy working in 1000BASE-T mode. 4. configure the related thresholds. Signed-off-by: Luo Jie <luoj@codeaurora.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Luo Jie
David S. Miller
parent
8bc1c5430c
commit
8c84d7528d
@ -229,6 +229,32 @@
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#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
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#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
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/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
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* when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
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*/
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#define QCA808X_DBG_AN_TEST 0xb
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#define QCA808X_HIBERNATION_EN BIT(15)
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#define QCA808X_CDT_ENABLE_TEST BIT(15)
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#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
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#define QCA808X_CDT_LENGTH_UNIT BIT(10)
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#define QCA808X_MMD3_CDT_STATUS 0x8064
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#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
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#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
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#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
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#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
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#define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0)
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#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
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#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
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#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
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#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
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#define QCA808X_CDT_STATUS_STAT_FAIL 0
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#define QCA808X_CDT_STATUS_STAT_NORMAL 1
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#define QCA808X_CDT_STATUS_STAT_OPEN 2
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#define QCA808X_CDT_STATUS_STAT_SHORT 3
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MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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@ -1319,8 +1345,14 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair)
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{
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u16 cdt;
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cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
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AT803X_CDT_ENABLE_TEST;
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/* qca8081 takes the different bit 15 to enable CDT test */
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if (phydev->drv->phy_id == QCA8081_PHY_ID)
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cdt = QCA808X_CDT_ENABLE_TEST |
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QCA808X_CDT_LENGTH_UNIT |
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QCA808X_CDT_INTER_CHECK_DIS;
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else
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cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
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AT803X_CDT_ENABLE_TEST;
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return phy_write(phydev, AT803X_CDT, cdt);
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}
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@ -1328,10 +1360,16 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair)
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static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
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{
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int val, ret;
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u16 cdt_en;
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if (phydev->drv->phy_id == QCA8081_PHY_ID)
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cdt_en = QCA808X_CDT_ENABLE_TEST;
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else
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cdt_en = AT803X_CDT_ENABLE_TEST;
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/* One test run takes about 25ms */
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ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
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!(val & AT803X_CDT_ENABLE_TEST),
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!(val & cdt_en),
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30000, 100000, true);
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return ret < 0 ? ret : 0;
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@ -1685,6 +1723,153 @@ static int qca808x_soft_reset(struct phy_device *phydev)
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return qca808x_phy_ms_seed_enable(phydev, true);
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}
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static bool qca808x_cdt_fault_length_valid(int cdt_code)
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{
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switch (cdt_code) {
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case QCA808X_CDT_STATUS_STAT_SHORT:
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case QCA808X_CDT_STATUS_STAT_OPEN:
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return true;
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default:
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return false;
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}
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}
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static int qca808x_cable_test_result_trans(int cdt_code)
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{
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switch (cdt_code) {
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case QCA808X_CDT_STATUS_STAT_NORMAL:
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return ETHTOOL_A_CABLE_RESULT_CODE_OK;
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case QCA808X_CDT_STATUS_STAT_SHORT:
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return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
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case QCA808X_CDT_STATUS_STAT_OPEN:
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return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
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case QCA808X_CDT_STATUS_STAT_FAIL:
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default:
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return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
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}
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}
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static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)
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{
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int val;
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u32 cdt_length_reg = 0;
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switch (pair) {
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case ETHTOOL_A_CABLE_PAIR_A:
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cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
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break;
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case ETHTOOL_A_CABLE_PAIR_B:
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cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
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break;
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case ETHTOOL_A_CABLE_PAIR_C:
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cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
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break;
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case ETHTOOL_A_CABLE_PAIR_D:
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cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
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break;
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default:
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return -EINVAL;
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}
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
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if (val < 0)
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return val;
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return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;
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}
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static int qca808x_cable_test_start(struct phy_device *phydev)
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{
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int ret;
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/* perform CDT with the following configs:
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* 1. disable hibernation.
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* 2. force PHY working in MDI mode.
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* 3. for PHY working in 1000BaseT.
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* 4. configure the threshold.
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*/
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ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
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if (ret < 0)
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return ret;
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ret = at803x_config_mdix(phydev, ETH_TP_MDI);
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if (ret < 0)
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return ret;
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/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_1000;
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ret = genphy_c45_pma_setup_forced(phydev);
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if (ret < 0)
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return ret;
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ret = genphy_setup_forced(phydev);
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if (ret < 0)
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return ret;
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/* configure the thresholds for open, short, pair ok test */
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
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return 0;
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}
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static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
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{
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int ret, val;
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int pair_a, pair_b, pair_c, pair_d;
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*finished = false;
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ret = at803x_cdt_start(phydev, 0);
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if (ret)
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return ret;
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ret = at803x_cdt_wait_for_completion(phydev);
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if (ret)
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return ret;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
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if (val < 0)
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return val;
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pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);
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pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);
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pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);
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pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
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qca808x_cable_test_result_trans(pair_a));
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
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qca808x_cable_test_result_trans(pair_b));
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
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qca808x_cable_test_result_trans(pair_c));
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
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qca808x_cable_test_result_trans(pair_d));
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if (qca808x_cdt_fault_length_valid(pair_a))
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ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
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qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));
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if (qca808x_cdt_fault_length_valid(pair_b))
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ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,
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qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));
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if (qca808x_cdt_fault_length_valid(pair_c))
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ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,
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qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));
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if (qca808x_cdt_fault_length_valid(pair_d))
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ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,
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qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));
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*finished = true;
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return 0;
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}
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static struct phy_driver at803x_driver[] = {
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{
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/* Qualcomm Atheros AR8035 */
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@ -1848,6 +2033,7 @@ static struct phy_driver at803x_driver[] = {
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/* Qualcomm QCA8081 */
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PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
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.name = "Qualcomm QCA8081",
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.flags = PHY_POLL_CABLE_TEST,
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.config_intr = at803x_config_intr,
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.handle_interrupt = at803x_handle_interrupt,
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.get_tunable = at803x_get_tunable,
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@ -1861,6 +2047,8 @@ static struct phy_driver at803x_driver[] = {
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.read_status = qca808x_read_status,
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.config_init = qca808x_config_init,
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.soft_reset = qca808x_soft_reset,
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.cable_test_start = qca808x_cable_test_start,
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.cable_test_get_status = qca808x_cable_test_get_status,
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}, };
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module_phy_driver(at803x_driver);
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