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drm/nouveau/fifo: expose non-stall intr in host channel event class

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2022-06-01 20:46:39 +10:00
parent 801bc8584e
commit 8c880fd4c1
14 changed files with 64 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
View File

@ -10,6 +10,4 @@ struct g82_channel_dma_v0 {
__u64 pushbuf;
__u64 offset;
};
#define NV826E_V0_NTFY_NON_STALL_INTERRUPT 0x00
#endif

2
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
View File

@ -11,6 +11,4 @@ struct g82_channel_gpfifo_v0 {
__u64 pushbuf;
__u64 vmm;
};
#define NV826F_V0_NTFY_NON_STALL_INTERRUPT 0x00
#endif

1
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
View File

@ -11,6 +11,5 @@ struct fermi_channel_gpfifo_v0 {
__u64 vmm;
};
#define NV906F_V0_NTFY_NON_STALL_INTERRUPT 0x00
#define NV906F_V0_NTFY_KILLED 0x01
#endif

1
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
View File

@ -13,6 +13,5 @@ struct kepler_channel_gpfifo_a_v0 {
__u64 inst;
};
#define NVA06F_V0_NTFY_NON_STALL_INTERRUPT 0x00
#define NVA06F_V0_NTFY_KILLED 0x01
#endif

2
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@ -40,6 +40,8 @@
#define NVIF_CLASS_HEAD /* if0013.h */ 0x80000013
#define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014
#define NVIF_CLASS_CHAN /* if0020.h */ 0x80000020
/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_NULL_CLASS 0x00000030

1
drivers/gpu/drm/nouveau/include/nvif/clc36f.h
View File

@ -14,6 +14,5 @@ struct volta_channel_gpfifo_a_v0 {
__u32 token;
};
#define NVC36F_V0_NTFY_NON_STALL_INTERRUPT 0x00
#define NVC36F_V0_NTFY_KILLED 0x01
#endif

12
drivers/gpu/drm/nouveau/include/nvif/if0020.h Normal file
View File

@ -0,0 +1,12 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0020_H__
#define __NVIF_IF0020_H__
union nvif_chan_event_args {
struct nvif_chan_event_v0 {
__u8 version;
#define NVIF_CHAN_EVENT_V0_NON_STALL_INTR 0x00
__u8 type;
} v0;
};
#endif

1
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View File

@ -42,6 +42,7 @@ struct nvkm_fifo {
spinlock_t lock;
struct mutex mutex;
#define NVKM_FIFO_EVENT_NON_STALL_INTR BIT(0)
struct nvkm_event uevent; /* async user trigger */
struct nvkm_event kevent; /* channel killed */
};

42
drivers/gpu/drm/nouveau/nouveau_fence.c
View File

@ -29,9 +29,7 @@
#include <linux/sched/signal.h>
#include <trace/events/dma_fence.h>
#include <nvif/cl826e.h>
#include <nvif/notify.h>
#include <nvif/event.h>
#include <nvif/if0020.h>
#include "nouveau_drv.h"
#include "nouveau_dma.h"
@ -99,7 +97,7 @@ nouveau_fence_context_kill(struct nouveau_fence_chan *fctx, int error)
dma_fence_set_error(&fence->base, error);
if (nouveau_fence_signal(fence))
nvif_notify_put(&fctx->notify);
nvif_event_block(&fctx->event);
}
spin_unlock_irq(&fctx->lock);
}
@ -108,7 +106,7 @@ void
nouveau_fence_context_del(struct nouveau_fence_chan *fctx)
{
nouveau_fence_context_kill(fctx, 0);
nvif_notify_dtor(&fctx->notify);
nvif_event_dtor(&fctx->event);
fctx->dead = 1;
/*
@ -150,12 +148,11 @@ nouveau_fence_update(struct nouveau_channel *chan, struct nouveau_fence_chan *fc
}
static int
nouveau_fence_wait_uevent_handler(struct nvif_notify *notify)
nouveau_fence_wait_uevent_handler(struct nvif_event *event, void *repv, u32 repc)
{
struct nouveau_fence_chan *fctx =
container_of(notify, typeof(*fctx), notify);
struct nouveau_fence_chan *fctx = container_of(event, typeof(*fctx), event);
unsigned long flags;
int ret = NVIF_NOTIFY_KEEP;
int ret = NVIF_EVENT_KEEP;
spin_lock_irqsave(&fctx->lock, flags);
if (!list_empty(&fctx->pending)) {
@ -165,7 +162,7 @@ nouveau_fence_wait_uevent_handler(struct nvif_notify *notify)
fence = list_entry(fctx->pending.next, typeof(*fence), head);
chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock));
if (nouveau_fence_update(chan, fctx))
ret = NVIF_NOTIFY_DROP;
ret = NVIF_EVENT_DROP;
}
spin_unlock_irqrestore(&fctx->lock, flags);
@ -177,6 +174,10 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha
{
struct nouveau_fence_priv *priv = (void*)chan->drm->fence;
struct nouveau_cli *cli = (void *)chan->user.client;
struct {
struct nvif_event_v0 base;
struct nvif_chan_event_v0 host;
} args;
int ret;
INIT_LIST_HEAD(&fctx->flip);
@ -195,13 +196,12 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha
if (!priv->uevent)
return;
ret = nvif_notify_ctor(&chan->user, "fenceNonStallIntr",
nouveau_fence_wait_uevent_handler,
false, NV826E_V0_NTFY_NON_STALL_INTERRUPT,
&(struct nvif_notify_uevent_req) { },
sizeof(struct nvif_notify_uevent_req),
sizeof(struct nvif_notify_uevent_rep),
&fctx->notify);
args.host.version = 0;
args.host.type = NVIF_CHAN_EVENT_V0_NON_STALL_INTR;
ret = nvif_event_ctor(&chan->user, "fenceNonStallIntr", chan->chid,
nouveau_fence_wait_uevent_handler, false,
&args.base, sizeof(args), &fctx->event);
WARN_ON(ret);
}
@ -230,7 +230,7 @@ nouveau_fence_emit(struct nouveau_fence *fence, struct nouveau_channel *chan)
spin_lock_irq(&fctx->lock);
if (nouveau_fence_update(chan, fctx))
nvif_notify_put(&fctx->notify);
nvif_event_block(&fctx->event);
list_add_tail(&fence->head, &fctx->pending);
spin_unlock_irq(&fctx->lock);
@ -254,7 +254,7 @@ nouveau_fence_done(struct nouveau_fence *fence)
spin_lock_irqsave(&fctx->lock, flags);
chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock));
if (chan && nouveau_fence_update(chan, fctx))
nvif_notify_put(&fctx->notify);
nvif_event_block(&fctx->event);
spin_unlock_irqrestore(&fctx->lock, flags);
}
return dma_fence_is_signaled(&fence->base);
@ -505,13 +505,13 @@ static bool nouveau_fence_enable_signaling(struct dma_fence *f)
bool ret;
if (!fctx->notify_ref++)
nvif_notify_get(&fctx->notify);
nvif_event_allow(&fctx->event);
ret = nouveau_fence_no_signaling(f);
if (ret)
set_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags);
else if (!--fctx->notify_ref)
nvif_notify_put(&fctx->notify);
nvif_event_block(&fctx->event);
return ret;
}

4
drivers/gpu/drm/nouveau/nouveau_fence.h
View File

@ -3,7 +3,7 @@
#define __NOUVEAU_FENCE_H__
#include <linux/dma-fence.h>
#include <nvif/notify.h>
#include <nvif/event.h>
struct nouveau_drm;
struct nouveau_bo;
@ -44,7 +44,7 @@ struct nouveau_fence_chan {
u32 context;
char name[32];
struct nvif_notify notify;
struct nvif_event event;
int notify_ref, dead;
};

23
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
View File

@ -158,27 +158,8 @@ nvkm_fifo_uevent_init(struct nvkm_event *event, int type, int index)
fifo->func->uevent_init(fifo);
}
static int
nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
union {
struct nvif_notify_uevent_req none;
} *req = data;
int ret = -ENOSYS;
if (!(ret = nvif_unvers(ret, &data, &size, req->none))) {
notify->size = sizeof(struct nvif_notify_uevent_rep);
notify->types = 1;
notify->index = 0;
}
return ret;
}
static const struct nvkm_event_func
nvkm_fifo_uevent_func = {
.ctor = nvkm_fifo_uevent_ctor,
.init = nvkm_fifo_uevent_init,
.fini = nvkm_fifo_uevent_fini,
};
@ -186,9 +167,7 @@ nvkm_fifo_uevent_func = {
void
nvkm_fifo_uevent(struct nvkm_fifo *fifo)
{
struct nvif_notify_uevent_rep rep = {
};
nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep));
nvkm_event_send(&fifo->uevent, NVKM_FIFO_EVENT_NON_STALL_INTR, 0, NULL, 0);
}
static int

25
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
View File

@ -29,6 +29,8 @@
#include <subdev/mmu.h>
#include <engine/dma.h>
#include <nvif/if0020.h>
struct nvkm_fifo_chan_object {
struct nvkm_oproxy oproxy;
struct nvkm_fifo_chan *chan;
@ -250,6 +252,28 @@ nvkm_fifo_chan_child_get(struct nvkm_object *object, int index,
return -EINVAL;
}
static int
nvkm_fifo_chan_uevent(struct nvkm_object *object, void *argv, u32 argc, struct nvkm_uevent *uevent)
{
struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
union nvif_chan_event_args *args = argv;
if (!uevent)
return 0;
if (argc != sizeof(args->v0) || args->v0.version != 0)
return -ENOSYS;
switch (args->v0.type) {
case NVIF_CHAN_EVENT_V0_NON_STALL_INTR:
return nvkm_uevent_add(uevent, &chan->fifo->uevent, 0,
NVKM_FIFO_EVENT_NON_STALL_INTR, NULL);
default:
break;
}
return -ENOSYS;
}
static int
nvkm_fifo_chan_ntfy(struct nvkm_object *object, u32 type,
struct nvkm_event **pevent)
@ -320,6 +344,7 @@ nvkm_fifo_chan_func = {
.ntfy = nvkm_fifo_chan_ntfy,
.map = nvkm_fifo_chan_map,
.sclass = nvkm_fifo_chan_child_get,
.uevent = nvkm_fifo_chan_uevent,
};
int

15
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
View File

@ -30,20 +30,6 @@
#include <nvif/cl826e.h>
static int
g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
struct nvkm_event **pevent)
{
switch (type) {
case NV826E_V0_NTFY_NON_STALL_INTERRUPT:
*pevent = &chan->fifo->uevent;
return 0;
default:
break;
}
return -EINVAL;
}
static int
g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
{
@ -198,7 +184,6 @@ g84_fifo_chan_func = {
.dtor = nv50_fifo_chan_dtor,
.init = g84_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
.ntfy = g84_fifo_chan_ntfy,
.engine_ctor = g84_fifo_chan_engine_ctor,
.engine_dtor = nv50_fifo_chan_engine_dtor,
.engine_init = g84_fifo_chan_engine_init,

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
View File

@ -37,9 +37,6 @@ gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
struct nvkm_event **pevent)
{
switch (type) {
case NV906F_V0_NTFY_NON_STALL_INTERRUPT:
*pevent = &chan->fifo->uevent;
return 0;
case NV906F_V0_NTFY_KILLED:
*pevent = &chan->fifo->kevent;
return 0;