dmaengine/amba-pl08x: Take flow controller info from DMA_SLAVE_CONFIG
Flow controller information is passed now from DMA_SLAVE_CONFIG option. This patch makes changes in pl08x driver to use device_fc from it instead of platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
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@ -1139,6 +1139,8 @@ static int dma_set_runtime_config(struct dma_chan *chan,
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cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
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cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
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cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
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cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
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plchan->device_fc = config->device_fc;
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if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
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if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
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plchan->src_addr = config->src_addr;
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plchan->src_addr = config->src_addr;
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plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
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plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
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@ -1370,7 +1372,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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return NULL;
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return NULL;
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}
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}
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if (plchan->cd->device_fc)
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if (plchan->device_fc)
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tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
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tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
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PL080_FLOW_PER2MEM_PER;
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PL080_FLOW_PER2MEM_PER;
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else
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else
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@ -47,9 +47,6 @@ enum {
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* @muxval: a number usually used to poke into some mux regiser to
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* @muxval: a number usually used to poke into some mux regiser to
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* mux in the signal to this channel
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* mux in the signal to this channel
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* @cctl_opt: default options for the channel control register
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* @cctl_opt: default options for the channel control register
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* @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
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* channels. Fill with 'true' if peripheral should be flow controller. Direction
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* will be selected at Runtime.
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* @addr: source/target address in physical memory for this DMA channel,
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* @addr: source/target address in physical memory for this DMA channel,
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* can be the address of a FIFO register for burst requests for example.
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* can be the address of a FIFO register for burst requests for example.
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* This can be left undefined if the PrimeCell API is used for configuring
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* This can be left undefined if the PrimeCell API is used for configuring
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@ -68,7 +65,6 @@ struct pl08x_channel_data {
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int max_signal;
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int max_signal;
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u32 muxval;
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u32 muxval;
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u32 cctl;
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u32 cctl;
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bool device_fc;
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dma_addr_t addr;
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dma_addr_t addr;
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bool circular_buffer;
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bool circular_buffer;
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bool single;
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bool single;
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@ -183,6 +179,9 @@ enum pl08x_dma_chan_state {
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* @host: a pointer to the host (internal use)
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* @host: a pointer to the host (internal use)
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* @state: whether the channel is idle, paused, running etc
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* @state: whether the channel is idle, paused, running etc
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* @slave: whether this channel is a device (slave) or for memcpy
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* @slave: whether this channel is a device (slave) or for memcpy
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* @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
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* channels. Fill with 'true' if peripheral should be flow controller. Direction
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* will be selected at Runtime.
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* @waiting: a TX descriptor on this channel which is waiting for a physical
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* @waiting: a TX descriptor on this channel which is waiting for a physical
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* channel to become available
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* channel to become available
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*/
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*/
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@ -205,6 +204,7 @@ struct pl08x_dma_chan {
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struct pl08x_driver_data *host;
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struct pl08x_driver_data *host;
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enum pl08x_dma_chan_state state;
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enum pl08x_dma_chan_state state;
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bool slave;
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bool slave;
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bool device_fc;
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struct pl08x_txd *waiting;
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struct pl08x_txd *waiting;
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};
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};
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