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staging: ccree: fix enum/struct definitions style

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Fix enum and struct definition coding style by removing uneeded typedef and
s/CamelCase/snake_case/g.

Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef 2017-05-07 16:35:58 +03:00 committed by Greg Kroah-Hartman
parent df8a6b053c
commit 8ca57f5cec
11 changed files with 100 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/staging/ccree/cc_hw_queue_defs.h
View File

@ -40,29 +40,28 @@
* TYPE DEFINITIONS
******************************************************************************/
typedef struct HwDesc {
struct cc_hw_desc {
u32 word[HW_DESC_SIZE_WORDS];
} HwDesc_s;
};
typedef enum DescDirection {
enum cc_desc_direction {
DESC_DIRECTION_ILLEGAL = -1,
DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
DESC_DIRECTION_DECRYPT_DECRYPT = 1,
DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
DESC_DIRECTION_END = S32_MAX,
}DescDirection_t;
};
typedef enum DmaMode {
enum cc_dma_mode {
DMA_MODE_NULL = -1,
NO_DMA = 0,
DMA_SRAM = 1,
DMA_DLLI = 2,
DMA_MLLI = 3,
DmaMode_OPTIONTS,
DmaMode_END = S32_MAX,
}DmaMode_t;
DMA_MODE_END = S32_MAX,
};
typedef enum FlowMode {
enum cc_flow_mode {
FLOW_MODE_NULL = -1,
/* data flows */
BYPASS = 0,
@ -97,19 +96,17 @@ typedef enum FlowMode {
S_DES_to_DOUT = 42,
S_HASH_to_DOUT = 43,
SET_FLOW_ID = 44,
FlowMode_OPTIONTS,
FlowMode_END = S32_MAX,
}FlowMode_t;
FLOW_MODE_END = S32_MAX,
};
typedef enum TunnelOp {
enum cc_tunnel_op {
TUNNEL_OP_INVALID = -1,
TUNNEL_OFF = 0,
TUNNEL_ON = 1,
TunnelOp_OPTIONS,
TunnelOp_END = S32_MAX,
} TunnelOp_t;
TUNNEL_OP_END = S32_MAX,
};
typedef enum SetupOp {
enum cc_setup_op {
SETUP_LOAD_NOP = 0,
SETUP_LOAD_STATE0 = 1,
SETUP_LOAD_STATE1 = 2,
@ -120,15 +117,14 @@ typedef enum SetupOp {
SETUP_WRITE_STATE1 = 9,
SETUP_WRITE_STATE2 = 10,
SETUP_WRITE_STATE3 = 11,
setupOp_OPTIONTS,
setupOp_END = S32_MAX,
}SetupOp_t;
SETUP_OP_END = S32_MAX,
};
enum AesMacSelector {
enum cc_aes_mac_selector {
AES_SK = 1,
AES_CMAC_INIT = 2,
AES_CMAC_SIZE0 = 3,
AesMacEnd = S32_MAX,
AES_MAC_END = S32_MAX,
};
#define HW_KEY_MASK_CIPHER_DO 0x3
@ -137,7 +133,7 @@ enum AesMacSelector {
/* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
/* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
typedef enum HwCryptoKey {
enum cc_hw_crypto_key {
USER_KEY = 0, /* 0x0000 */
ROOT_KEY = 1, /* 0x0001 */
PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */
@ -150,21 +146,21 @@ typedef enum HwCryptoKey {
KFDE2_KEY = 10, /* 0x1010 */
KFDE3_KEY = 11, /* 0x1011 */
END_OF_KEYS = S32_MAX,
}HwCryptoKey_t;
};
typedef enum HwAesKeySize {
enum cc_hw_aes_key_size {
AES_128_KEY = 0,
AES_192_KEY = 1,
AES_256_KEY = 2,
END_OF_AES_KEYS = S32_MAX,
}HwAesKeySize_t;
};
typedef enum HwDesKeySize {
enum cc_hw_des_key_size {
DES_ONE_KEY = 0,
DES_TWO_KEYS = 1,
DES_THREE_KEYS = 2,
END_OF_DES_KEYS = S32_MAX,
}HwDesKeySize_t;
};
/*****************************/
/* Descriptor packing macros */
@ -172,7 +168,7 @@ typedef enum HwDesKeySize {
#define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx) )
#define HW_DESC_INIT(pDesc) memset(pDesc, 0, sizeof(HwDesc_s))
#define HW_DESC_INIT(pDesc) memset(pDesc, 0, sizeof(struct cc_hw_desc))
/*!
* This macro indicates the end of current HW descriptors flow and release the HW engines.

54
drivers/staging/ccree/ssi_aead.c
View File

@ -79,7 +79,7 @@ struct ssi_aead_ctx {
unsigned int auth_keylen;
unsigned int authsize; /* Actual (reduced?) size of the MAC/ICv */
enum drv_cipher_mode cipher_mode;
enum FlowMode flow_mode;
enum cc_flow_mode flow_mode;
enum drv_hash_mode auth_mode;
};
@ -274,7 +274,7 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c
aead_request_complete(areq, err);
}
static int xcbc_setkey(HwDesc_s *desc, struct ssi_aead_ctx *ctx)
static int xcbc_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx)
{
/* Load the AES key */
HW_DESC_INIT(&desc[0]);
@ -309,7 +309,7 @@ static int xcbc_setkey(HwDesc_s *desc, struct ssi_aead_ctx *ctx)
return 4;
}
static int hmac_setkey(HwDesc_s *desc, struct ssi_aead_ctx *ctx)
static int hmac_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx)
{
unsigned int hmacPadConst[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST };
unsigned int digest_ofs = 0;
@ -436,7 +436,7 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl
unsigned int hashmode;
unsigned int idx = 0;
int rc = 0;
HwDesc_s desc[MAX_AEAD_SETKEY_SEQ];
struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ];
dma_addr_t padded_authkey_dma_addr =
ctx->auth_state.hmac.padded_authkey_dma_addr;
@ -568,7 +568,7 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
struct rtattr *rta = (struct rtattr *)key;
struct ssi_crypto_req ssi_req = {};
struct crypto_authenc_key_param *param;
HwDesc_s desc[MAX_AEAD_SETKEY_SEQ];
struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ];
int seq_len = 0, rc = -EINVAL;
DECL_CYCLE_COUNT_RESOURCES;
@ -756,7 +756,7 @@ static inline void
ssi_aead_create_assoc_desc(
struct aead_request *areq,
unsigned int flow_mode,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(areq);
@ -799,7 +799,7 @@ static inline void
ssi_aead_process_authenc_data_desc(
struct aead_request *areq,
unsigned int flow_mode,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size,
int direct)
{
@ -862,7 +862,7 @@ static inline void
ssi_aead_process_cipher_data_desc(
struct aead_request *areq,
unsigned int flow_mode,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
unsigned int idx = *seq_size;
@ -905,7 +905,7 @@ ssi_aead_process_cipher_data_desc(
static inline void ssi_aead_process_digest_result_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -955,7 +955,7 @@ static inline void ssi_aead_process_digest_result_desc(
static inline void ssi_aead_setup_cipher_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1002,7 +1002,7 @@ static inline void ssi_aead_setup_cipher_desc(
static inline void ssi_aead_process_cipher(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size,
unsigned int data_flow_mode)
{
@ -1028,7 +1028,7 @@ static inline void ssi_aead_process_cipher(
static inline void ssi_aead_hmac_setup_digest_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1064,7 +1064,7 @@ static inline void ssi_aead_hmac_setup_digest_desc(
static inline void ssi_aead_xcbc_setup_digest_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1128,7 +1128,7 @@ static inline void ssi_aead_xcbc_setup_digest_desc(
static inline void ssi_aead_process_digest_header_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
unsigned int idx = *seq_size;
@ -1142,7 +1142,7 @@ static inline void ssi_aead_process_digest_header_desc(
static inline void ssi_aead_process_digest_scheme_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1206,7 +1206,7 @@ static inline void ssi_aead_process_digest_scheme_desc(
static inline void ssi_aead_load_mlli_to_sram(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
@ -1233,12 +1233,12 @@ static inline void ssi_aead_load_mlli_to_sram(
}
}
static inline enum FlowMode ssi_aead_get_data_flow_mode(
static inline enum cc_flow_mode ssi_aead_get_data_flow_mode(
enum drv_crypto_direction direct,
enum FlowMode setup_flow_mode,
enum cc_flow_mode setup_flow_mode,
bool is_single_pass)
{
enum FlowMode data_flow_mode;
enum cc_flow_mode data_flow_mode;
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
if (setup_flow_mode == S_DIN_to_AES)
@ -1261,7 +1261,7 @@ static inline enum FlowMode ssi_aead_get_data_flow_mode(
static inline void ssi_aead_hmac_authenc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1313,7 +1313,7 @@ static inline void ssi_aead_hmac_authenc(
static inline void
ssi_aead_xcbc_authenc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1457,7 +1457,7 @@ static int set_msg_len(u8 *block, unsigned int msglen, unsigned int csize)
static inline int ssi_aead_ccm(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1663,7 +1663,7 @@ static void ssi_rfc4309_ccm_process(struct aead_request *req)
static inline void ssi_aead_gcm_setup_ghash_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1742,7 +1742,7 @@ static inline void ssi_aead_gcm_setup_ghash_desc(
static inline void ssi_aead_gcm_setup_gctr_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1780,7 +1780,7 @@ static inline void ssi_aead_gcm_setup_gctr_desc(
static inline void ssi_aead_process_gcm_result_desc(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
@ -1849,7 +1849,7 @@ static inline void ssi_aead_process_gcm_result_desc(
static inline int ssi_aead_gcm(
struct aead_request *req,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct aead_req_ctx *req_ctx = aead_request_ctx(req);
@ -1999,7 +1999,7 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
{
int rc = 0;
int seq_len = 0;
HwDesc_s desc[MAX_AEAD_PROCESS_SEQ];
struct cc_hw_desc desc[MAX_AEAD_PROCESS_SEQ];
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);

14
drivers/staging/ccree/ssi_cipher.c
View File

@ -49,8 +49,8 @@ struct cc_user_key_info {
dma_addr_t key_dma_addr;
};
struct cc_hw_key_info {
enum HwCryptoKey key1_slot;
enum HwCryptoKey key2_slot;
enum cc_hw_crypto_key key1_slot;
enum cc_hw_crypto_key key2_slot;
};
struct ssi_ablkcipher_ctx {
@ -302,7 +302,7 @@ static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
return 0;
}
static enum HwCryptoKey hw_key_to_cc_hw_key(int slot_num)
static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
{
switch (slot_num) {
case 0:
@ -464,7 +464,7 @@ ssi_blkcipher_create_setup_desc(
struct blkcipher_req_ctx *req_ctx,
unsigned int ivsize,
unsigned int nbytes,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
@ -592,7 +592,7 @@ static inline void ssi_blkcipher_create_multi2_setup_desc(
struct crypto_tfm *tfm,
struct blkcipher_req_ctx *req_ctx,
unsigned int ivsize,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
@ -645,7 +645,7 @@ ssi_blkcipher_create_data_desc(
struct scatterlist *dst, struct scatterlist *src,
unsigned int nbytes,
void *areq,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
@ -784,7 +784,7 @@ static int ssi_blkcipher_process(
{
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
struct device *dev = &ctx_p->drvdata->plat_dev->dev;
HwDesc_s desc[MAX_ABLKCIPHER_SEQ_LEN];
struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN];
struct ssi_crypto_req ssi_req = {};
int rc, seq_len = 0,cts_restore_flag = 0;
DECL_CYCLE_COUNT_RESOURCES;

12
drivers/staging/ccree/ssi_fips_ll.c
View File

@ -314,7 +314,7 @@ ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata,
int rc;
struct ssi_crypto_req ssi_req = {0};
HwDesc_s desc[FIPS_CIPHER_MAX_SEQ_LEN];
struct cc_hw_desc desc[FIPS_CIPHER_MAX_SEQ_LEN];
int idx = 0;
int s_flow_mode = is_aes ? S_DIN_to_AES : S_DIN_to_DES;
@ -495,7 +495,7 @@ ssi_cmac_fips_run_test(struct ssi_drvdata *drvdata,
int rc;
struct ssi_crypto_req ssi_req = {0};
HwDesc_s desc[FIPS_CMAC_MAX_SEQ_LEN];
struct cc_hw_desc desc[FIPS_CMAC_MAX_SEQ_LEN];
int idx = 0;
/* Setup CMAC Key */
@ -640,7 +640,7 @@ ssi_hash_fips_run_test(struct ssi_drvdata *drvdata,
int rc;
struct ssi_crypto_req ssi_req = {0};
HwDesc_s desc[FIPS_HASH_MAX_SEQ_LEN];
struct cc_hw_desc desc[FIPS_HASH_MAX_SEQ_LEN];
int idx = 0;
/* Load initial digest */
@ -823,7 +823,7 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata,
int rc;
struct ssi_crypto_req ssi_req = {0};
HwDesc_s desc[FIPS_HMAC_MAX_SEQ_LEN];
struct cc_hw_desc desc[FIPS_HMAC_MAX_SEQ_LEN];
int idx = 0;
int i;
/* calc the hash opad first and ipad only afterwards (unlike the flow in ssi_hash.c) */
@ -1131,7 +1131,7 @@ ssi_ccm_fips_run_test(struct ssi_drvdata *drvdata,
int rc;
struct ssi_crypto_req ssi_req = {0};
HwDesc_s desc[FIPS_CCM_MAX_SEQ_LEN];
struct cc_hw_desc desc[FIPS_CCM_MAX_SEQ_LEN];
unsigned int idx = 0;
unsigned int cipher_flow_mode;
@ -1358,7 +1358,7 @@ ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata,
int rc;
struct ssi_crypto_req ssi_req = {0};
HwDesc_s desc[FIPS_GCM_MAX_SEQ_LEN];
struct cc_hw_desc desc[FIPS_GCM_MAX_SEQ_LEN];
unsigned int idx = 0;
unsigned int cipher_flow_mode;

38
drivers/staging/ccree/ssi_hash.c
View File

@ -67,11 +67,11 @@ static const u64 sha512_init[] = {
static void ssi_hash_create_xcbc_setup(
struct ahash_request *areq,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size);
static void ssi_hash_create_cmac_setup(struct ahash_request *areq,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size);
struct ssi_hash_alg {
@ -116,11 +116,11 @@ static const struct crypto_type crypto_shash_type;
static void ssi_hash_create_data_desc(
struct ahash_req_ctx *areq_ctx,
struct ssi_hash_ctx *ctx,
unsigned int flow_mode,HwDesc_s desc[],
unsigned int flow_mode,struct cc_hw_desc desc[],
bool is_not_last_data,
unsigned int *seq_size);
static inline void ssi_set_hash_endianity(u32 mode, HwDesc_s *desc)
static inline void ssi_set_hash_endianity(u32 mode, struct cc_hw_desc *desc)
{
if (unlikely((mode == DRV_HASH_MD5) ||
(mode == DRV_HASH_SHA384) ||
@ -162,7 +162,7 @@ static int ssi_hash_map_request(struct device *dev,
ssi_sram_addr_t larval_digest_addr = ssi_ahash_get_larval_digest_sram_addr(
ctx->drvdata, ctx->hash_mode);
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc;
struct cc_hw_desc desc;
int rc = -ENOMEM;
state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE ,GFP_KERNEL|GFP_DMA);
@ -450,7 +450,7 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
struct device *dev = &ctx->drvdata->plat_dev->dev;
bool is_hmac = ctx->is_hmac;
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
ssi_sram_addr_t larval_digest_addr = ssi_ahash_get_larval_digest_sram_addr(
ctx->drvdata, ctx->hash_mode);
int idx = 0;
@ -610,7 +610,7 @@ static int ssi_hash_update(struct ahash_req_ctx *state,
{
struct device *dev = &ctx->drvdata->plat_dev->dev;
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
u32 idx = 0;
int rc;
@ -708,7 +708,7 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
struct device *dev = &ctx->drvdata->plat_dev->dev;
bool is_hmac = ctx->is_hmac;
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
int idx = 0;
int rc;
@ -839,7 +839,7 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
struct device *dev = &ctx->drvdata->plat_dev->dev;
bool is_hmac = ctx->is_hmac;
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
int idx = 0;
int rc;
@ -1007,7 +1007,7 @@ static int ssi_hash_setkey(void *hash,
int blocksize = 0;
int digestsize = 0;
int i, idx = 0, rc = 0;
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
ssi_sram_addr_t larval_addr;
SSI_LOG_DEBUG("ssi_hash_setkey: start keylen: %d", keylen);
@ -1218,7 +1218,7 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
struct ssi_crypto_req ssi_req = {};
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash);
int idx = 0, rc = 0;
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen);
CHECK_AND_RETURN_UPON_FIPS_ERROR();
@ -1471,7 +1471,7 @@ static int ssi_mac_update(struct ahash_request *req)
struct device *dev = &ctx->drvdata->plat_dev->dev;
unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base);
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
int rc;
u32 idx = 0;
@ -1533,7 +1533,7 @@ static int ssi_mac_final(struct ahash_request *req)
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm);
struct device *dev = &ctx->drvdata->plat_dev->dev;
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
int idx = 0;
int rc = 0;
u32 keySize, keyLen;
@ -1647,7 +1647,7 @@ static int ssi_mac_finup(struct ahash_request *req)
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm);
struct device *dev = &ctx->drvdata->plat_dev->dev;
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
int idx = 0;
int rc = 0;
u32 key_len = 0;
@ -1721,7 +1721,7 @@ static int ssi_mac_digest(struct ahash_request *req)
struct device *dev = &ctx->drvdata->plat_dev->dev;
u32 digestsize = crypto_ahash_digestsize(tfm);
struct ssi_crypto_req ssi_req = {};
HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN];
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
u32 keyLen;
int idx = 0;
int rc;
@ -2284,7 +2284,7 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata)
struct ssi_hash_handle *hash_handle = drvdata->hash_handle;
ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr;
unsigned int larval_seq_len = 0;
HwDesc_s larval_seq[CC_DIGEST_SIZE_MAX/sizeof(u32)];
struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX/sizeof(u32)];
int rc = 0;
#if (DX_DEV_SHA_MAX > 256)
int i;
@ -2543,7 +2543,7 @@ int ssi_hash_free(struct ssi_drvdata *drvdata)
}
static void ssi_hash_create_xcbc_setup(struct ahash_request *areq,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size) {
unsigned int idx = *seq_size;
struct ahash_req_ctx *state = ahash_request_ctx(areq);
@ -2599,7 +2599,7 @@ static void ssi_hash_create_xcbc_setup(struct ahash_request *areq,
}
static void ssi_hash_create_cmac_setup(struct ahash_request *areq,
HwDesc_s desc[],
struct cc_hw_desc desc[],
unsigned int *seq_size)
{
unsigned int idx = *seq_size;
@ -2633,7 +2633,7 @@ static void ssi_hash_create_cmac_setup(struct ahash_request *areq,
static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx,
struct ssi_hash_ctx *ctx,
unsigned int flow_mode,
HwDesc_s desc[],
struct cc_hw_desc desc[],
bool is_not_last_data,
unsigned int *seq_size)
{

6
drivers/staging/ccree/ssi_ivgen.c
View File

@ -58,7 +58,7 @@ struct ssi_ivgen_ctx {
*/
static int ssi_ivgen_generate_pool(
struct ssi_ivgen_ctx *ivgen_ctx,
HwDesc_s iv_seq[],
struct cc_hw_desc iv_seq[],
unsigned int *iv_seq_len)
{
unsigned int idx = *iv_seq_len;
@ -120,7 +120,7 @@ static int ssi_ivgen_generate_pool(
int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata)
{
struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
HwDesc_s iv_seq[SSI_IVPOOL_SEQ_LEN];
struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN];
unsigned int iv_seq_len = 0;
int rc;
@ -243,7 +243,7 @@ int ssi_ivgen_getiv(
dma_addr_t iv_out_dma[],
unsigned int iv_out_dma_len,
unsigned int iv_out_size,
HwDesc_s iv_seq[],
struct cc_hw_desc iv_seq[],
unsigned int *iv_seq_len)
{
struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;

2
drivers/staging/ccree/ssi_ivgen.h
View File

@ -66,7 +66,7 @@ int ssi_ivgen_getiv(
dma_addr_t iv_out_dma[],
unsigned int iv_out_dma_len,
unsigned int iv_out_size,
HwDesc_s iv_seq[],
struct cc_hw_desc iv_seq[],
unsigned int *iv_seq_len);
#endif /*__SSI_IVGEN_H__*/

16
drivers/staging/ccree/ssi_request_mgr.c
View File

@ -72,7 +72,7 @@ do { \
#define CC_CYCLE_DESC_TAIL(cc_base_addr, desc_p, is_monitored) \
do { \
if ((is_monitored) == true) { \
HwDesc_s barrier_desc; \
struct cc_hw_desc barrier_desc; \
HW_DESC_INIT(&barrier_desc); \
HW_DESC_SET_DIN_NO_DMA(&barrier_desc, 0, 0xfffff0); \
HW_DESC_SET_DOUT_NO_DMA(&barrier_desc, 0, 0, 1); \
@ -116,10 +116,10 @@ struct ssi_request_mgr_handle {
u32 axi_completed;
u32 q_free_slots;
spinlock_t hw_lock;
HwDesc_s compl_desc;
struct cc_hw_desc compl_desc;
u8 *dummy_comp_buff;
dma_addr_t dummy_comp_buff_dma;
HwDesc_s monitor_desc;
struct cc_hw_desc monitor_desc;
volatile unsigned long monitor_lock;
#ifdef COMP_IN_WQ
struct workqueue_struct *workq;
@ -170,7 +170,7 @@ void request_mgr_fini(struct ssi_drvdata *drvdata)
int request_mgr_init(struct ssi_drvdata *drvdata)
{
#ifdef CC_CYCLE_COUNT
HwDesc_s monitor_desc[2];
struct cc_hw_desc monitor_desc[2];
struct ssi_crypto_req monitor_req = {0};
#endif
struct ssi_request_mgr_handle *req_mgr_h;
@ -259,7 +259,7 @@ req_mgr_init_err:
static inline void enqueue_seq(
void __iomem *cc_base,
HwDesc_s seq[], unsigned int seq_len)
struct cc_hw_desc seq[], unsigned int seq_len)
{
int i;
@ -357,14 +357,14 @@ static inline int request_mgr_queues_status_check(
*/
int send_request(
struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req,
HwDesc_s *desc, unsigned int len, bool is_dout)
struct cc_hw_desc *desc, unsigned int len, bool is_dout)
{
void __iomem *cc_base = drvdata->cc_base;
struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
unsigned int used_sw_slots;
unsigned int iv_seq_len = 0;
unsigned int total_seq_len = len; /*initial sequence length*/
HwDesc_s iv_seq[SSI_IVPOOL_SEQ_LEN];
struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN];
int rc;
unsigned int max_required_seq_len = (total_seq_len +
((ssi_req->ivgen_dma_addr_len == 0) ? 0 :
@ -503,7 +503,7 @@ int send_request(
* \return int Returns "0" upon success
*/
int send_request_init(
struct ssi_drvdata *drvdata, HwDesc_s *desc, unsigned int len)
struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len)
{
void __iomem *cc_base = drvdata->cc_base;
struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;

4
drivers/staging/ccree/ssi_request_mgr.h
View File

@ -40,10 +40,10 @@ int request_mgr_init(struct ssi_drvdata *drvdata);
*/
int send_request(
struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req,
HwDesc_s *desc, unsigned int len, bool is_dout);
struct cc_hw_desc *desc, unsigned int len, bool is_dout);
int send_request_init(
struct ssi_drvdata *drvdata, HwDesc_s *desc, unsigned int len);
struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len);
void complete_request(struct ssi_drvdata *drvdata);

2
drivers/staging/ccree/ssi_sram_mgr.c
View File

@ -121,7 +121,7 @@ ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, u32 size)
void ssi_sram_mgr_const2sram_desc(
const u32 *src, ssi_sram_addr_t dst,
unsigned int nelement,
HwDesc_s *seq, unsigned int *seq_len)
struct cc_hw_desc *seq, unsigned int *seq_len)
{
u32 i;
unsigned int idx = *seq_len;

2
drivers/staging/ccree/ssi_sram_mgr.h
View File

@ -75,6 +75,6 @@ ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, u32 size);
void ssi_sram_mgr_const2sram_desc(
const u32 *src, ssi_sram_addr_t dst,
unsigned int nelement,
HwDesc_s *seq, unsigned int *seq_len);
struct cc_hw_desc *seq, unsigned int *seq_len);
#endif /*__SSI_SRAM_MGR_H__*/