clk: imx: keep uart clock on during system boot
Keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -76,6 +76,20 @@ static u32 share_count_ssi1;
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static u32 share_count_ssi2;
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static u32 share_count_ssi2;
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static u32 share_count_ssi3;
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static u32 share_count_ssi3;
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static struct clk ** const uart_clks[] __initconst = {
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&clks[IMX6SLL_CLK_UART1_IPG],
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&clks[IMX6SLL_CLK_UART1_SERIAL],
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&clks[IMX6SLL_CLK_UART2_IPG],
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&clks[IMX6SLL_CLK_UART2_SERIAL],
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&clks[IMX6SLL_CLK_UART3_IPG],
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&clks[IMX6SLL_CLK_UART3_SERIAL],
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&clks[IMX6SLL_CLK_UART4_IPG],
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&clks[IMX6SLL_CLK_UART4_SERIAL],
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&clks[IMX6SLL_CLK_UART5_IPG],
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&clks[IMX6SLL_CLK_UART5_SERIAL],
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NULL
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};
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static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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{
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{
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struct device_node *np;
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struct device_node *np;
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@ -334,6 +348,8 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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clk_data.clk_num = ARRAY_SIZE(clks);
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clk_data.clk_num = ARRAY_SIZE(clks);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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imx_register_uart_clocks(uart_clks);
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/* Lower the AHB clock rate before changing the clock source. */
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/* Lower the AHB clock rate before changing the clock source. */
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clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
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clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
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