ARM: shmobile: r8a73a4: wait for completion when kicking the clock
To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to be set and to make sure the setting has taken effect, it has to be read back repeatedly until it is cleared by the hardware. This patch adds the waiting part, that was missing until now. Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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0b8eeba451
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8d27657286
@ -184,6 +184,21 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
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SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
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static int frqcr_kick_do(struct clk *clk)
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{
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int i;
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/* set KICK bit in FRQCRB to update hardware setting, check success */
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iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
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for (i = 1000; i; i--)
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if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
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cpu_relax();
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else
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return 0;
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return -ETIMEDOUT;
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}
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static struct clk *main_clks[] = {
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&extalr_clk,
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&extal1_clk,
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@ -205,12 +220,7 @@ static struct clk *main_clks[] = {
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/* DIV4 */
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static void div4_kick(struct clk *clk)
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{
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unsigned long value;
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/* set KICK bit in FRQCRB to update hardware setting */
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value = ioread32(CPG_MAP(FRQCRB));
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value |= (1 << 31);
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iowrite32(value, CPG_MAP(FRQCRB));
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frqcr_kick_do(clk);
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}
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
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