ARM: 7023/1: L2x0: Add interrupts property to OF binding
Following the discussion here: http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007301.html The L2x0 L2 Cache Controllers support a combined interrupt line which can be used for several events (e.g. read/write/parity errors on tag/data RAM, event counter increment/overflow). Unfortunately the OF binding added in c519ecf2 ("ARM: 7009/1: l2x0: Add OF based initialization") does not represent the interrupt. This patch adds an "interrupts" property to the L2x0 OF binding, representing the combined interrupt line. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Barry Song <21cnbao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -28,6 +28,7 @@ Optional properties:
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- arm,filter-ranges : <start length> Starting address and length of window to
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- arm,filter-ranges : <start length> Starting address and length of window to
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filter. Addresses in the filter window are directed to the M1 port. Other
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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addresses will go to the M0 port.
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- interrupts : 1 combined interrupt.
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Example:
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Example:
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@ -39,4 +40,5 @@ L2: cache-controller {
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arm,filter-latency = <0x80000000 0x8000000>;
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arm,filter-latency = <0x80000000 0x8000000>;
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cache-unified;
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cache-unified;
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cache-level = <2>;
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cache-level = <2>;
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interrupts = <45>;
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};
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};
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