clk: tegra: Don't warn for PLL defaults unnecessarily
If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -502,7 +502,7 @@ static void tegra210_pllcx_set_defaults(const char *name,
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pllcx->params->defaults_set = true;
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if (readl_relaxed(clk_base + pllcx->params->base_reg) &
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PLL_ENABLE) {
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PLL_ENABLE && !pllcx->params->defaults_set) {
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/* PLL is ON: only check if defaults already set */
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pllcx_check_defaults(pllcx->params);
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pr_warn("%s already enabled. Postponing set full defaults\n",
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@ -608,7 +608,6 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
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if (readl_relaxed(clk_base + plld->params->base_reg) &
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PLL_ENABLE) {
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pr_warn("PLL_D already enabled. Postponing set full defaults\n");
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/*
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* PLL is ON: check if defaults already set, then set those
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@ -625,6 +624,9 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
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_pll_misc_chk_default(clk_base, plld->params, 0, val,
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~mask & PLLD_MISC0_WRITE_MASK);
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if (!plld->params->defaults_set)
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pr_warn("PLL_D already enabled. Postponing set full defaults\n");
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/* Enable lock detect */
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mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
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val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
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@ -896,7 +898,6 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
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val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
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if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
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pr_warn("PLL_X already enabled. Postponing set full defaults\n");
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/*
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* PLL is ON: check if defaults already set, then set those
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@ -904,6 +905,8 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
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*/
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pllx_check_defaults(pllx);
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if (!pllx->params->defaults_set)
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pr_warn("PLL_X already enabled. Postponing set full defaults\n");
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/* Configure dyn ramp, disable lock override */
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writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
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@ -948,7 +951,6 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
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pllmb->params->defaults_set = true;
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if (val & PLL_ENABLE) {
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pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
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/*
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* PLL is ON: check if defaults already set, then set those
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@ -959,6 +961,8 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
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_pll_misc_chk_default(clk_base, pllmb->params, 0, val,
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~mask & PLLMB_MISC1_WRITE_MASK);
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if (!pllmb->params->defaults_set)
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pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
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/* Enable lock detect */
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val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
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val &= ~mask;
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@ -1008,13 +1012,14 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
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pllp->params->defaults_set = true;
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if (val & PLL_ENABLE) {
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pr_warn("PLL_P already enabled. Postponing set full defaults\n");
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/*
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* PLL is ON: check if defaults already set, then set those
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* that can be updated in flight.
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*/
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pllp_check_defaults(pllp, true);
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if (!pllp->params->defaults_set)
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pr_warn("PLL_P already enabled. Postponing set full defaults\n");
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/* Enable lock detect */
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val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
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@ -1069,13 +1074,14 @@ static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
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pllu->params->defaults_set = true;
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if (val & PLL_ENABLE) {
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pr_warn("PLL_U already enabled. Postponing set full defaults\n");
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/*
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* PLL is ON: check if defaults already set, then set those
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* that can be updated in flight.
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*/
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pllu_check_defaults(pllu, false);
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if (!pllu->params->defaults_set)
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pr_warn("PLL_U already enabled. Postponing set full defaults\n");
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/* Enable lock detect */
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val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]);
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