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qed: Align CIDs according to DORQ requirement

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[ Upstream commit f3e48119b97f56fb09310c95d49da122a27003d7 ]

The Doorbell HW block can be configured at a granularity
of 16 x CIDs, so we need to make sure that the actual number
of CIDs configured would be a multiplication of 16.

Today, when RoCE is enabled - given that the number is unaligned,
doorbelling the higher CIDs would fail to reach the firmware and
would eventually timeout.

Fixes: dbb799c39717 ("qed: Initialize hardware for new protocols")
Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ram Amrani 2017-03-14 15:25:58 +02:00 committed by Greg Kroah-Hartman
parent fddc3df764
commit 8de6d7b28d
1 changed files with 2 additions and 1 deletions
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3
drivers/net/ethernet/qlogic/qed/qed_cxt.c
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@ -373,8 +373,9 @@ static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
u32 align = elems_per_page * DQ_RANGE_ALIGN;
p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page);
p_conn->cid_count = roundup(p_conn->cid_count, align);
}
}