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amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use API

Browse Source 
v2: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour
v3: removed smu implementation of powerplay get_power_limit
    Resolved context clashes with other commits

Modified Files
  smu_set_power_limit()         - modifed arg0 to match Powerplay API set_power_limit
  smu_sys_get_pp_table()        - modifed signature to match Powerplay API get_pp_table
  smu_get_power_num_states()    - modifed arg0 to match Powerplay API get_pp_num_states
  smu_get_current_power_state() - modifed arg0 to match Powerplay API get_current_power_state
  smu_sys_get_pp_feature_mask() - modifed signature to match Powerplay API get_ppfeature_status
  smu_sys_set_pp_feature_mask() - modifed arg0 to match Powerplay API set_ppfeature_status

Other Changes
  added 6 above smu Powerplay functions to swsmu_dpm_funcs
  removed special smu handling of above functions and called through Powerplay API

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Darren Powell 2020-11-01 01:16:49 -04:00 committed by Alex Deucher
parent f46587bced
commit 8dfc8c53c3
3 changed files with 58 additions and 67 deletions
drivers/gpu/drm/amd/pm
amdgpu_pm.c
inc
amdgpu_smu.h
swsmu
amdgpu_smu.c

62
drivers/gpu/drm/amd/pm/amdgpu_pm.c

@ -123,6 +123,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum amd_pm_state_type pm;
int ret;
@ -135,12 +136,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
return ret;
}
if (is_support_sw_smu(adev)) {
if (adev->smu.ppt_funcs->get_current_power_state)
pm = smu_get_current_power_state(&adev->smu);
else
pm = adev->pm.dpm.user_state;
} else if (adev->powerplay.pp_funcs->get_current_power_state) {
if (pp_funcs->get_current_power_state) {
pm = amdgpu_dpm_get_current_power_state(adev);
} else {
pm = adev->pm.dpm.user_state;
@ -306,6 +302,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum amd_dpm_forced_level level;
enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
@ -341,9 +338,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
return ret;
}
if (is_support_sw_smu(adev))
current_level = smu_get_performance_level(&adev->smu);
else if (adev->powerplay.pp_funcs->get_performance_level)
if (pp_funcs->get_performance_level)
current_level = amdgpu_dpm_get_performance_level(adev);
if (current_level == level) {
@ -380,7 +375,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
pm_runtime_put_autosuspend(ddev->dev);
return -EINVAL;
}
} else if (adev->powerplay.pp_funcs->force_performance_level) {
} else if (pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
mutex_unlock(&adev->pm.mutex);
@ -411,6 +406,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
int i, buf_len, ret;
@ -423,11 +419,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
return ret;
}
if (is_support_sw_smu(adev)) {
ret = smu_get_power_num_states(&adev->smu, &data);
if (ret)
return ret;
} else if (adev->powerplay.pp_funcs->get_pp_num_states) {
if (pp_funcs->get_pp_num_states) {
amdgpu_dpm_get_pp_num_states(adev, &data);
} else {
memset(&data, 0, sizeof(data));
@ -453,8 +445,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_states_info data;
struct smu_context *smu = &adev->smu;
enum amd_pm_state_type pm = 0;
int i = 0, ret = 0;
@ -467,13 +459,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
return ret;
}
if (is_support_sw_smu(adev)) {
pm = smu_get_current_power_state(smu);
ret = smu_get_power_num_states(smu, &data);
if (ret)
return ret;
} else if (adev->powerplay.pp_funcs->get_current_power_state
&& adev->powerplay.pp_funcs->get_pp_num_states) {
if (pp_funcs->get_current_power_state
&& pp_funcs->get_pp_num_states) {
pm = amdgpu_dpm_get_current_power_state(adev);
amdgpu_dpm_get_pp_num_states(adev, &data);
}
@ -588,13 +575,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
return ret;
}
if (is_support_sw_smu(adev)) {
size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
if (size < 0)
return size;
} else if (adev->powerplay.pp_funcs->get_pp_table) {
if (adev->powerplay.pp_funcs->get_pp_table) {
size = amdgpu_dpm_get_pp_table(adev, &table);
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
@ -1008,9 +989,7 @@ static ssize_t amdgpu_get_pp_features(struct device *dev,
return ret;
}
if (is_support_sw_smu(adev))
size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
else if (adev->powerplay.pp_funcs->get_ppfeature_status)
if (adev->powerplay.pp_funcs->get_ppfeature_status)
size = amdgpu_dpm_get_ppfeature_status(adev, buf);
else
size = snprintf(buf, PAGE_SIZE, "\n");
@ -3022,6 +3001,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit = limit_type << 24;
ssize_t size;
@ -3039,8 +3019,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
if (is_support_sw_smu(adev)) {
smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@ -3057,6 +3037,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
char *buf)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit = limit_type << 24;
ssize_t size;
@ -3074,8 +3055,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
if (is_support_sw_smu(adev)) {
smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@ -3103,6 +3084,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
size_t count)
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
int err;
u32 value;
@ -3126,10 +3108,8 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
return err;
}
if (is_support_sw_smu(adev))
err = smu_set_power_limit(&adev->smu, value);
else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
if (pp_funcs && pp_funcs->set_power_limit)
err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
else
err = -EINVAL;

12
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

@ -1236,7 +1236,7 @@ int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
enum smu_ppt_limit_level limit_level);
int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
int smu_set_power_limit(void *handle, uint32_t limit);
int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
int smu_od_edit_dpm_table(struct smu_context *smu,
@ -1293,10 +1293,10 @@ extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
bool is_support_sw_smu(struct amdgpu_device *adev);
bool is_support_cclk_dpm(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
int smu_sys_get_pp_table(struct smu_context *smu, void **table);
int smu_sys_get_pp_table(void *handle, char **table);
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
int smu_get_power_num_states(void *handle, struct pp_states_info *state_info);
enum amd_pm_state_type smu_get_current_power_state(void *handle);
int smu_write_watermarks_table(struct smu_context *smu);
int smu_set_watermarks_for_clock_ranges(
struct smu_context *smu,
@ -1322,8 +1322,8 @@ enum amd_dpm_forced_level smu_get_performance_level(void *handle);
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count);
int smu_set_ac_dc(struct smu_context *smu);
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_sys_get_pp_feature_mask(void *handle, char *buf);
int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);

51
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

@ -48,9 +48,10 @@
static const struct amd_pm_funcs swsmu_pm_funcs;
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
int smu_sys_get_pp_feature_mask(void *handle, char *buf)
{
size_t size = 0;
struct smu_context *smu = handle;
int size = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
@ -64,8 +65,9 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
return size;
}
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@ -381,7 +383,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
}
int smu_get_power_num_states(struct smu_context *smu,
int smu_get_power_num_states(void *handle,
struct pp_states_info *state_info)
{
if (!state_info)
@ -417,8 +419,9 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev)
}
int smu_sys_get_pp_table(struct smu_context *smu, void **table)
int smu_sys_get_pp_table(void *handle, char **table)
{
struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
uint32_t powerplay_table_size;
@ -2085,8 +2088,9 @@ int smu_get_power_limit(struct smu_context *smu,
return ret;
}
int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
int smu_set_power_limit(void *handle, uint32_t limit)
{
struct smu_context *smu = handle;
uint32_t limit_type = limit >> 24;
int ret = 0;
@ -2663,8 +2667,9 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
return ret;
}
enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
enum amd_pm_state_type smu_get_current_power_state(void *handle)
{
struct smu_context *smu = handle;
enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@ -2750,19 +2755,25 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
static const struct amd_pm_funcs swsmu_pm_funcs = {
/* export for sysfs */
.set_fan_control_mode = smu_pp_set_fan_control_mode,
.get_fan_control_mode = smu_get_fan_control_mode,
.set_fan_speed_percent = smu_set_fan_speed_percent,
.get_fan_speed_percent = smu_get_fan_speed_percent,
.get_performance_level = smu_get_performance_level,
.get_fan_speed_rpm = smu_get_fan_speed_rpm,
.set_fan_speed_rpm = smu_set_fan_speed_rpm,
.switch_power_profile = smu_switch_power_profile,
.set_fan_control_mode = smu_pp_set_fan_control_mode,
.get_fan_control_mode = smu_get_fan_control_mode,
.set_fan_speed_percent = smu_set_fan_speed_percent,
.get_fan_speed_percent = smu_get_fan_speed_percent,
.get_performance_level = smu_get_performance_level,
.get_current_power_state = smu_get_current_power_state,
.get_fan_speed_rpm = smu_get_fan_speed_rpm,
.set_fan_speed_rpm = smu_set_fan_speed_rpm,
.get_pp_num_states = smu_get_power_num_states,
.get_pp_table = smu_sys_get_pp_table,
.switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
.set_mp1_state = smu_set_mp1_state,
.set_power_limit = smu_set_power_limit,
.set_mp1_state = smu_set_mp1_state,
/* export to DC */
.enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
.asic_reset_mode_2 = smu_mode2_reset,
.set_df_cstate = smu_set_df_cstate,
.set_xgmi_pstate = smu_set_xgmi_pstate,
.enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
.get_ppfeature_status = smu_sys_get_pp_feature_mask,
.set_ppfeature_status = smu_sys_set_pp_feature_mask,
.asic_reset_mode_2 = smu_mode2_reset,
.set_df_cstate = smu_set_df_cstate,
.set_xgmi_pstate = smu_set_xgmi_pstate,
};