sky2: use correct Inter Packet Gap at 10/100mbit
This is another fix picked out of the vendor driver. The IPG value in the serial mode register is supposed to be programmed differently at lower speeds. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -714,6 +714,20 @@ static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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}
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/* configure IPG according to used link speed */
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static void sky2_set_ipg(struct sky2_port *sky2)
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{
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u16 reg;
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reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
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reg &= ~GM_SMOD_IPG_MSK;
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if (sky2->speed > SPEED_100)
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reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
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else
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reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
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gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
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}
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/* Enable Rx/Tx */
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static void sky2_enable_rx_tx(struct sky2_port *sky2)
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{
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@ -882,7 +896,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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/* serial mode register */
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reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
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GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
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GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
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if (hw->dev[port]->mtu > ETH_DATA_LEN)
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reg |= GM_SMOD_JUMBO_ENA;
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@ -2053,6 +2067,8 @@ static void sky2_link_up(struct sky2_port *sky2)
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[FC_BOTH] = "both",
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};
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sky2_set_ipg(sky2);
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sky2_enable_rx_tx(sky2);
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gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
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@ -2290,8 +2306,11 @@ static int sky2_change_mtu(struct net_device *dev, int new_mtu)
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dev->mtu = new_mtu;
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netdev_update_features(dev);
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mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
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GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
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mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
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if (sky2->speed > SPEED_100)
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mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
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else
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mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
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if (dev->mtu > ETH_DATA_LEN)
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mode |= GM_SMOD_JUMBO_ENA;
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@ -1807,10 +1807,11 @@ enum {
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};
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#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
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#define DATA_BLIND_DEF 0x04
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#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
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#define IPG_DATA_DEF 0x1e
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#define DATA_BLIND_DEF 0x04
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#define IPG_DATA_DEF_1000 0x1e
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#define IPG_DATA_DEF_10_100 0x18
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/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
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enum {
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