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PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms

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The current default of 20ms cause some devices, which are slow to
initialize, to not show up during the bus scanning.  Change this to the
PCIe spec mandated 100ms and document this in the DT binding.

From PCIe base spec rev 3.0, chapter "6.6.1. Conventional Reset":

  To allow components to perform internal initialization, system software
  must wait a specified minimum period following the end of a Conventional
  Reset of one or more devices before it is permitted to issue
  Configuration Requests to those devices.

  With a Downstream Port that does not support Link speeds greater than 5.0
  GT/s, software must wait a minimum of 100 ms before sending a
  Configuration Request to the device immediately below that Port.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Lucas Stach 2017-02-02 18:15:31 +01:00 committed by Bjorn Helgaas
parent d9bf28e265
commit 8ed81ec82a
2 changed files with 3 additions and 2 deletions
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3
Documentation/devicetree/bindings/pci/mvebu-pci.txt
View File

@ -78,7 +78,8 @@ and the following optional properties:
multiple lanes. If this property is not found, we assume that the
value is 0.
- reset-gpios: optional gpio to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion
- reset-delay-us: delay in us to wait after reset de-assertion, if not
specified will default to 100ms, as required by the PCIe specification.
Example:

2
drivers/pci/host/pci-mvebu.c
View File

@ -1181,7 +1181,7 @@ static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
return ret;
if (port->reset_gpio) {
u32 reset_udelay = 20000;
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
of_property_read_u32(port->dn, "reset-delay-us",
&reset_udelay);