ARM: footbridge: use fixed PCI i/o mapping
Move footbridge PCI to fixed i/o mapping. io.h is still needed for the !MMU case. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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@ -431,7 +431,7 @@ config ARCH_FOOTBRIDGE
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select FOOTBRIDGE
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select GENERIC_CLOCKEVENTS
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select HAVE_IDE
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select NEED_MACH_IO_H
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select NEED_MACH_IO_H if !MMU
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select NEED_MACH_MEMORY_H
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help
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Support for systems based on the DC21285 companion chip
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@ -15,7 +15,7 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/irq.h>
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@ -26,6 +26,7 @@
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/pci.h>
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#include "common.h"
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@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(DC21285_PCI_IACK),
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.length = PCIIACK_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = PCIO_BASE,
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.pfn = __phys_to_pfn(DC21285_PCI_IO),
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.length = PCIO_SIZE,
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.type = MT_DEVICE,
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},
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#endif
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};
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@ -196,8 +192,10 @@ void __init footbridge_map_io(void)
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* Now, work out what we've got to map in addition on this
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* platform.
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*/
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if (footbridge_cfn_mode())
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if (footbridge_cfn_mode()) {
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iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
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pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
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}
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}
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void footbridge_restart(char mode, const char *cmd)
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@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
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sys->mem_offset = DC21285_PCI_MEM;
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pci_add_resource_offset(&sys->resources,
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&ioport_resource, sys->io_offset);
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pci_ioremap_io(0, DC21285_PCI_IO);
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pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
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@ -298,7 +298,7 @@ void __init dc21285_preinit(void)
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mem_size = (unsigned int)high_memory - PAGE_OFFSET;
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for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
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if (mem_mask >= mem_size)
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break;
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break;
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/*
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* These registers need to be set up whether we're the
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@ -350,14 +350,6 @@ void __init dc21285_preinit(void)
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"PCI data parity", NULL);
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if (cfn_mode) {
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static struct resource csrio;
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csrio.flags = IORESOURCE_IO;
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csrio.name = "Footbridge";
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allocate_resource(&ioport_resource, &csrio, 128,
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0xff00, 0xffff, 128, NULL, NULL);
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/*
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* Map our SDRAM at a known address in PCI space, just in case
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* the firmware had other ideas. Using a nonzero base is
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@ -365,7 +357,7 @@ void __init dc21285_preinit(void)
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* in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
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*/
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*CSR_PCICSRBASE = 0xf4000000;
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*CSR_PCICSRIOBASE = csrio.start;
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*CSR_PCICSRIOBASE = 0;
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*CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
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*CSR_PCIROMBASE = 0;
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*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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@ -17,7 +17,8 @@
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/* For NetWinder debugging */
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.macro addruart, rp, rv, tmp
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mov \rp, #0x000003f8
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orr \rv, \rp, #0xff000000 @ virtual
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orr \rv, \rp, #0xfe000000 @ virtual
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orr \rv, \rv, #0x00e00000 @ virtual
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orr \rp, \rp, #0x7c000000 @ physical
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.endm
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@ -14,18 +14,10 @@
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#ifdef CONFIG_MMU
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#define MMU_IO(a, b) (a)
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#else
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#define MMU_IO(a, b) (b)
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#endif
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#define PCIO_SIZE 0x00100000
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#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000)
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/*
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* Translation of various region addresses to virtual addresses
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* Translation of various i/o addresses to host addresses for !CONFIG_MMU
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*/
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#define PCIO_BASE 0x7c000000
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#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
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#endif
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