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Qualcomm clock updates for v6.1

Browse Source 
This introduces display clock controllers are introduces for SM6115 and
 SM8450, and SC8280XP gains a GPU clock controller.  MSM8909 and SM6375
 gains global and SMD RPM clock controller drivers.
 
 The handling of GDSCs with PWRSTS_RET was fixed, to keep the GDSC on
 while powering down the parent supply. This solved retention issues
 during suspend of USB on sc7180/7280 and SC8280XP.
 
 SM6115 and QCM2260 are moved to reuse PLL configuration. SDM660 SDCC1
 was moved to floor ops.
 
 Support for the APCS PLLs for IPQ8064, IPQ8074 and IPQ6018 was
 added/fixed. The MSM8996 CPU clocks was updated, with support for ACD
 clocks added.
 
 Support for SDM670 was added to the SDM845 Glbal clock controller and
 the RPMh clock controller driver.
 
 Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
 num_parents was done for MSM8660, MSM8916, MSM8939, MSM8960 global clock
 controllers, IPQ8064 LPASS clock controller and MSM8960 multimedia clock
 controller.
 
 Support for per-reset defined delay of was introduced.
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Merge tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

This introduces display clock controllers are introduces for SM6115 and
SM8450, and SC8280XP gains a GPU clock controller.  MSM8909 and SM6375
gains global and SMD RPM clock controller drivers.

The handling of GDSCs with PWRSTS_RET was fixed, to keep the GDSC on
while powering down the parent supply. This solved retention issues
during suspend of USB on sc7180/7280 and SC8280XP.

SM6115 and QCM2260 are moved to reuse PLL configuration. SDM660 SDCC1
was moved to floor ops.

Support for the APCS PLLs for IPQ8064, IPQ8074 and IPQ6018 was
added/fixed. The MSM8996 CPU clocks was updated, with support for ACD
clocks added.

Support for SDM670 was added to the SDM845 Glbal clock controller and
the RPMh clock controller driver.

Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for MSM8660, MSM8916, MSM8939, MSM8960 global clock
controllers, IPQ8064 LPASS clock controller and MSM8960 multimedia clock
controller.

Support for per-reset defined delay of was introduced.

* tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (93 commits)
  clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8939: use parent_hws where possible
  dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
  clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc8280xp: use retention for USB power domains
  clk: qcom: gdsc: add missing error handling
  dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos
  clk: qcom: Add global clock controller driver for SM6375
  dt-bindings: clock: add SM6375 QCOM global clock bindings
  clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit
  clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc
  clk: qcom: gdsc: Fix the handling of PWRSTS_RET support
  clk: qcom: Add SC8280XP GPU clock controller
  dt-bindings: clock: Add Qualcomm SC8280XP GPU binding
  clk: qcom: smd: Add SM6375 clocks
  dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG
  dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375
  clk: qcom: rpmhcc: add sdm670 clocks
  dt-bindings: clock: add rpmhcc bindings for sdm670
  ...
This commit is contained in:
Stephen Boyd 2022-10-03 20:48:41 -07:00
commit 8f2fcac809
85 changed files with 13661 additions and 2251 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A53 PLL Binding
maintainers:
- Sivaprakash Murugesan <sivaprak@codeaurora.org>
- Bjorn Andersson <andersson@kernel.org>
description:
The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,msm8916-a53pll
- qcom,msm8939-a53pll

9
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
View File

@ -38,6 +38,15 @@ properties:
description: child tsens device
$ref: /schemas/thermal/qcom-tsens.yaml#
clocks:
maxItems: 3
clock-names:
items:
- const: cxo
- const: pxo
- const: pll4
nvmem-cells:
minItems: 1
maxItems: 2

54
Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml Normal file
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks and resets on
MSM8660
See also:
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
allOf:
- $ref: "qcom,gcc.yaml#"
properties:
compatible:
enum:
- qcom,gcc-msm8660
clocks:
maxItems: 2
clock-names:
items:
- const: pxo
- const: cxo
required:
- compatible
unevaluatedProperties: false
examples:
# Example for GCC for MSM8974:
- |
clock-controller@900000 {
compatible = "qcom,gcc-msm8660";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
};
...

58
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml Normal file
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@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8909.
See also:
- dt-bindings/clock/qcom,gcc-msm8909.h
properties:
compatible:
const: qcom,gcc-msm8909
clocks:
items:
- description: XO source
- description: Sleep clock source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: dsi0pll
- const: dsi0pllbyte
required:
- compatible
- clocks
- clock-names
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-msm8909";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>;
clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte";
};
...

66
Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml Normal file
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@ -0,0 +1,66 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8916 or MSM8939.
See also:
- dt-bindings/clock/qcom,gcc-msm8916.h
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/reset/qcom,gcc-msm8916.h
- dt-bindings/reset/qcom,gcc-msm8939.h
properties:
compatible:
enum:
- qcom,gcc-msm8916
- qcom,gcc-msm8939
clocks:
items:
- description: XO source
- description: Sleep clock source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: External MCLK clock
- description: External Primary I2S clock
- description: External Secondary I2S clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: dsi0pll
- const: dsi0pllbyte
- const: ext_mclk
- const: ext_pri_i2s
- const: ext_sec_i2s
required:
- compatible
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@300000 {
compatible = "qcom,gcc-msm8916";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x300000 0x90000>;
};
...

21
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
View File

@ -45,29 +45,16 @@ properties:
description:
Phandle to voltage regulator providing power to the GX domain.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- vdd_gfx-supply
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

21
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
View File

@ -32,28 +32,15 @@ properties:
- const: xo
- const: sleep
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
View File

@ -49,30 +49,13 @@ properties:
- const: ufs_rx_symbol_1_clk_src
- const: ufs_tx_symbol_0_clk_src
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
View File

@ -37,32 +37,15 @@ properties:
- const: core_bi_pll_test_se # Optional clock
minItems: 2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

7
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
View File

@ -18,11 +18,7 @@ description: |
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8953.h
- dt-bindings/reset/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-mdm9607.h
@ -40,9 +36,6 @@ properties:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8660
- qcom,gcc-msm8916
- qcom,gcc-msm8939
- qcom,gcc-msm8953
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro

25
Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
View File

@ -30,32 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
View File

@ -33,32 +33,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

21
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
View File

@ -44,28 +44,15 @@ properties:
- const: ufs_phy_tx_symbol_0_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
View File

@ -32,32 +32,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
View File

@ -33,7 +33,7 @@ properties:
- description: Primary USB SuperSpeed pipe clock
- description: USB4 PHY pipegmux clock source
- description: USB4 PHY DP gmux clock source
- description: USB4 PHY sys piegmux clock source
- description: USB4 PHY sys pipegmux clock source
- description: USB4 PHY PCIe pipe clock
- description: USB4 PHY router max pipe clock
- description: Primary USB4 RX0 clock
@ -46,7 +46,7 @@ properties:
- description: Second USB4 PHY router max pipe clock
- description: Secondary USB4 RX0 clock
- description: Secondary USB4 RX1 clock
- description: Multiport USB first SupserSpeed pipe clock
- description: Multiport USB first SuperSpeed pipe clock
- description: Multiport USB second SuperSpeed pipe clock
- description: PCIe 2a pipe clock
- description: PCIe 2b pipe clock
@ -56,30 +56,17 @@ properties:
- description: First EMAC controller reference clock
- description: Second EMAC controller reference clock
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
maxItems: 389
required:
- compatible
- clocks
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

84
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
View File

@ -19,51 +19,67 @@ description: |
properties:
compatible:
const: qcom,gcc-sdm845
enum:
- qcom,gcc-sdm670
- qcom,gcc-sdm845
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
minItems: 3
maxItems: 5
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: pcie_0_pipe_clk
- const: pcie_1_pipe_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
minItems: 3
maxItems: 5
power-domains:
maxItems: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
const: qcom,gcc-sdm670
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- if:
properties:
compatible:
contains:
const: qcom,gcc-sdm845
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: pcie_0_pipe_clk
- const: pcie_1_pipe_clk
unevaluatedProperties: false
examples:
# Example for GCC for SDM845:

21
Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
View File

@ -35,28 +35,15 @@ properties:
- const: core_bi_pll_test_se # Optional clock
minItems: 2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

21
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
View File

@ -20,9 +20,6 @@ properties:
compatible:
const: qcom,gcc-sdx65
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
@ -43,25 +40,15 @@ properties:
- const: core_bi_pll_test_se # Optional clock
minItems: 5
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
View File

@ -30,32 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
View File

@ -30,32 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
View File

@ -32,32 +32,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View File

@ -31,32 +31,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

25
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View File

@ -31,32 +31,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

21
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
View File

@ -54,28 +54,15 @@ properties:
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

21
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
View File

@ -46,28 +46,15 @@ properties:
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
minItems: 2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

2
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
View File

@ -17,6 +17,7 @@ description: |
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
dt-bindings/clock/qcom,gpucc-sc8280xp.h
dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
@ -28,6 +29,7 @@ properties:
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
- qcom,sc8280xp-gpucc
- qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc

207
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
View File

@ -31,30 +31,12 @@ properties:
- qcom,mmcc-sdm660
clocks:
items:
- description: Board XO source
- description: Board sleep source
- description: Global PLL 0 clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
- description: DisplayPort phy PLL vco clock
- description: DisplayPort phy PLL link clock
minItems: 8
maxItems: 10
clock-names:
items:
- const: xo
- const: sleep
- const: gpll0
- const: dsi0dsi
- const: dsi0byte
- const: dsi1dsi
- const: dsi1byte
- const: hdmipll
- const: dpvco
- const: dplink
minItems: 8
maxItems: 10
'#clock-cells':
const: 1
@ -85,16 +67,179 @@ required:
additionalProperties: false
if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8998
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-apq8064
- qcom,mmcc-msm8960
then:
properties:
clocks:
items:
- description: Board PXO source
- description: PLL 3 clock
- description: PLL 3 Vote clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: DSI phy instance 2 dsi clock
- description: DSI phy instance 2 byte clock
- description: HDMI phy PLL clock
then:
required:
- clocks
- clock-names
clock-names:
items:
- const: pxo
- const: pll3
- const: pll8_vote
- const: dsi1pll
- const: dsi1pllbyte
- const: dsi2pll
- const: dsi2pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-msm8994
- qcom,mmcc-msm8998
- qcom,mmcc-sdm630
- qcom,mmcc-sdm660
then:
required:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8994
then:
properties:
clocks:
items:
- description: Board XO source
- description: Global PLL 0 clock
- description: MMSS NoC AHB clock
- description: GFX3D clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
clock-names:
items:
- const: xo
- const: gpll0
- const: mmssnoc_ahb
- const: oxili_gfx3d_clk_src
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8996
then:
properties:
clocks:
items:
- description: Board XO source
- description: Global PLL 0 clock
- description: MMSS NoC AHB clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
clock-names:
items:
- const: xo
- const: gpll0
- const: gcc_mmss_noc_cfg_ahb_clk
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8998
then:
properties:
clocks:
items:
- description: Board XO source
- description: Global PLL 0 clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
- description: DisplayPort phy PLL link clock
- description: DisplayPort phy PLL vco clock
- description: Test clock
clock-names:
items:
- const: xo
- const: gpll0
- const: dsi0dsi
- const: dsi0byte
- const: dsi1dsi
- const: dsi1byte
- const: hdmipll
- const: dplink
- const: dpvco
- const: core_bi_pll_test_se
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-sdm630
- qcom,mmcc-sdm660
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board sleep source
- description: Global PLL 0 clock
- description: Global PLL 0 DIV clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: DisplayPort phy PLL link clock
- description: DisplayPort phy PLL vco clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: gpll0
- const: gpll0_div
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: dp_link_2x_clk_divsel_five
- const: dp_vco_divided_clk_src_mux
examples:
# Example for MMCC for MSM8960:

15
Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml
View File

@ -26,22 +26,18 @@ properties:
clocks:
items:
- description: Primary PLL clock for power cluster (little)
- description: Primary PLL clock for perf cluster (big)
- description: Alternate PLL clock for power cluster (little)
- description: Alternate PLL clock for perf cluster (big)
- description: XO source
clock-names:
items:
- const: pwrcl_pll
- const: perfcl_pll
- const: pwrcl_alt_pll
- const: perfcl_alt_pll
- const: xo
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
@ -51,4 +47,7 @@ examples:
compatible = "qcom,msm8996-apcc";
reg = <0x6400000 0x90000>;
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};

2
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
View File

@ -29,6 +29,7 @@ properties:
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
@ -43,6 +44,7 @@ properties:
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
- qcom,rpmcc-sm6375
- const: qcom,rpmcc
'#clock-cells':

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -21,6 +21,7 @@ properties:
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
- qcom,sc8280xp-rpmh-clk
- qcom,sdm670-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk

6
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
View File

@ -36,13 +36,11 @@ properties:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
- description: LPASS cc register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
- const: cc
required:
- compatible
@ -59,8 +57,8 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
reg-names = "qdsp6ss", "top_cc", "cc";
reg = <0x03000000 0x40>, <0x03c04000 0x4>;
reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;

26
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
View File

@ -22,6 +22,8 @@ properties:
clock-names: true
reg: true
compatible:
enum:
- qcom,sc7280-lpassaoncc
@ -38,8 +40,14 @@ properties:
'#power-domain-cells':
const: 1
reg:
maxItems: 1
'#reset-cells':
const: 1
qcom,adsp-pil-mode:
description:
Indicates if the LPASS would be brought out of reset using
peripheral loader.
type: boolean
required:
- compatible
@ -69,6 +77,11 @@ allOf:
items:
- const: bi_tcxo
- const: lpass_aon_cc_main_rcg_clk_src
reg:
items:
- description: lpass core cc register
- description: lpass audio csr register
- if:
properties:
compatible:
@ -90,6 +103,8 @@ allOf:
- const: bi_tcxo_ao
- const: iface
reg:
maxItems: 1
- if:
properties:
compatible:
@ -108,6 +123,8 @@ allOf:
items:
- const: bi_tcxo
reg:
maxItems: 1
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
@ -116,13 +133,15 @@ examples:
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0x3300000 0x30000>;
reg = <0x3300000 0x30000>,
<0x32a9000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
- |
@ -165,6 +184,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
qcom,adsp-pil-mode;
#clock-cells = <1>;
#power-domain-cells = <1>;
};

70
Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml Normal file
View File

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock Controller for SM6115
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm display clock control module which supports the clocks and
power domains on SM6115.
See also:
include/dt-bindings/clock/qcom,sm6115-dispcc.h
properties:
compatible:
enum:
- qcom,sm6115-dispcc
clocks:
items:
- description: Board XO source
- description: Board sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: GPLL0 DISP DIV clock from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
clock-controller@5f00000 {
compatible = "qcom,sm6115-dispcc";
reg = <0x5f00000 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

52
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml Normal file
View File

@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6375
See also:
- dt-bindings/clock/qcom,sm6375-gcc.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sm6375-gcc
clocks:
items:
- description: Board XO source
- description: Board XO Active-Only source
- description: Sleep clock source
required:
- compatible
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@1400000 {
compatible = "qcom,sm6375-gcc";
reg = <0x01400000 0x1f0000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

98
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml Normal file
View File

@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8450
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8450.
See also:
include/dt-bindings/clock/qcom,sm8450-dispcc.h
properties:
compatible:
enum:
- qcom,sm8450-dispcc
clocks:
minItems: 3
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8450-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8450_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

47
drivers/clk/qcom/Kconfig
View File

@ -180,6 +180,14 @@ config MSM_GCC_8660
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
config MSM_GCC_8909
tristate "MSM8909 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on msm8909 devices.
Say Y if you want to use devices such as UART, SPI, I2C, USB,
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8916
tristate "MSM8916 Global Clock Controller"
select QCOM_GDSC
@ -445,6 +453,14 @@ config SC_GPUCC_7280
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SC_GPUCC_8280XP
tristate "SC8280XP Graphics Clock Controller"
select SC_GCC_8280XP
help
Support for the graphics clock controller on SC8280XP devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SC_LPASSCC_7280
tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller"
select SC_GCC_7280
@ -545,10 +561,10 @@ config QCS_Q6SSTOP_404
controller to reset the Q6SSTOP subsystem.
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
tristate "SDM845/SDM670 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SDM845 devices.
Support for the global clock controller on SDM845 and SDM670 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2C, USB, UFS, SDDC, PCIe, etc.
@ -616,6 +632,15 @@ config SM_CAMCC_8450
Support for the camera clock controller on SM8450 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on SM_GCC_6115
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM6115/SM4250 devices.
Say Y if you want to support display devices and functionality such as
splash screen
config SM_DISPCC_6125
tristate "SM6125 Display Clock Controller"
depends on SM_GCC_6125
@ -643,8 +668,18 @@ config SM_DISPCC_6350
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_8450
tristate "SM8450 Display Clock Controller"
depends on SM_GCC_8450
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM8450 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_GCC_6115
tristate "SM6115 and SM4250 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SM6115 and SM4250 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
@ -665,6 +700,14 @@ config SM_GCC_6350
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_6375
tristate "SM6375 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SM6375 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS etc.
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help

5
drivers/clk/qcom/Makefile
View File

@ -32,6 +32,7 @@ obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o
obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
obj-$(CONFIG_MSM_GCC_8939) += gcc-msm8939.o
obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o
@ -71,6 +72,7 @@ obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o
obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o
obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
@ -90,12 +92,15 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o
obj-$(CONFIG_SM_GCC_6375) += gcc-sm6375.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o

4
drivers/clk/qcom/a53-pll.c
View File

@ -127,7 +127,9 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
if (!init.name)
return -ENOMEM;
init.parent_names = (const char *[]){ "xo" };
init.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
};
init.num_parents = 1;
init.ops = &clk_pll_sr2_ops;
pll->clkr.hw.init = &init;

33
drivers/clk/qcom/apss-ipq-pll.c
View File

@ -2,6 +2,7 @@
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@ -36,12 +37,28 @@ static struct clk_alpha_pll ipq_pll = {
},
};
static const struct alpha_pll_config ipq_pll_config = {
static const struct alpha_pll_config ipq6018_pll_config = {
.l = 0x37,
.config_ctl_val = 0x04141200,
.config_ctl_hi_val = 0x0,
.config_ctl_val = 0x240d4828,
.config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
.aux2_output_mask = BIT(2),
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.test_ctl_val = 0x1c0000C0,
.test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config ipq8074_pll_config = {
.l = 0x48,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
.aux2_output_mask = BIT(2),
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.test_ctl_val = 0x1c000000,
.test_ctl_hi_val = 0x4000,
};
static const struct regmap_config ipq_pll_regmap_config = {
@ -54,6 +71,7 @@ static const struct regmap_config ipq_pll_regmap_config = {
static int apss_ipq_pll_probe(struct platform_device *pdev)
{
const struct alpha_pll_config *ipq_pll_config;
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
@ -67,7 +85,11 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
ipq_pll_config = of_device_get_match_data(&pdev->dev);
if (!ipq_pll_config)
return -ENODEV;
clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
if (ret)
@ -78,7 +100,8 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
}
static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq6018-a53pll" },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

15
drivers/clk/qcom/apss-ipq6018.c
View File

@ -16,7 +16,7 @@
#include "clk-regmap.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
#include "clk-regmap-mux.h"
#include "clk-rcg.h"
enum {
P_XO,
@ -33,16 +33,15 @@ static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
{ P_APSS_PLL_EARLY, 5 },
};
static struct clk_regmap_mux apcs_alias0_clk_src = {
.reg = 0x0050,
.width = 3,
.shift = 7,
static struct clk_rcg2 apcs_alias0_clk_src = {
.cmd_rcgr = 0x0050,
.hid_width = 5,
.parent_map = parents_apcs_alias0_clk_src_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apcs_alias0_clk_src",
.parent_data = parents_apcs_alias0_clk_src,
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
.num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
.ops = &clk_rcg2_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
@ -57,7 +56,7 @@ static struct clk_branch apcs_alias0_core_clk = {
.parent_hws = (const struct clk_hw *[]){
&apcs_alias0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},

66
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -27,6 +27,7 @@
# define PLL_VOTE_FSM_RESET BIT(21)
# define PLL_UPDATE BIT(22)
# define PLL_UPDATE_BYPASS BIT(23)
# define PLL_FSM_LEGACY_MODE BIT(24)
# define PLL_OFFLINE_ACK BIT(28)
# define ALPHA_PLL_ACK_LATCH BIT(29)
# define PLL_ACTIVE_FLAG BIT(30)
@ -166,6 +167,27 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x28,
[PLL_OFF_TEST_CTL_U] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1C,
[PLL_OFF_STATUS] = 0x20,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@ -1102,6 +1124,10 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
}
if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
PLL_FSM_LEGACY_MODE);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
PLL_UPDATE_BYPASS);
@ -2088,7 +2114,7 @@ static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
return ret;
}
static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
@ -2117,9 +2143,12 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
/* Place the PLL mode in STANDBY */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
if (reset)
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
}
static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct clk_hw *p;
@ -2139,11 +2168,31 @@ static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
if (ret)
return ret;
alpha_pll_lucid_evo_disable(hw);
_alpha_pll_lucid_evo_disable(hw, reset);
return 0;
}
static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
{
_alpha_pll_lucid_evo_disable(hw, false);
}
static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
{
return _alpha_pll_lucid_evo_prepare(hw, false);
}
static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
{
_alpha_pll_lucid_evo_disable(hw, true);
}
static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
{
return _alpha_pll_lucid_evo_prepare(hw, true);
}
static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@ -2191,6 +2240,17 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
.prepare = alpha_pll_reset_lucid_evo_prepare,
.enable = alpha_pll_lucid_evo_enable,
.disable = alpha_pll_reset_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{

8
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -19,6 +19,8 @@ enum {
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_MAX,
};
@ -70,9 +72,10 @@ struct clk_alpha_pll {
const struct pll_vco *vco_table;
size_t num_vco;
#define SUPPORTS_OFFLINE_REQ BIT(0)
#define SUPPORTS_FSM_MODE BIT(2)
#define SUPPORTS_OFFLINE_REQ BIT(0)
#define SUPPORTS_FSM_MODE BIT(2)
#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
#define SUPPORTS_FSM_LEGACY_MODE BIT(4)
u8 flags;
struct clk_regmap clkr;
@ -155,6 +158,7 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;

345
drivers/clk/qcom/clk-cpu-8996.c
View File

@ -49,6 +49,7 @@
* detect voltage droops.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
@ -59,9 +60,10 @@
#include "clk-alpha-pll.h"
#include "clk-regmap.h"
#include "clk-regmap-mux.h"
enum _pmux_input {
DIV_2_INDEX = 0,
SMUX_INDEX = 0,
PLL_INDEX,
ACD_INDEX,
ALT_INDEX,
@ -75,6 +77,8 @@ enum _pmux_input {
#define ALT_PLL_OFFSET 0x100
#define SSSCTL_OFFSET 0x160
#define PMUX_MASK 0x3
static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
@ -111,16 +115,8 @@ static const struct alpha_pll_config hfpll_config = {
.early_output_mask = BIT(3),
};
static struct clk_alpha_pll perfcl_pll = {
.offset = PERFCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "perfcl_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
static const struct clk_parent_data pll_parent[] = {
{ .fw_name = "xo" },
};
static struct clk_alpha_pll pwrcl_pll = {
@ -129,12 +125,80 @@ static struct clk_alpha_pll pwrcl_pll = {
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "pwrcl_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_huayra_ops,
},
};
static struct clk_alpha_pll perfcl_pll = {
.offset = PERFCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "perfcl_pll",
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_huayra_ops,
},
};
static struct clk_fixed_factor pwrcl_pll_postdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "pwrcl_pll_postdiv",
.parent_data = &(const struct clk_parent_data){
.hw = &pwrcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor perfcl_pll_postdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "perfcl_pll_postdiv",
.parent_data = &(const struct clk_parent_data){
.hw = &perfcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor perfcl_pll_acd = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "perfcl_pll_acd",
.parent_data = &(const struct clk_parent_data){
.hw = &perfcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor pwrcl_pll_acd = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "pwrcl_pll_acd",
.parent_data = &(const struct clk_parent_data){
.hw = &pwrcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct pll_vco alt_pll_vco_modes[] = {
VCO(3, 250000000, 500000000),
VCO(2, 500000000, 750000000),
@ -153,20 +217,6 @@ static const struct alpha_pll_config altpll_config = {
.early_output_mask = BIT(3),
};
static struct clk_alpha_pll perfcl_alt_pll = {
.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_alt_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
static struct clk_alpha_pll pwrcl_alt_pll = {
.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
@ -175,71 +225,79 @@ static struct clk_alpha_pll pwrcl_alt_pll = {
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_alt_pll",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
struct clk_cpu_8996_mux {
static struct clk_alpha_pll perfcl_alt_pll = {
.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_alt_pll",
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
struct clk_cpu_8996_pmux {
u32 reg;
u8 shift;
u8 width;
struct notifier_block nb;
struct clk_hw *pll;
struct clk_hw *pll_div_2;
struct clk_regmap clkr;
};
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data);
#define to_clk_cpu_8996_mux_nb(_nb) \
container_of(_nb, struct clk_cpu_8996_mux, nb)
#define to_clk_cpu_8996_pmux_nb(_nb) \
container_of(_nb, struct clk_cpu_8996_pmux, nb)
static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
static inline struct clk_cpu_8996_pmux *to_clk_cpu_8996_pmux_hw(struct clk_hw *hw)
{
return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
return container_of(to_clk_regmap(hw), struct clk_cpu_8996_pmux, clkr);
}
static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
u32 mask = GENMASK(cpuclk->width - 1, 0);
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw);
u32 val;
regmap_read(clkr->regmap, cpuclk->reg, &val);
val >>= cpuclk->shift;
return val & mask;
return FIELD_GET(PMUX_MASK, val);
}
static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift);
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw);
u32 val;
val = index;
val <<= cpuclk->shift;
val = FIELD_PREP(PMUX_MASK, index);
return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val);
}
static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw,
static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
struct clk_hw *parent = cpuclk->pll;
struct clk_hw *parent;
if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {
if (req->rate < (DIV_2_THRESHOLD / 2))
return -EINVAL;
if (req->rate < (DIV_2_THRESHOLD / 2))
return -EINVAL;
parent = cpuclk->pll_div_2;
}
if (req->rate < DIV_2_THRESHOLD)
parent = clk_hw_get_parent_by_index(hw, SMUX_INDEX);
else
parent = clk_hw_get_parent_by_index(hw, ACD_INDEX);
if (!parent)
return -EINVAL;
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
req->best_parent_hw = parent;
@ -247,83 +305,83 @@ static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw,
return 0;
}
static const struct clk_ops clk_cpu_8996_mux_ops = {
.set_parent = clk_cpu_8996_mux_set_parent,
.get_parent = clk_cpu_8996_mux_get_parent,
.determine_rate = clk_cpu_8996_mux_determine_rate,
static const struct clk_ops clk_cpu_8996_pmux_ops = {
.set_parent = clk_cpu_8996_pmux_set_parent,
.get_parent = clk_cpu_8996_pmux_get_parent,
.determine_rate = clk_cpu_8996_pmux_determine_rate,
};
static struct clk_cpu_8996_mux pwrcl_smux = {
static const struct clk_parent_data pwrcl_smux_parents[] = {
{ .fw_name = "xo" },
{ .hw = &pwrcl_pll_postdiv.hw },
};
static const struct clk_parent_data perfcl_smux_parents[] = {
{ .fw_name = "xo" },
{ .hw = &perfcl_pll_postdiv.hw },
};
static struct clk_regmap_mux pwrcl_smux = {
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_smux",
.parent_names = (const char *[]){
"xo",
"pwrcl_pll_main",
},
.num_parents = 2,
.ops = &clk_cpu_8996_mux_ops,
.parent_data = pwrcl_smux_parents,
.num_parents = ARRAY_SIZE(pwrcl_smux_parents),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_cpu_8996_mux perfcl_smux = {
static struct clk_regmap_mux perfcl_smux = {
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_smux",
.parent_names = (const char *[]){
"xo",
"perfcl_pll_main",
},
.num_parents = 2,
.ops = &clk_cpu_8996_mux_ops,
.parent_data = perfcl_smux_parents,
.num_parents = ARRAY_SIZE(perfcl_smux_parents),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_cpu_8996_mux pwrcl_pmux = {
static const struct clk_hw *pwrcl_pmux_parents[] = {
[SMUX_INDEX] = &pwrcl_smux.clkr.hw,
[PLL_INDEX] = &pwrcl_pll.clkr.hw,
[ACD_INDEX] = &pwrcl_pll_acd.hw,
[ALT_INDEX] = &pwrcl_alt_pll.clkr.hw,
};
static const struct clk_hw *perfcl_pmux_parents[] = {
[SMUX_INDEX] = &perfcl_smux.clkr.hw,
[PLL_INDEX] = &perfcl_pll.clkr.hw,
[ACD_INDEX] = &perfcl_pll_acd.hw,
[ALT_INDEX] = &perfcl_alt_pll.clkr.hw,
};
static struct clk_cpu_8996_pmux pwrcl_pmux = {
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
.pll_div_2 = &pwrcl_smux.clkr.hw,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_pmux",
.parent_names = (const char *[]){
"pwrcl_smux",
"pwrcl_pll",
"pwrcl_pll_acd",
"pwrcl_alt_pll",
},
.num_parents = 4,
.ops = &clk_cpu_8996_mux_ops,
.parent_hws = pwrcl_pmux_parents,
.num_parents = ARRAY_SIZE(pwrcl_pmux_parents),
.ops = &clk_cpu_8996_pmux_ops,
/* CPU clock is critical and should never be gated */
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
};
static struct clk_cpu_8996_mux perfcl_pmux = {
static struct clk_cpu_8996_pmux perfcl_pmux = {
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
.pll_div_2 = &perfcl_smux.clkr.hw,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_pmux",
.parent_names = (const char *[]){
"perfcl_smux",
"perfcl_pll",
"perfcl_pll_acd",
"perfcl_alt_pll",
},
.num_parents = 4,
.ops = &clk_cpu_8996_mux_ops,
.parent_hws = perfcl_pmux_parents,
.num_parents = ARRAY_SIZE(perfcl_pmux_parents),
.ops = &clk_cpu_8996_pmux_ops,
/* CPU clock is critical and should never be gated */
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
@ -338,15 +396,22 @@ static const struct regmap_config cpu_msm8996_regmap_config = {
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
static struct clk_hw *cpu_msm8996_hw_clks[] = {
&pwrcl_pll_postdiv.hw,
&perfcl_pll_postdiv.hw,
&pwrcl_pll_acd.hw,
&perfcl_pll_acd.hw,
};
static struct clk_regmap *cpu_msm8996_clks[] = {
&perfcl_pll.clkr,
&pwrcl_pll.clkr,
&perfcl_alt_pll.clkr,
&perfcl_pll.clkr,
&pwrcl_alt_pll.clkr,
&perfcl_smux.clkr,
&perfcl_alt_pll.clkr,
&pwrcl_smux.clkr,
&perfcl_pmux.clkr,
&perfcl_smux.clkr,
&pwrcl_pmux.clkr,
&perfcl_pmux.clkr,
};
static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
@ -354,67 +419,33 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
{
int i, ret;
perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
"perfcl_pll",
CLK_SET_RATE_PARENT,
1, 2);
if (IS_ERR(perfcl_smux.pll)) {
dev_err(dev, "Failed to initialize perfcl_pll_main\n");
return PTR_ERR(perfcl_smux.pll);
}
pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
"pwrcl_pll",
CLK_SET_RATE_PARENT,
1, 2);
if (IS_ERR(pwrcl_smux.pll)) {
dev_err(dev, "Failed to initialize pwrcl_pll_main\n");
clk_hw_unregister(perfcl_smux.pll);
return PTR_ERR(pwrcl_smux.pll);
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) {
ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);
if (ret)
return ret;
}
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
if (ret) {
clk_hw_unregister(perfcl_smux.pll);
clk_hw_unregister(pwrcl_smux.pll);
if (ret)
return ret;
}
}
clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
/* Enable alt PLLs */
clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
devm_clk_notifier_register(dev, pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
devm_clk_notifier_register(dev, perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
return ret;
}
static int qcom_cpu_clk_msm8996_unregister_clks(void)
{
int ret = 0;
ret = clk_notifier_unregister(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
if (ret)
return ret;
ret = clk_notifier_unregister(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
if (ret)
return ret;
clk_hw_unregister(perfcl_smux.pll);
clk_hw_unregister(pwrcl_smux.pll);
return 0;
}
#define CPU_AFINITY_MASK 0xFFF
#define PWRCL_CPU_REG_MASK 0x3
#define PERFCL_CPU_REG_MASK 0x103
@ -456,22 +487,22 @@ static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base)
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb);
struct clk_notifier_data *cnd = data;
int ret;
switch (event) {
case PRE_RATE_CHANGE:
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
qcom_cpu_clk_msm8996_acd_init(base);
break;
case POST_RATE_CHANGE:
if (cnd->new_rate < DIV_2_THRESHOLD)
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
DIV_2_INDEX);
ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw,
SMUX_INDEX);
else
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
ACD_INDEX);
ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw,
ACD_INDEX);
break;
default:
ret = 0;
@ -513,11 +544,6 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
}
static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev)
{
return qcom_cpu_clk_msm8996_unregister_clks();
}
static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
{ .compatible = "qcom,msm8996-apcc" },
{}
@ -526,7 +552,6 @@ MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table);
static struct platform_driver qcom_cpu_clk_msm8996_driver = {
.probe = qcom_cpu_clk_msm8996_driver_probe,
.remove = qcom_cpu_clk_msm8996_driver_remove,
.driver = {
.name = "qcom-msm8996-apcc",
.of_match_table = qcom_cpu_clk_msm8996_match_table,

1
drivers/clk/qcom/clk-rcg.h
View File

@ -167,6 +167,7 @@ struct clk_rcg2_gfx3d {
extern const struct clk_ops clk_rcg2_ops;
extern const struct clk_ops clk_rcg2_floor_ops;
extern const struct clk_ops clk_rcg2_mux_closest_ops;
extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;
extern const struct clk_ops clk_byte2_ops;

7
drivers/clk/qcom/clk-rcg2.c
View File

@ -509,6 +509,13 @@ const struct clk_ops clk_rcg2_floor_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
const struct clk_ops clk_rcg2_mux_closest_ops = {
.determine_rate = __clk_mux_determine_rate_closest,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
};
EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
struct frac_entry {
int num;
int den;

25
drivers/clk/qcom/clk-rpmh.c
View File

@ -195,10 +195,6 @@ static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
{
int ret;
/* Nothing required to be done if already off or on */
if (enable == c->state)
return 0;
c->state = enable ? c->valid_state_mask : 0;
c->aggr_state = c->state | c->peer->state;
c->peer->aggr_state = c->aggr_state;
@ -382,6 +378,26 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
};
static struct clk_hw *sdm670_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_CE_CLK] = &sdm845_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
.clks = sdm670_rpmh_clocks,
.num_clks = ARRAY_SIZE(sdm670_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
@ -715,6 +731,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
{ .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
{ .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670},
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},

83
drivers/clk/qcom/clk-smd-rpm.c
View File

@ -417,6 +417,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
@ -427,6 +428,40 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 192
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);
static struct clk_smd_rpm *msm8909_clks[] = {
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
.clks = msm8909_clks,
.num_clks = ARRAY_SIZE(msm8909_clks),
};
static struct clk_smd_rpm *msm8916_clks[] = {
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
@ -787,7 +822,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
};
DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);
static struct clk_smd_rpm *qcs404_clks[] = {
@ -1085,13 +1119,54 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
.num_clks = ARRAY_SIZE(sm6115_clks),
};
/* SM6375 */
DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 0);
DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 1);
DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1);
static struct clk_smd_rpm *sm6375_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
[RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
[RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
[RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
[RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
[RPM_SMD_MMRT_CLK] = &sm6375_mmrt_clk,
[RPM_SMD_MMRT_A_CLK] = &sm6375_mmrt_a_clk,
[RPM_SMD_MMNRT_CLK] = &sm6375_mmnrt_clk,
[RPM_SMD_MMNRT_A_CLK] = &sm6375_mmnrt_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
[RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
[RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
[RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
[RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
[RPM_SMD_BIMC_FREQ_LOG] = &sm6375_bimc_freq_log,
};
static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
.clks = sm6375_clks,
.num_clks = ARRAY_SIZE(sm6375_clks),
};
/* QCM2290 */
DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000);
DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk,
QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk,
@ -1146,6 +1221,7 @@ static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
{ .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
{ .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
{ .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
@ -1160,6 +1236,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
{ .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },
{ .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },
{ .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);

608
drivers/clk/qcom/dispcc-sm6115.c Normal file
View File

@ -0,0 +1,608 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Based on dispcc-qcm2290.c
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
DT_GPLL0_DISP_DIV,
};
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco spark_vco[] = {
{ 500000000, 1000000000, 2 },
};
/* 768MHz configuration */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x28,
.alpha = 0x0,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_disp_cc_pll0_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv disp_cc_pll0_out_main = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_disp_cc_pll0_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0_out_main",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_DISP_DIV },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0_out_main.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .index = DT_SLEEP_CLK, },
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x20bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
.ops = &clk_byte2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x20d4,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x2154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x20d8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x2074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x205c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x208c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x20a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32764, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_sleep_clk_src = {
.cmd_rcgr = 0x6050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x2018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x2010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_names = (const char *[]){
"disp_cc_mdss_rot_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0x6068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc *disp_cc_sm6115_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static struct clk_regmap *disp_cc_sm6115_clocks[] = {
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL0_OUT_MAIN] = &disp_cc_pll0_out_main.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
};
static const struct regmap_config disp_cc_sm6115_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm6115_desc = {
.config = &disp_cc_sm6115_regmap_config,
.clks = disp_cc_sm6115_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6115_clocks),
.gdscs = disp_cc_sm6115_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6115_gdscs),
};
static const struct of_device_id disp_cc_sm6115_match_table[] = {
{ .compatible = "qcom,sm6115-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm6115_match_table);
static int disp_cc_sm6115_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm6115_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
}
return ret;
}
static struct platform_driver disp_cc_sm6115_driver = {
.probe = disp_cc_sm6115_probe,
.driver = {
.name = "dispcc-sm6115",
.of_match_table = disp_cc_sm6115_match_table,
},
};
module_platform_driver(disp_cc_sm6115_driver);
MODULE_DESCRIPTION("Qualcomm SM6115 Display Clock controller");
MODULE_LICENSE("GPL");

1829
drivers/clk/qcom/dispcc-sm8450.c Normal file
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File diff suppressed because it is too large Load Diff

330
drivers/clk/qcom/gcc-msm8660.c
View File

@ -34,7 +34,9 @@ static struct clk_pll pll8 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
.parent_names = (const char *[]){ "pxo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
@ -45,7 +47,9 @@ static struct clk_regmap pll8_vote = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
.parent_names = (const char *[]){ "pll8" },
.parent_hws = (const struct clk_hw*[]){
&pll8.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@ -62,9 +66,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PLL8, 3 }
};
static const char * const gcc_pxo_pll8[] = {
"pxo",
"pll8_vote",
static const struct clk_parent_data gcc_pxo_pll8[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
@ -73,10 +77,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_CXO, 5 }
};
static const char * const gcc_pxo_pll8_cxo[] = {
"pxo",
"pll8_vote",
"cxo",
static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
{ .fw_name = "cxo", .name = "cxo_board" },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
@ -122,8 +126,8 @@ static struct clk_rcg gsbi1_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -138,8 +142,8 @@ static struct clk_branch gsbi1_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
.parent_names = (const char *[]){
"gsbi1_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -173,8 +177,8 @@ static struct clk_rcg gsbi2_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -189,8 +193,8 @@ static struct clk_branch gsbi2_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
.parent_names = (const char *[]){
"gsbi2_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -224,8 +228,8 @@ static struct clk_rcg gsbi3_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -240,8 +244,8 @@ static struct clk_branch gsbi3_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_clk",
.parent_names = (const char *[]){
"gsbi3_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi3_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -275,8 +279,8 @@ static struct clk_rcg gsbi4_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -291,8 +295,8 @@ static struct clk_branch gsbi4_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
.parent_names = (const char *[]){
"gsbi4_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -326,8 +330,8 @@ static struct clk_rcg gsbi5_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -342,8 +346,8 @@ static struct clk_branch gsbi5_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
.parent_names = (const char *[]){
"gsbi5_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -377,8 +381,8 @@ static struct clk_rcg gsbi6_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -393,8 +397,8 @@ static struct clk_branch gsbi6_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_clk",
.parent_names = (const char *[]){
"gsbi6_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -428,8 +432,8 @@ static struct clk_rcg gsbi7_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -444,8 +448,8 @@ static struct clk_branch gsbi7_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_clk",
.parent_names = (const char *[]){
"gsbi7_uart_src",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
@ -479,8 +483,8 @@ static struct clk_rcg gsbi8_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -495,7 +499,9 @@ static struct clk_branch gsbi8_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_clk",
.parent_names = (const char *[]){ "gsbi8_uart_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi8_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -528,8 +534,8 @@ static struct clk_rcg gsbi9_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -544,7 +550,9 @@ static struct clk_branch gsbi9_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_clk",
.parent_names = (const char *[]){ "gsbi9_uart_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi9_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -577,8 +585,8 @@ static struct clk_rcg gsbi10_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -593,7 +601,9 @@ static struct clk_branch gsbi10_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_clk",
.parent_names = (const char *[]){ "gsbi10_uart_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi10_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -626,8 +636,8 @@ static struct clk_rcg gsbi11_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -642,7 +652,9 @@ static struct clk_branch gsbi11_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_clk",
.parent_names = (const char *[]){ "gsbi11_uart_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi11_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -675,8 +687,8 @@ static struct clk_rcg gsbi12_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -691,7 +703,9 @@ static struct clk_branch gsbi12_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_clk",
.parent_names = (const char *[]){ "gsbi12_uart_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi12_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -737,8 +751,8 @@ static struct clk_rcg gsbi1_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -753,7 +767,9 @@ static struct clk_branch gsbi1_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
.parent_names = (const char *[]){ "gsbi1_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi1_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -786,8 +802,8 @@ static struct clk_rcg gsbi2_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -802,7 +818,9 @@ static struct clk_branch gsbi2_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
.parent_names = (const char *[]){ "gsbi2_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi2_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -835,8 +853,8 @@ static struct clk_rcg gsbi3_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -851,7 +869,9 @@ static struct clk_branch gsbi3_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_clk",
.parent_names = (const char *[]){ "gsbi3_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi3_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -884,8 +904,8 @@ static struct clk_rcg gsbi4_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -900,7 +920,9 @@ static struct clk_branch gsbi4_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
.parent_names = (const char *[]){ "gsbi4_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi4_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -933,8 +955,8 @@ static struct clk_rcg gsbi5_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -949,7 +971,9 @@ static struct clk_branch gsbi5_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
.parent_names = (const char *[]){ "gsbi5_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi5_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -982,8 +1006,8 @@ static struct clk_rcg gsbi6_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -998,7 +1022,9 @@ static struct clk_branch gsbi6_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_clk",
.parent_names = (const char *[]){ "gsbi6_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi6_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1031,8 +1057,8 @@ static struct clk_rcg gsbi7_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1047,7 +1073,9 @@ static struct clk_branch gsbi7_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_clk",
.parent_names = (const char *[]){ "gsbi7_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi7_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1080,8 +1108,8 @@ static struct clk_rcg gsbi8_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1096,7 +1124,9 @@ static struct clk_branch gsbi8_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_clk",
.parent_names = (const char *[]){ "gsbi8_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi8_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1129,8 +1159,8 @@ static struct clk_rcg gsbi9_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1145,7 +1175,9 @@ static struct clk_branch gsbi9_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_clk",
.parent_names = (const char *[]){ "gsbi9_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi9_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1178,8 +1210,8 @@ static struct clk_rcg gsbi10_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1194,7 +1226,9 @@ static struct clk_branch gsbi10_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_clk",
.parent_names = (const char *[]){ "gsbi10_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi10_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1227,8 +1261,8 @@ static struct clk_rcg gsbi11_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1243,7 +1277,9 @@ static struct clk_branch gsbi11_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_clk",
.parent_names = (const char *[]){ "gsbi11_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi11_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1276,8 +1312,8 @@ static struct clk_rcg gsbi12_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1292,7 +1328,9 @@ static struct clk_branch gsbi12_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_clk",
.parent_names = (const char *[]){ "gsbi12_qup_src" },
.parent_hws = (const struct clk_hw*[]){
&gsbi12_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1338,8 +1376,8 @@ static struct clk_rcg gp0_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_names = gcc_pxo_pll8_cxo,
.num_parents = 3,
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@ -1354,7 +1392,9 @@ static struct clk_branch gp0_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
.parent_names = (const char *[]){ "gp0_src" },
.parent_hws = (const struct clk_hw*[]){
&gp0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1387,8 +1427,8 @@ static struct clk_rcg gp1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_names = gcc_pxo_pll8_cxo,
.num_parents = 3,
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@ -1403,7 +1443,9 @@ static struct clk_branch gp1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
.parent_names = (const char *[]){ "gp1_src" },
.parent_hws = (const struct clk_hw*[]){
&gp1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1436,8 +1478,8 @@ static struct clk_rcg gp2_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_names = gcc_pxo_pll8_cxo,
.num_parents = 3,
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@ -1452,7 +1494,9 @@ static struct clk_branch gp2_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
.parent_names = (const char *[]){ "gp2_src" },
.parent_hws = (const struct clk_hw*[]){
&gp2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1488,8 +1532,8 @@ static struct clk_rcg prng_src = {
.clkr.hw = {
.init = &(struct clk_init_data){
.name = "prng_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
@ -1504,7 +1548,9 @@ static struct clk_branch prng_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
.parent_names = (const char *[]){ "prng_src" },
.parent_hws = (const struct clk_hw*[]){
&prng_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
@ -1547,8 +1593,8 @@ static struct clk_rcg sdc1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@ -1562,7 +1608,9 @@ static struct clk_branch sdc1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
.parent_names = (const char *[]){ "sdc1_src" },
.parent_hws = (const struct clk_hw*[]){
&sdc1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1595,8 +1643,8 @@ static struct clk_rcg sdc2_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@ -1610,7 +1658,9 @@ static struct clk_branch sdc2_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc2_clk",
.parent_names = (const char *[]){ "sdc2_src" },
.parent_hws = (const struct clk_hw*[]){
&sdc2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1643,8 +1693,8 @@ static struct clk_rcg sdc3_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@ -1658,7 +1708,9 @@ static struct clk_branch sdc3_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc3_clk",
.parent_names = (const char *[]){ "sdc3_src" },
.parent_hws = (const struct clk_hw*[]){
&sdc3_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1691,8 +1743,8 @@ static struct clk_rcg sdc4_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc4_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@ -1706,7 +1758,9 @@ static struct clk_branch sdc4_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc4_clk",
.parent_names = (const char *[]){ "sdc4_src" },
.parent_hws = (const struct clk_hw*[]){
&sdc4_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1739,8 +1793,8 @@ static struct clk_rcg sdc5_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc5_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@ -1754,7 +1808,9 @@ static struct clk_branch sdc5_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc5_clk",
.parent_names = (const char *[]){ "sdc5_src" },
.parent_hws = (const struct clk_hw*[]){
&sdc5_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1792,8 +1848,8 @@ static struct clk_rcg tsif_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@ -1808,7 +1864,9 @@ static struct clk_branch tsif_ref_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk",
.parent_names = (const char *[]){ "tsif_ref_src" },
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1846,8 +1904,8 @@ static struct clk_rcg usb_hs1_xcvr_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@ -1862,7 +1920,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
.parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
.parent_hws = (const struct clk_hw*[]){
&usb_hs1_xcvr_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1895,16 +1955,14 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
static struct clk_branch usb_fs1_xcvr_fs_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 15,
@ -1913,7 +1971,9 @@ static struct clk_branch usb_fs1_xcvr_fs_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_clk",
.parent_names = usb_fs1_xcvr_fs_src_p,
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1928,7 +1988,9 @@ static struct clk_branch usb_fs1_system_clk = {
.enable_reg = 0x296c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_names = usb_fs1_xcvr_fs_src_p,
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_fs1_system_clk",
.ops = &clk_branch_ops,
@ -1962,16 +2024,14 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
static struct clk_branch usb_fs2_xcvr_fs_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 12,
@ -1980,7 +2040,9 @@ static struct clk_branch usb_fs2_xcvr_fs_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_clk",
.parent_names = usb_fs2_xcvr_fs_src_p,
.parent_hws = (const struct clk_hw*[]){
&usb_fs2_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1996,7 +2058,9 @@ static struct clk_branch usb_fs2_system_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_system_clk",
.parent_names = usb_fs2_xcvr_fs_src_p,
.parent_hws = (const struct clk_hw*[]){
&usb_fs2_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,

2731
drivers/clk/qcom/gcc-msm8909.c Normal file
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1102
drivers/clk/qcom/gcc-msm8916.c
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552
drivers/clk/qcom/gcc-msm8939.c
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File diff suppressed because it is too large Load Diff

436
drivers/clk/qcom/gcc-msm8960.c
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File diff suppressed because it is too large Load Diff

56
drivers/clk/qcom/gcc-qcm2290.c
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@ -54,33 +54,9 @@ static const struct pll_vco spark_vco[] = {
{ 750000000, 1500000000, 1 },
};
static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1C,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1C,
[PLL_OFF_STATUS] = 0x20,
},
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
@ -106,7 +82,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
.post_div_table = post_div_table_gpll0_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
.width = 4,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_aux2",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@ -117,7 +93,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
static struct clk_alpha_pll gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(1),
@ -147,7 +123,7 @@ static struct clk_alpha_pll gpll10 = {
.offset = 0xa000,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(10),
@ -179,7 +155,7 @@ static struct clk_alpha_pll gpll11 = {
.offset = 0xb000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x79000,
@ -197,7 +173,7 @@ static struct clk_alpha_pll gpll11 = {
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
@ -223,7 +199,7 @@ static struct clk_alpha_pll_postdiv gpll3_out_main = {
.post_div_table = post_div_table_gpll3_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main),
.width = 4,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw },
@ -234,7 +210,7 @@ static struct clk_alpha_pll_postdiv gpll3_out_main = {
static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
@ -251,7 +227,7 @@ static struct clk_alpha_pll gpll4 = {
static struct clk_alpha_pll gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(5),
@ -268,7 +244,7 @@ static struct clk_alpha_pll gpll5 = {
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
@ -294,7 +270,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
.post_div_table = post_div_table_gpll6_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
.width = 4,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
@ -305,7 +281,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
@ -340,7 +316,7 @@ static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x79000,
@ -367,7 +343,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
.post_div_table = post_div_table_gpll8_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
.width = 4,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll8_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
@ -393,7 +369,7 @@ static struct clk_alpha_pll gpll9 = {
.offset = 0x9000,
.vco_table = brammo_vco,
.num_vco = ARRAY_SIZE(brammo_vco),
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
@ -419,7 +395,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
.post_div_table = post_div_table_gpll9_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
.width = 2,
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll9_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },

2
drivers/clk/qcom/gcc-sc7180.c
View File

@ -2224,7 +2224,7 @@ static struct gdsc usb30_prim_gdsc = {
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {

6
drivers/clk/qcom/gcc-sc7280.c
View File

@ -3108,7 +3108,7 @@ static struct gdsc gcc_pcie_1_gdsc = {
.pd = {
.name = "gcc_pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};
@ -3126,7 +3126,7 @@ static struct gdsc gcc_usb30_prim_gdsc = {
.pd = {
.name = "gcc_usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};
@ -3135,7 +3135,7 @@ static struct gdsc gcc_usb30_sec_gdsc = {
.pd = {
.name = "gcc_usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};

20
drivers/clk/qcom/gcc-sc8280xp.c
View File

@ -6768,6 +6768,10 @@ static struct gdsc pcie_1_tunnel_gdsc = {
.flags = VOTABLE,
};
/*
* The Qualcomm PCIe driver does not yet implement suspend so to keep the
* PCIe power domains always-on for now.
*/
static struct gdsc pcie_2a_gdsc = {
.gdscr = 0x9d004,
.collapse_ctrl = 0x52128,
@ -6776,7 +6780,7 @@ static struct gdsc pcie_2a_gdsc = {
.name = "pcie_2a_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc pcie_2b_gdsc = {
@ -6787,7 +6791,7 @@ static struct gdsc pcie_2b_gdsc = {
.name = "pcie_2b_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc pcie_3a_gdsc = {
@ -6798,7 +6802,7 @@ static struct gdsc pcie_3a_gdsc = {
.name = "pcie_3a_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc pcie_3b_gdsc = {
@ -6809,7 +6813,7 @@ static struct gdsc pcie_3b_gdsc = {
.name = "pcie_3b_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc pcie_4_gdsc = {
@ -6820,7 +6824,7 @@ static struct gdsc pcie_4_gdsc = {
.name = "pcie_4_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc ufs_card_gdsc = {
@ -6844,7 +6848,7 @@ static struct gdsc usb30_mp_gdsc = {
.pd = {
.name = "usb30_mp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc usb30_prim_gdsc = {
@ -6852,7 +6856,7 @@ static struct gdsc usb30_prim_gdsc = {
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc usb30_sec_gdsc = {
@ -6860,7 +6864,7 @@ static struct gdsc usb30_sec_gdsc = {
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct clk_regmap *gcc_sc8280xp_clocks[] = {

2
drivers/clk/qcom/gcc-sdm660.c
View File

@ -757,7 +757,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_floor_ops,
},
};

400
drivers/clk/qcom/gcc-sdm845.c
View File

@ -31,6 +31,7 @@ enum {
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_MAIN,
P_SLEEP_CLK,
};
@ -68,6 +69,23 @@ static struct clk_alpha_pll gpll4 = {
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x13000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
@ -194,6 +212,19 @@ static const struct clk_parent_data gcc_parent_data_10[] = {
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
@ -233,6 +264,26 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = {
.cmd_rcgr = 0x4815c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk_src",
.parent_data = gcc_parent_data_8_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
@ -656,6 +707,54 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x26028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x26010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
@ -705,6 +804,31 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
F(105495, P_BI_TCXO, 2, 1, 91),
{ }
@ -1283,6 +1407,28 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = {
},
};
/*
* The source clock frequencies are different for SDM670; define a child clock
* pointing to the source clock that uses SDM670 frequencies.
*/
static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x44038,
.halt_check = BRANCH_VOTED,
@ -2353,6 +2499,55 @@ static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x26004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
@ -2415,6 +2610,28 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
},
};
/*
* The source clock frequencies are different for SDM670; define a child clock
* pointing to the source clock that uses SDM670 frequencies.
*/
static struct clk_branch gcc_sdm670_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdm670_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x414c,
.halt_check = BRANCH_HALT_VOTED,
@ -3308,6 +3525,155 @@ static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sdm670_clocks[] = {
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr,
[GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
[GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
[GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] =
&gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
[GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
[GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
[GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
[GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
[GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL6] = &gpll6.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
};
static struct clk_regmap *gcc_sdm845_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
@ -3533,6 +3899,22 @@ static const struct qcom_reset_map gcc_sdm845_resets[] = {
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
};
static struct gdsc *gcc_sdm670_gdscs[] = {
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
};
static struct gdsc *gcc_sdm845_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
@ -3563,6 +3945,17 @@ static const struct regmap_config gcc_sdm845_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sdm670_desc = {
.config = &gcc_sdm845_regmap_config,
.clks = gcc_sdm670_clocks,
.num_clks = ARRAY_SIZE(gcc_sdm670_clocks),
/* Snapdragon 670 can function without its own exclusive resets. */
.resets = gcc_sdm845_resets,
.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
.gdscs = gcc_sdm670_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
};
static const struct qcom_cc_desc gcc_sdm845_desc = {
.config = &gcc_sdm845_regmap_config,
.clks = gcc_sdm845_clocks,
@ -3574,7 +3967,8 @@ static const struct qcom_cc_desc gcc_sdm845_desc = {
};
static const struct of_device_id gcc_sdm845_match_table[] = {
{ .compatible = "qcom,gcc-sdm845" },
{ .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc },
{ .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
@ -3600,6 +3994,7 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
static int gcc_sdm845_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *gcc_desc;
struct regmap *regmap;
int ret;
@ -3616,7 +4011,8 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
gcc_desc = of_device_get_match_data(&pdev->dev);
return qcom_cc_really_probe(pdev, gcc_desc, regmap);
}
static struct platform_driver gcc_sdm845_driver = {

48
drivers/clk/qcom/gcc-sm6115.c
View File

@ -57,7 +57,7 @@ static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
@ -83,7 +83,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
.post_div_table = post_div_table_gpll0_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_aux2",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@ -92,18 +92,6 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
},
};
/* listed as BRAMMO, but it doesn't really match */
static const u8 clk_gpll9_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1C,
[PLL_OFF_STATUS] = 0x20,
};
static const struct clk_div_table post_div_table_gpll0_out_main[] = {
{ 0x0, 1 },
{ }
@ -115,7 +103,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_main = {
.post_div_table = post_div_table_gpll0_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@ -137,7 +125,7 @@ static struct clk_alpha_pll gpll10 = {
.offset = 0xa000,
.vco_table = gpll10_vco,
.num_vco = ARRAY_SIZE(gpll10_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(10),
@ -163,7 +151,7 @@ static struct clk_alpha_pll_postdiv gpll10_out_main = {
.post_div_table = post_div_table_gpll10_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll10_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
@ -189,7 +177,7 @@ static struct clk_alpha_pll gpll11 = {
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(11),
@ -215,7 +203,7 @@ static struct clk_alpha_pll_postdiv gpll11_out_main = {
.post_div_table = post_div_table_gpll11_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll11_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
@ -229,7 +217,7 @@ static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
@ -248,7 +236,7 @@ static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
@ -274,7 +262,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_main = {
.post_div_table = post_div_table_gpll4_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
@ -287,7 +275,7 @@ static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
@ -313,7 +301,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
.post_div_table = post_div_table_gpll6_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
@ -326,7 +314,7 @@ static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
@ -352,7 +340,7 @@ static struct clk_alpha_pll_postdiv gpll7_out_main = {
.post_div_table = post_div_table_gpll7_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll7_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
@ -380,7 +368,7 @@ static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x79000,
@ -407,7 +395,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
.post_div_table = post_div_table_gpll8_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll8_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
@ -431,7 +419,7 @@ static struct clk_alpha_pll gpll9 = {
.offset = 0x9000,
.vco_table = gpll9_vco,
.num_vco = ARRAY_SIZE(gpll9_vco),
.regs = clk_gpll9_regs,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
@ -457,7 +445,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
.post_div_table = post_div_table_gpll9_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
.width = 2,
.regs = clk_gpll9_regs,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll9_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },

2
drivers/clk/qcom/gcc-sm6350.c
View File

@ -2316,7 +2316,7 @@ static struct gdsc usb30_prim_gdsc = {
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc ufs_phy_gdsc = {

3931
drivers/clk/qcom/gcc-sm6375.c Normal file
View File

File diff suppressed because it is too large Load Diff

35
drivers/clk/qcom/gdsc.c
View File

@ -368,6 +368,16 @@ static int _gdsc_disable(struct gdsc *sc)
if (sc->pwrsts & PWRSTS_OFF)
gdsc_clear_mem_on(sc);
/*
* If the GDSC supports only a Retention state, apart from ON,
* leave it in ON state.
* There is no SW control to transition the GDSC into
* Retention state. This happens in HW when the parent
* domain goes down to a Low power state
*/
if (sc->pwrsts == PWRSTS_RET_ON)
return 0;
ret = gdsc_toggle_logic(sc, GDSC_OFF);
if (ret)
return ret;
@ -439,11 +449,8 @@ static int gdsc_init(struct gdsc *sc)
/* ...and the power-domain */
ret = gdsc_pm_runtime_get(sc);
if (ret) {
if (sc->rsupply)
regulator_disable(sc->rsupply);
return ret;
}
if (ret)
goto err_disable_supply;
/*
* Votable GDSCs can be ON due to Vote from other masters.
@ -452,14 +459,14 @@ static int gdsc_init(struct gdsc *sc)
if (sc->flags & VOTABLE) {
ret = gdsc_update_collapse_bit(sc, false);
if (ret)
return ret;
goto err_put_rpm;
}
/* Turn on HW trigger mode if supported */
if (sc->flags & HW_CTRL) {
ret = gdsc_hwctrl(sc, true);
if (ret < 0)
return ret;
goto err_put_rpm;
}
/*
@ -486,9 +493,21 @@ static int gdsc_init(struct gdsc *sc)
sc->pd.power_off = gdsc_disable;
if (!sc->pd.power_on)
sc->pd.power_on = gdsc_enable;
pm_genpd_init(&sc->pd, NULL, !on);
ret = pm_genpd_init(&sc->pd, NULL, !on);
if (ret)
goto err_put_rpm;
return 0;
err_put_rpm:
if (on)
gdsc_pm_runtime_put(sc);
err_disable_supply:
if (on && sc->rsupply)
regulator_disable(sc->rsupply);
return ret;
}
int gdsc_register(struct gdsc_desc *desc,

5
drivers/clk/qcom/gdsc.h
View File

@ -49,6 +49,11 @@ struct gdsc {
const u8 pwrsts;
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF BIT(0)
/*
* There is no SW control to transition a GDSC into
* PWRSTS_RET. This happens in HW when the parent
* domain goes down to a low power state
*/
#define PWRSTS_RET BIT(1)
#define PWRSTS_ON BIT(2)
#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)

461
drivers/clk/qcom/gpucc-sc8280xp.c Normal file
View File

@ -0,0 +1,461 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GCC_GPU_GPLL0_CLK_SRC,
P_GCC_GPU_GPLL0_DIV_CLK_SRC,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1800000000, 0 },
};
static struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1c,
.alpha = 0xa555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1A,
.alpha = 0xaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(200000000, P_GCC_GPU_GPLL0_CLK_SRC, 3, 0, 0),
F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0),
F(400000000, P_GCC_GPU_GPLL0_CLK_SRC, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x117c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x11c0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x11bc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x1178,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1178,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x1204,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1204,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gpu_cc_sc8280xp_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
};
static struct gdsc cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | RETAIN_FF_ENABLE,
};
static struct gdsc *gpu_cc_sc8280xp_gdscs[] = {
[GPU_CC_CX_GDSC] = &cx_gdsc,
[GPU_CC_GX_GDSC] = &gx_gdsc,
};
static const struct regmap_config gpu_cc_sc8280xp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8030,
.fast_io = true,
};
static struct qcom_cc_desc gpu_cc_sc8280xp_desc = {
.config = &gpu_cc_sc8280xp_regmap_config,
.clks = gpu_cc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sc8280xp_clocks),
.gdscs = gpu_cc_sc8280xp_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sc8280xp_gdscs),
};
static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep the clocks always-ON
* GPU_CC_CB_CLK, GPU_CC_CXO_CLK
*/
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
}
static const struct of_device_id gpu_cc_sc8280xp_match_table[] = {
{ .compatible = "qcom,sc8280xp-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sc8280xp_match_table);
static struct platform_driver gpu_cc_sc8280xp_driver = {
.probe = gpu_cc_sc8280xp_probe,
.driver = {
.name = "gpu_cc-sc8280xp",
.of_match_table = gpu_cc_sc8280xp_match_table,
},
};
module_platform_driver(gpu_cc_sc8280xp_driver);
MODULE_DESCRIPTION("Qualcomm SC8280XP GPU clock controller");
MODULE_LICENSE("GPL");

84
drivers/clk/qcom/lcc-ipq806x.c
View File

@ -22,6 +22,7 @@
#include "clk-branch.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "reset.h"
static struct clk_pll pll4 = {
.l_reg = 0x4,
@ -33,7 +34,9 @@ static struct clk_pll pll4 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll4",
.parent_names = (const char *[]){ "pxo" },
.parent_data = &(const struct clk_parent_data) {
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
@ -63,9 +66,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PLL4, 2 }
};
static const char * const lcc_pxo_pll4[] = {
"pxo",
"pll4_vote",
static const struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_mi2s[] = {
@ -130,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "mi2s_osr_src",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static const char * const lcc_mi2s_parents[] = {
"mi2s_osr_src",
};
static struct clk_branch mi2s_osr_clk = {
.halt_reg = 0x50,
.halt_bit = 1,
@ -151,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = {
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "mi2s_osr_clk",
.parent_names = lcc_mi2s_parents,
.parent_hws = (const struct clk_hw*[]) {
&mi2s_osr_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -166,7 +167,9 @@ static struct clk_regmap_div mi2s_div_clk = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mi2s_div_clk",
.parent_names = lcc_mi2s_parents,
.parent_hws = (const struct clk_hw*[]) {
&mi2s_osr_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
@ -182,7 +185,9 @@ static struct clk_branch mi2s_bit_div_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "mi2s_bit_div_clk",
.parent_names = (const char *[]){ "mi2s_div_clk" },
.parent_hws = (const struct clk_hw*[]) {
&mi2s_div_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -190,6 +195,10 @@ static struct clk_branch mi2s_bit_div_clk = {
},
};
static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
{ .hw = &mi2s_bit_div_clk.clkr.hw, },
{ .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" },
};
static struct clk_regmap_mux mi2s_bit_clk = {
.reg = 0x48,
@ -198,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_clk = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mi2s_bit_clk",
.parent_names = (const char *[]){
"mi2s_bit_div_clk",
"mi2s_codec_clk",
},
.num_parents = 2,
.parent_data = lcc_mi2s_bit_div_codec_clk,
.num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
@ -244,8 +250,8 @@ static struct clk_rcg pcm_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcm_src",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@ -261,7 +267,9 @@ static struct clk_branch pcm_clk_out = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcm_clk_out",
.parent_names = (const char *[]){ "pcm_src" },
.parent_hws = (const struct clk_hw*[]) {
&pcm_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -269,6 +277,11 @@ static struct clk_branch pcm_clk_out = {
},
};
static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
{ .hw = &pcm_clk_out.clkr.hw, },
{ .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
};
static struct clk_regmap_mux pcm_clk = {
.reg = 0x54,
.shift = 10,
@ -276,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcm_clk",
.parent_names = (const char *[]){
"pcm_clk_out",
"pcm_codec_clk",
},
.num_parents = 2,
.parent_data = lcc_pcm_clk_out_codec_clk,
.num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
@ -324,18 +334,14 @@ static struct clk_rcg spdif_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "spdif_src",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static const char * const lcc_spdif_parents[] = {
"spdif_src",
};
static struct clk_branch spdif_clk = {
.halt_reg = 0xd4,
.halt_bit = 1,
@ -345,7 +351,9 @@ static struct clk_branch spdif_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "spdif_clk",
.parent_names = lcc_spdif_parents,
.parent_hws = (const struct clk_hw*[]) {
&spdif_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -383,8 +391,8 @@ static struct clk_rcg ahbix_clk = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "ahbix",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_lcc_ops,
},
},
@ -405,6 +413,10 @@ static struct clk_regmap *lcc_ipq806x_clks[] = {
[AHBIX_CLK] = &ahbix_clk.clkr,
};
static const struct qcom_reset_map lcc_ipq806x_resets[] = {
[LCC_PCM_RESET] = { 0x54, 13 },
};
static const struct regmap_config lcc_ipq806x_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -417,6 +429,8 @@ static const struct qcom_cc_desc lcc_ipq806x_desc = {
.config = &lcc_ipq806x_regmap_config,
.clks = lcc_ipq806x_clks,
.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
.resets = lcc_ipq806x_resets,
.num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
};
static const struct of_device_id lcc_ipq806x_match_table[] = {

211
drivers/clk/qcom/lcc-msm8960.c
View File

@ -33,7 +33,9 @@ static struct clk_pll pll4 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll4",
.parent_names = (const char *[]){ "pxo" },
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
@ -49,9 +51,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PLL4, 2 }
};
static const char * const lcc_pxo_pll4[] = {
"pxo",
"pll4_vote",
static const struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_osr_492[] = {
@ -86,112 +88,7 @@ static struct freq_tbl clk_tbl_aif_osr_393[] = {
{ }
};
static struct clk_rcg mi2s_osr_src = {
.ns_reg = 0x48,
.md_reg = 0x4c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_aif_osr_393,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "mi2s_osr_src",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static const char * const lcc_mi2s_parents[] = {
"mi2s_osr_src",
};
static struct clk_branch mi2s_osr_clk = {
.halt_reg = 0x50,
.halt_bit = 1,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "mi2s_osr_clk",
.parent_names = lcc_mi2s_parents,
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div mi2s_div_clk = {
.reg = 0x48,
.shift = 10,
.width = 4,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "mi2s_div_clk",
.parent_names = lcc_mi2s_parents,
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
},
};
static struct clk_branch mi2s_bit_div_clk = {
.halt_reg = 0x50,
.halt_bit = 0,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "mi2s_bit_div_clk",
.parent_names = (const char *[]){ "mi2s_div_clk" },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_mux mi2s_bit_clk = {
.reg = 0x48,
.shift = 14,
.width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mi2s_bit_clk",
.parent_names = (const char *[]){
"mi2s_bit_div_clk",
"mi2s_codec_clk",
},
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
#define CLK_AIF_OSR_SRC(prefix, _ns, _md) \
static struct clk_rcg prefix##_osr_src = { \
.ns_reg = _ns, \
.md_reg = _md, \
@ -217,85 +114,103 @@ static struct clk_rcg prefix##_osr_src = { \
.enable_mask = BIT(9), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_src", \
.parent_names = lcc_pxo_pll4, \
.num_parents = 2, \
.parent_data = lcc_pxo_pll4, \
.num_parents = ARRAY_SIZE(lcc_pxo_pll4), \
.ops = &clk_rcg_ops, \
.flags = CLK_SET_RATE_GATE, \
}, \
}, \
}; \
\
static const char * const lcc_##prefix##_parents[] = { \
#prefix "_osr_src", \
}; \
\
#define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_osr_clk = { \
.halt_reg = hr, \
.halt_bit = 1, \
.halt_check = BRANCH_HALT_ENABLE, \
.clkr = { \
.enable_reg = _ns, \
.enable_mask = BIT(21), \
.enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_clk", \
.parent_names = lcc_##prefix##_parents, \
.parent_hws = (const struct clk_hw*[]){ \
&prefix##_osr_src.clkr.hw, \
}, \
.num_parents = 1, \
.ops = &clk_branch_ops, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
}; \
\
#define CLK_AIF_OSR_DIV_CLK(prefix, _ns, _width) \
static struct clk_regmap_div prefix##_div_clk = { \
.reg = _ns, \
.shift = 10, \
.width = 8, \
.width = _width, \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_div_clk", \
.parent_names = lcc_##prefix##_parents, \
.parent_hws = (const struct clk_hw*[]){ \
&prefix##_osr_src.clkr.hw, \
}, \
.num_parents = 1, \
.ops = &clk_regmap_div_ops, \
}, \
}, \
}; \
\
#define CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_bit_div_clk = { \
.halt_reg = hr, \
.halt_bit = 0, \
.halt_check = BRANCH_HALT_ENABLE, \
.clkr = { \
.enable_reg = _ns, \
.enable_mask = BIT(19), \
.enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_div_clk", \
.parent_names = (const char *[]){ \
#prefix "_div_clk" \
}, \
.parent_hws = (const struct clk_hw*[]){ \
&prefix##_div_clk.clkr.hw, \
}, \
.num_parents = 1, \
.ops = &clk_branch_ops, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
}; \
\
#define CLK_AIF_OSR_BIT_CLK(prefix, _ns, _shift) \
static struct clk_regmap_mux prefix##_bit_clk = { \
.reg = _ns, \
.shift = 18, \
.shift = _shift, \
.width = 1, \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_clk", \
.parent_names = (const char *[]){ \
#prefix "_bit_div_clk", \
#prefix "_codec_clk", \
.parent_data = (const struct clk_parent_data[]){ \
{ .hw = &prefix##_bit_div_clk.clkr.hw, }, \
{ .fw_name = #prefix "_codec_clk", \
.name = #prefix "_codec_clk", }, \
}, \
.num_parents = 2, \
.ops = &clk_regmap_mux_closest_ops, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
}
};
CLK_AIF_OSR_SRC(mi2s, 0x48, 0x4c)
CLK_AIF_OSR_CLK(mi2s, 0x48, 0x50, 17)
CLK_AIF_OSR_DIV_CLK(mi2s, 0x48, 4)
CLK_AIF_OSR_BIT_DIV_CLK(mi2s, 0x48, 0x50, 15)
CLK_AIF_OSR_BIT_CLK(mi2s, 0x48, 14)
#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
CLK_AIF_OSR_SRC(prefix, _ns, _md) \
CLK_AIF_OSR_CLK(prefix, _ns, hr, 21) \
CLK_AIF_OSR_DIV_CLK(prefix, _ns, 8) \
CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, 19) \
CLK_AIF_OSR_BIT_CLK(prefix, _ns, 18)
CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
@ -361,8 +276,8 @@ static struct clk_rcg pcm_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcm_src",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@ -378,7 +293,9 @@ static struct clk_branch pcm_clk_out = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcm_clk_out",
.parent_names = (const char *[]){ "pcm_src" },
.parent_hws = (const struct clk_hw*[]){
&pcm_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -393,9 +310,9 @@ static struct clk_regmap_mux pcm_clk = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcm_clk",
.parent_names = (const char *[]){
"pcm_clk_out",
"pcm_codec_clk",
.parent_data = (const struct clk_parent_data[]){
{ .hw = &pcm_clk_out.clkr.hw },
{ .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
},
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
@ -429,18 +346,14 @@ static struct clk_rcg slimbus_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "slimbus_src",
.parent_names = lcc_pxo_pll4,
.num_parents = 2,
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static const char * const lcc_slimbus_parents[] = {
"slimbus_src",
};
static struct clk_branch audio_slimbus_clk = {
.halt_reg = 0xd4,
.halt_bit = 0,
@ -450,7 +363,9 @@ static struct clk_branch audio_slimbus_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "audio_slimbus_clk",
.parent_names = lcc_slimbus_parents,
.parent_hws = (const struct clk_hw*[]){
&slimbus_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -467,7 +382,9 @@ static struct clk_branch sps_slimbus_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "sps_slimbus_clk",
.parent_names = lcc_slimbus_parents,
.parent_hws = (const struct clk_hw*[]){
&slimbus_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,

66
drivers/clk/qcom/lpassaudiocc-sc7280.c
View File

@ -12,6 +12,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include "clk-alpha-pll.h"
@ -22,6 +23,7 @@
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
@ -38,6 +40,32 @@ static const struct pll_vco zonda_vco[] = {
{ 595200000UL, 3600000000UL, 0 },
};
static struct clk_branch lpass_q6ss_ahbm_clk = {
.halt_reg = 0x901c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x901c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_q6ss_ahbs_clk = {
.halt_reg = 0x9020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
/* 1128.96MHz configuration */
static const struct alpha_pll_config lpass_audio_cc_pll_config = {
.l = 0x3a,
@ -221,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
.parent_data = lpass_aon_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -614,6 +642,11 @@ static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = {
.flags = RETAIN_FF_ENABLE,
};
static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
[LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
[LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
};
static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] = {
[LPASS_AON_CC_AUDIO_HM_H_CLK] = &lpass_aon_cc_audio_hm_h_clk.clkr,
[LPASS_AON_CC_VA_MEM0_CLK] = &lpass_aon_cc_va_mem0_clk.clkr,
@ -659,12 +692,30 @@ static struct regmap_config lpass_audio_cc_sc7280_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
};
static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_audio_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
};
static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
};
static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.resets = lpass_audio_cc_sc7280_resets,
.num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
};
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpassaudiocc" },
{ }
@ -741,6 +792,13 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
return ret;
}
ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
pm_runtime_disable(&pdev->dev);
return ret;
}
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
@ -785,6 +843,12 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
if (ret)
return ret;
if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
lpass_audio_cc_sc7280_regmap_config.name = "cc";
desc = &lpass_cc_sc7280_desc;
return qcom_cc_probe(pdev, desc);
}
lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";
lpass_audio_cc_sc7280_regmap_config.max_register = 0xa0008;
desc = &lpass_aon_cc_sc7280_desc;

44
drivers/clk/qcom/lpasscc-sc7280.c
View File

@ -17,32 +17,6 @@
#include "clk-branch.h"
#include "common.h"
static struct clk_branch lpass_q6ss_ahbm_clk = {
.halt_reg = 0x1c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_q6ss_ahbs_clk = {
.halt_reg = 0x20,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
.halt_reg = 0x0,
.halt_check = BRANCH_HALT,
@ -105,17 +79,6 @@ static struct regmap_config lpass_regmap_config = {
.fast_io = true,
};
static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
[LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
[LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
};
static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
.config = &lpass_regmap_config,
.clks = lpass_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
};
static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
@ -169,13 +132,6 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
if (ret)
goto destroy_pm_clk;
lpass_regmap_config.name = "cc";
desc = &lpass_cc_sc7280_desc;
ret = qcom_cc_probe_by_index(pdev, 2, desc);
if (ret)
goto destroy_pm_clk;
return 0;
destroy_pm_clk:

33
drivers/clk/qcom/lpasscorecc-sc7280.c
View File

@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
},
};
static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
.cmd_rcgr = 0x20000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_mclk0_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch lpass_core_cc_core_clk = {
.halt_reg = 0x1f000,
@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
},
};
static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
.halt_reg = 0x20014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
[LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
[LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
};
static struct regmap_config lpass_core_cc_sc7280_regmap_config = {

454
drivers/clk/qcom/mmcc-msm8960.c
View File

@ -41,70 +41,6 @@ enum {
#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 }
};
static const char * const mmcc_pxo_pll8_pll2[] = {
"pxo",
"pll8_vote",
"pll2",
};
static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL3, 3 }
};
static const char * const mmcc_pxo_pll8_pll2_pll15[] = {
"pxo",
"pll8_vote",
"pll2",
"pll15",
};
static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL15, 3 }
};
static const char * const mmcc_pxo_pll8_pll2_pll3[] = {
"pxo",
"pll8_vote",
"pll2",
"pll3",
};
static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
{ P_PXO, 0 },
{ P_DSI2_PLL_DSICLK, 1 },
{ P_DSI1_PLL_DSICLK, 3 },
};
static const char * const mmcc_pxo_dsi2_dsi1[] = {
"pxo",
"dsi2pll",
"dsi1pll",
};
static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
{ P_PXO, 0 },
{ P_DSI1_PLL_BYTECLK, 1 },
{ P_DSI2_PLL_BYTECLK, 2 },
};
static const char * const mmcc_pxo_dsi1_dsi2_byte[] = {
"pxo",
"dsi1pllbyte",
"dsi2pllbyte",
};
static struct clk_pll pll2 = {
.l_reg = 0x320,
.m_reg = 0x324,
@ -115,7 +51,9 @@ static struct clk_pll pll2 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll2",
.parent_names = (const char *[]){ "pxo" },
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
@ -131,7 +69,9 @@ static struct clk_pll pll15 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll15",
.parent_names = (const char *[]){ "pxo" },
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
@ -151,6 +91,70 @@ static const struct pll_config pll15_config = {
.main_output_mask = BIT(23),
};
static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 }
};
static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .hw = &pll2.clkr.hw },
};
static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL3, 3 }
};
static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .hw = &pll2.clkr.hw },
{ .hw = &pll15.clkr.hw },
};
static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL15, 3 }
};
static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .hw = &pll2.clkr.hw },
{ .fw_name = "pll3", .name = "pll3" },
};
static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
{ P_PXO, 0 },
{ P_DSI2_PLL_DSICLK, 1 },
{ P_DSI1_PLL_DSICLK, 3 },
};
static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "dsi2pll", .name = "dsi2pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
{ P_PXO, 0 },
{ P_DSI1_PLL_BYTECLK, 1 },
{ P_DSI2_PLL_BYTECLK, 2 },
};
static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
{ .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
};
static struct freq_tbl clk_tbl_cam[] = {
{ 6000000, P_PLL8, 4, 1, 16 },
{ 8000000, P_PLL8, 4, 1, 12 },
@ -192,8 +196,8 @@ static struct clk_rcg camclk0_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "camclk0_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -207,7 +211,9 @@ static struct clk_branch camclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camclk0_clk",
.parent_names = (const char *[]){ "camclk0_src" },
.parent_hws = (const struct clk_hw*[]){
&camclk0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
@ -241,8 +247,8 @@ static struct clk_rcg camclk1_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "camclk1_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -256,7 +262,9 @@ static struct clk_branch camclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camclk1_clk",
.parent_names = (const char *[]){ "camclk1_src" },
.parent_hws = (const struct clk_hw*[]){
&camclk1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
@ -290,8 +298,8 @@ static struct clk_rcg camclk2_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "camclk2_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -305,7 +313,9 @@ static struct clk_branch camclk2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camclk2_clk",
.parent_names = (const char *[]){ "camclk2_src" },
.parent_hws = (const struct clk_hw*[]){
&camclk2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
@ -345,8 +355,8 @@ static struct clk_rcg csi0_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi0_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -359,7 +369,9 @@ static struct clk_branch csi0_clk = {
.enable_reg = 0x0040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "csi0_src" },
.parent_hws = (const struct clk_hw*[]){
&csi0_src.clkr.hw
},
.num_parents = 1,
.name = "csi0_clk",
.ops = &clk_branch_ops,
@ -375,7 +387,9 @@ static struct clk_branch csi0_phy_clk = {
.enable_reg = 0x0040,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "csi0_src" },
.parent_hws = (const struct clk_hw*[]){
&csi0_src.clkr.hw
},
.num_parents = 1,
.name = "csi0_phy_clk",
.ops = &clk_branch_ops,
@ -409,8 +423,8 @@ static struct clk_rcg csi1_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi1_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -423,7 +437,9 @@ static struct clk_branch csi1_clk = {
.enable_reg = 0x0024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "csi1_src" },
.parent_hws = (const struct clk_hw*[]){
&csi1_src.clkr.hw
},
.num_parents = 1,
.name = "csi1_clk",
.ops = &clk_branch_ops,
@ -439,7 +455,9 @@ static struct clk_branch csi1_phy_clk = {
.enable_reg = 0x0024,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "csi1_src" },
.parent_hws = (const struct clk_hw*[]){
&csi1_src.clkr.hw
},
.num_parents = 1,
.name = "csi1_phy_clk",
.ops = &clk_branch_ops,
@ -473,8 +491,8 @@ static struct clk_rcg csi2_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi2_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -487,7 +505,9 @@ static struct clk_branch csi2_clk = {
.enable_reg = 0x022c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "csi2_src" },
.parent_hws = (const struct clk_hw*[]){
&csi2_src.clkr.hw
},
.num_parents = 1,
.name = "csi2_clk",
.ops = &clk_branch_ops,
@ -503,7 +523,9 @@ static struct clk_branch csi2_phy_clk = {
.enable_reg = 0x022c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "csi2_src" },
.parent_hws = (const struct clk_hw*[]){
&csi2_src.clkr.hw
},
.num_parents = 1,
.name = "csi2_phy_clk",
.ops = &clk_branch_ops,
@ -602,10 +624,10 @@ static const struct clk_ops clk_ops_pix_rdi = {
.determine_rate = __clk_mux_determine_rate,
};
static const char * const pix_rdi_parents[] = {
"csi0_clk",
"csi1_clk",
"csi2_clk",
static const struct clk_hw *pix_rdi_parents[] = {
&csi0_clk.clkr.hw,
&csi1_clk.clkr.hw,
&csi2_clk.clkr.hw,
};
static struct clk_pix_rdi csi_pix_clk = {
@ -618,8 +640,8 @@ static struct clk_pix_rdi csi_pix_clk = {
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "csi_pix_clk",
.parent_names = pix_rdi_parents,
.num_parents = 3,
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
@ -635,8 +657,8 @@ static struct clk_pix_rdi csi_pix1_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "csi_pix1_clk",
.parent_names = pix_rdi_parents,
.num_parents = 3,
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
@ -652,8 +674,8 @@ static struct clk_pix_rdi csi_rdi_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "csi_rdi_clk",
.parent_names = pix_rdi_parents,
.num_parents = 3,
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
@ -669,8 +691,8 @@ static struct clk_pix_rdi csi_rdi1_clk = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi_rdi1_clk",
.parent_names = pix_rdi_parents,
.num_parents = 3,
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
@ -686,8 +708,8 @@ static struct clk_pix_rdi csi_rdi2_clk = {
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "csi_rdi2_clk",
.parent_names = pix_rdi_parents,
.num_parents = 3,
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
@ -725,15 +747,13 @@ static struct clk_rcg csiphytimer_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csiphytimer_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static const char * const csixphy_timer_src[] = { "csiphytimer_src" };
static struct clk_branch csiphy0_timer_clk = {
.halt_reg = 0x01e8,
.halt_bit = 17,
@ -741,7 +761,9 @@ static struct clk_branch csiphy0_timer_clk = {
.enable_reg = 0x0160,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_names = csixphy_timer_src,
.parent_hws = (const struct clk_hw*[]){
&csiphytimer_src.clkr.hw,
},
.num_parents = 1,
.name = "csiphy0_timer_clk",
.ops = &clk_branch_ops,
@ -757,7 +779,9 @@ static struct clk_branch csiphy1_timer_clk = {
.enable_reg = 0x0160,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.parent_names = csixphy_timer_src,
.parent_hws = (const struct clk_hw*[]){
&csiphytimer_src.clkr.hw,
},
.num_parents = 1,
.name = "csiphy1_timer_clk",
.ops = &clk_branch_ops,
@ -773,7 +797,9 @@ static struct clk_branch csiphy2_timer_clk = {
.enable_reg = 0x0160,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.parent_names = csixphy_timer_src,
.parent_hws = (const struct clk_hw*[]){
&csiphytimer_src.clkr.hw,
},
.num_parents = 1,
.name = "csiphy2_timer_clk",
.ops = &clk_branch_ops,
@ -835,8 +861,8 @@ static struct clk_dyn_rcg gfx2d0_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx2d0_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
@ -850,7 +876,9 @@ static struct clk_branch gfx2d0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx2d0_clk",
.parent_names = (const char *[]){ "gfx2d0_src" },
.parent_hws = (const struct clk_hw*[]){
&gfx2d0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -895,8 +923,8 @@ static struct clk_dyn_rcg gfx2d1_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx2d1_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
@ -910,7 +938,9 @@ static struct clk_branch gfx2d1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx2d1_clk",
.parent_names = (const char *[]){ "gfx2d1_src" },
.parent_hws = (const struct clk_hw*[]){
&gfx2d1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -996,8 +1026,8 @@ static struct clk_dyn_rcg gfx3d_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_src",
.parent_names = mmcc_pxo_pll8_pll2_pll3,
.num_parents = 4,
.parent_data = mmcc_pxo_pll8_pll2_pll3,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3),
.ops = &clk_dyn_rcg_ops,
},
},
@ -1005,8 +1035,8 @@ static struct clk_dyn_rcg gfx3d_src = {
static const struct clk_init_data gfx3d_8064_init = {
.name = "gfx3d_src",
.parent_names = mmcc_pxo_pll8_pll2_pll15,
.num_parents = 4,
.parent_data = mmcc_pxo_pll8_pll2_pll15,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15),
.ops = &clk_dyn_rcg_ops,
};
@ -1018,7 +1048,9 @@ static struct clk_branch gfx3d_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk",
.parent_names = (const char *[]){ "gfx3d_src" },
.parent_hws = (const struct clk_hw*[]){
&gfx3d_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1074,8 +1106,8 @@ static struct clk_dyn_rcg vcap_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vcap_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
@ -1089,7 +1121,9 @@ static struct clk_branch vcap_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vcap_clk",
.parent_names = (const char *[]){ "vcap_src" },
.parent_hws = (const struct clk_hw*[]){
&vcap_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1105,7 +1139,9 @@ static struct clk_branch vcap_npl_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "vcap_npl_clk",
.parent_names = (const char *[]){ "vcap_src" },
.parent_hws = (const struct clk_hw*[]){
&vcap_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1153,8 +1189,8 @@ static struct clk_rcg ijpeg_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "ijpeg_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -1168,7 +1204,9 @@ static struct clk_branch ijpeg_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ijpeg_clk",
.parent_names = (const char *[]){ "ijpeg_src" },
.parent_hws = (const struct clk_hw*[]){
&ijpeg_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1201,8 +1239,8 @@ static struct clk_rcg jpegd_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "jpegd_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -1216,7 +1254,9 @@ static struct clk_branch jpegd_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "jpegd_clk",
.parent_names = (const char *[]){ "jpegd_src" },
.parent_hws = (const struct clk_hw*[]){
&jpegd_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1281,8 +1321,8 @@ static struct clk_dyn_rcg mdp_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "mdp_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
@ -1296,7 +1336,9 @@ static struct clk_branch mdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdp_clk",
.parent_names = (const char *[]){ "mdp_src" },
.parent_hws = (const struct clk_hw*[]){
&mdp_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1311,7 +1353,9 @@ static struct clk_branch mdp_lut_clk = {
.enable_reg = 0x016c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "mdp_src" },
.parent_hws = (const struct clk_hw*[]){
&mdp_src.clkr.hw
},
.num_parents = 1,
.name = "mdp_lut_clk",
.ops = &clk_branch_ops,
@ -1328,7 +1372,9 @@ static struct clk_branch mdp_vsync_clk = {
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "mdp_vsync_clk",
.parent_names = (const char *[]){ "pxo" },
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_branch_ops
},
@ -1380,8 +1426,8 @@ static struct clk_dyn_rcg rot_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "rot_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
@ -1395,7 +1441,9 @@ static struct clk_branch rot_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "rot_clk",
.parent_names = (const char *[]){ "rot_src" },
.parent_hws = (const struct clk_hw*[]){
&rot_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1408,9 +1456,9 @@ static const struct parent_map mmcc_pxo_hdmi_map[] = {
{ P_HDMI_PLL, 3 }
};
static const char * const mmcc_pxo_hdmi[] = {
"pxo",
"hdmi_pll",
static const struct clk_parent_data mmcc_pxo_hdmi[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "hdmipll", .name = "hdmi_pll" },
};
static struct freq_tbl clk_tbl_tv[] = {
@ -1443,16 +1491,14 @@ static struct clk_rcg tv_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "tv_src",
.parent_names = mmcc_pxo_hdmi,
.num_parents = 2,
.parent_data = mmcc_pxo_hdmi,
.num_parents = ARRAY_SIZE(mmcc_pxo_hdmi),
.ops = &clk_rcg_bypass_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const char * const tv_src_name[] = { "tv_src" };
static struct clk_branch tv_enc_clk = {
.halt_reg = 0x01d4,
.halt_bit = 9,
@ -1460,7 +1506,9 @@ static struct clk_branch tv_enc_clk = {
.enable_reg = 0x00ec,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_names = tv_src_name,
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "tv_enc_clk",
.ops = &clk_branch_ops,
@ -1476,7 +1524,9 @@ static struct clk_branch tv_dac_clk = {
.enable_reg = 0x00ec,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.parent_names = tv_src_name,
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "tv_dac_clk",
.ops = &clk_branch_ops,
@ -1492,7 +1542,9 @@ static struct clk_branch mdp_tv_clk = {
.enable_reg = 0x00ec,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_names = tv_src_name,
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "mdp_tv_clk",
.ops = &clk_branch_ops,
@ -1508,7 +1560,9 @@ static struct clk_branch hdmi_tv_clk = {
.enable_reg = 0x00ec,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.parent_names = tv_src_name,
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "hdmi_tv_clk",
.ops = &clk_branch_ops,
@ -1524,7 +1578,9 @@ static struct clk_branch rgb_tv_clk = {
.enable_reg = 0x0124,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.parent_names = tv_src_name,
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "rgb_tv_clk",
.ops = &clk_branch_ops,
@ -1540,7 +1596,9 @@ static struct clk_branch npl_tv_clk = {
.enable_reg = 0x0124,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.parent_names = tv_src_name,
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "npl_tv_clk",
.ops = &clk_branch_ops,
@ -1556,7 +1614,9 @@ static struct clk_branch hdmi_app_clk = {
.enable_reg = 0x005c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "pxo" },
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.name = "hdmi_app_clk",
.ops = &clk_branch_ops,
@ -1614,8 +1674,8 @@ static struct clk_dyn_rcg vcodec_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vcodec_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
@ -1629,7 +1689,9 @@ static struct clk_branch vcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vcodec_clk",
.parent_names = (const char *[]){ "vcodec_src" },
.parent_hws = (const struct clk_hw*[]){
&vcodec_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1665,8 +1727,8 @@ static struct clk_rcg vpe_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vpe_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -1680,7 +1742,9 @@ static struct clk_branch vpe_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpe_clk",
.parent_names = (const char *[]){ "vpe_src" },
.parent_hws = (const struct clk_hw*[]){
&vpe_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1733,8 +1797,8 @@ static struct clk_rcg vfe_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vfe_src",
.parent_names = mmcc_pxo_pll8_pll2,
.num_parents = 3,
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
@ -1748,7 +1812,9 @@ static struct clk_branch vfe_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vfe_clk",
.parent_names = (const char *[]){ "vfe_src" },
.parent_hws = (const struct clk_hw*[]){
&vfe_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -1763,7 +1829,9 @@ static struct clk_branch vfe_csi_clk = {
.enable_reg = 0x0104,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "vfe_src" },
.parent_hws = (const struct clk_hw*[]){
&vfe_src.clkr.hw
},
.num_parents = 1,
.name = "vfe_csi_clk",
.ops = &clk_branch_ops,
@ -2067,8 +2135,8 @@ static struct clk_rcg dsi1_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_src",
.parent_names = mmcc_pxo_dsi2_dsi1,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@ -2083,7 +2151,9 @@ static struct clk_branch dsi1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi1_clk",
.parent_names = (const char *[]){ "dsi1_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2115,8 +2185,8 @@ static struct clk_rcg dsi2_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_src",
.parent_names = mmcc_pxo_dsi2_dsi1,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@ -2131,7 +2201,9 @@ static struct clk_branch dsi2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi2_clk",
.parent_names = (const char *[]){ "dsi2_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2154,8 +2226,8 @@ static struct clk_rcg dsi1_byte_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_byte_src",
.parent_names = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@ -2170,7 +2242,9 @@ static struct clk_branch dsi1_byte_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi1_byte_clk",
.parent_names = (const char *[]){ "dsi1_byte_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi1_byte_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2193,8 +2267,8 @@ static struct clk_rcg dsi2_byte_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_byte_src",
.parent_names = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@ -2209,7 +2283,9 @@ static struct clk_branch dsi2_byte_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi2_byte_clk",
.parent_names = (const char *[]){ "dsi2_byte_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi2_byte_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2232,8 +2308,8 @@ static struct clk_rcg dsi1_esc_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_esc_src",
.parent_names = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_esc_ops,
},
},
@ -2247,7 +2323,9 @@ static struct clk_branch dsi1_esc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi1_esc_clk",
.parent_names = (const char *[]){ "dsi1_esc_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi1_esc_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2270,8 +2348,8 @@ static struct clk_rcg dsi2_esc_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_esc_src",
.parent_names = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_esc_ops,
},
},
@ -2285,7 +2363,9 @@ static struct clk_branch dsi2_esc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi2_esc_clk",
.parent_names = (const char *[]){ "dsi2_esc_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi2_esc_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2317,8 +2397,8 @@ static struct clk_rcg dsi1_pixel_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_pixel_src",
.parent_names = mmcc_pxo_dsi2_dsi1,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_pixel_ops,
},
},
@ -2332,7 +2412,9 @@ static struct clk_branch dsi1_pixel_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdp_pclk1_clk",
.parent_names = (const char *[]){ "dsi1_pixel_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi1_pixel_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@ -2364,8 +2446,8 @@ static struct clk_rcg dsi2_pixel_src = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_pixel_src",
.parent_names = mmcc_pxo_dsi2_dsi1,
.num_parents = 3,
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_pixel_ops,
},
},
@ -2379,7 +2461,9 @@ static struct clk_branch dsi2_pixel_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdp_pclk2_clk",
.parent_names = (const char *[]){ "dsi2_pixel_src" },
.parent_hws = (const struct clk_hw*[]){
&dsi2_pixel_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,

4
drivers/clk/qcom/reset.c
View File

@ -13,8 +13,10 @@
static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
{
struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
rcdev->ops->assert(rcdev, id);
udelay(1);
udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
rcdev->ops->deassert(rcdev, id);
return 0;
}

1
drivers/clk/qcom/reset.h
View File

@ -11,6 +11,7 @@
struct qcom_reset_map {
unsigned int reg;
u8 bit;
u8 udelay;
};
struct regmap;

218
include/dt-bindings/clock/qcom,gcc-msm8909.h Normal file
View File

@ -0,0 +1,218 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Kernkonzept GmbH.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_8909_H
#define _DT_BINDINGS_CLK_QCOM_GCC_8909_H
/* PLLs */
#define GPLL0_EARLY 0
#define GPLL0 1
#define GPLL1 2
#define GPLL1_VOTE 3
#define GPLL2_EARLY 4
#define GPLL2 5
#define BIMC_PLL_EARLY 6
#define BIMC_PLL 7
/* RCGs */
#define APSS_AHB_CLK_SRC 8
#define BIMC_DDR_CLK_SRC 9
#define BIMC_GPU_CLK_SRC 10
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22
#define BLSP1_UART1_APPS_CLK_SRC 23
#define BLSP1_UART2_APPS_CLK_SRC 24
#define BYTE0_CLK_SRC 25
#define CAMSS_GP0_CLK_SRC 26
#define CAMSS_GP1_CLK_SRC 27
#define CAMSS_TOP_AHB_CLK_SRC 28
#define CODEC_DIGCODEC_CLK_SRC 29
#define CRYPTO_CLK_SRC 30
#define CSI0_CLK_SRC 31
#define CSI0PHYTIMER_CLK_SRC 32
#define CSI1_CLK_SRC 33
#define ESC0_CLK_SRC 34
#define GFX3D_CLK_SRC 35
#define GP1_CLK_SRC 36
#define GP2_CLK_SRC 37
#define GP3_CLK_SRC 38
#define MCLK0_CLK_SRC 39
#define MCLK1_CLK_SRC 40
#define MDP_CLK_SRC 41
#define PCLK0_CLK_SRC 42
#define PCNOC_BFDCD_CLK_SRC 43
#define PDM2_CLK_SRC 44
#define SDCC1_APPS_CLK_SRC 45
#define SDCC2_APPS_CLK_SRC 46
#define SYSTEM_NOC_BFDCD_CLK_SRC 47
#define ULTAUDIO_AHBFABRIC_CLK_SRC 48
#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 49
#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 50
#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 51
#define ULTAUDIO_XO_CLK_SRC 52
#define USB_HS_SYSTEM_CLK_SRC 53
#define VCODEC0_CLK_SRC 54
#define VFE0_CLK_SRC 55
#define VSYNC_CLK_SRC 56
/* Voteable Clocks */
#define GCC_APSS_TCU_CLK 57
#define GCC_BLSP1_AHB_CLK 58
#define GCC_BLSP1_SLEEP_CLK 59
#define GCC_BOOT_ROM_AHB_CLK 60
#define GCC_CRYPTO_CLK 61
#define GCC_CRYPTO_AHB_CLK 62
#define GCC_CRYPTO_AXI_CLK 63
#define GCC_GFX_TBU_CLK 64
#define GCC_GFX_TCU_CLK 65
#define GCC_GTCU_AHB_CLK 66
#define GCC_MDP_TBU_CLK 67
#define GCC_PRNG_AHB_CLK 68
#define GCC_SMMU_CFG_CLK 69
#define GCC_VENUS_TBU_CLK 70
#define GCC_VFE_TBU_CLK 71
/* Branches */
#define GCC_BIMC_GFX_CLK 72
#define GCC_BIMC_GPU_CLK 73
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 74
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 75
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 76
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 77
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 79
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 81
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 82
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 83
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 84
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 85
#define GCC_BLSP1_UART1_APPS_CLK 86
#define GCC_BLSP1_UART2_APPS_CLK 87
#define GCC_CAMSS_AHB_CLK 88
#define GCC_CAMSS_CSI0_CLK 89
#define GCC_CAMSS_CSI0_AHB_CLK 90
#define GCC_CAMSS_CSI0PHY_CLK 91
#define GCC_CAMSS_CSI0PHYTIMER_CLK 92
#define GCC_CAMSS_CSI0PIX_CLK 93
#define GCC_CAMSS_CSI0RDI_CLK 94
#define GCC_CAMSS_CSI1_CLK 95
#define GCC_CAMSS_CSI1_AHB_CLK 96
#define GCC_CAMSS_CSI1PHY_CLK 97
#define GCC_CAMSS_CSI1PIX_CLK 98
#define GCC_CAMSS_CSI1RDI_CLK 99
#define GCC_CAMSS_CSI_VFE0_CLK 100
#define GCC_CAMSS_GP0_CLK 101
#define GCC_CAMSS_GP1_CLK 102
#define GCC_CAMSS_ISPIF_AHB_CLK 103
#define GCC_CAMSS_MCLK0_CLK 104
#define GCC_CAMSS_MCLK1_CLK 105
#define GCC_CAMSS_TOP_AHB_CLK 106
#define GCC_CAMSS_VFE0_CLK 107
#define GCC_CAMSS_VFE_AHB_CLK 108
#define GCC_CAMSS_VFE_AXI_CLK 109
#define GCC_CODEC_DIGCODEC_CLK 110
#define GCC_GP1_CLK 111
#define GCC_GP2_CLK 112
#define GCC_GP3_CLK 113
#define GCC_MDSS_AHB_CLK 114
#define GCC_MDSS_AXI_CLK 115
#define GCC_MDSS_BYTE0_CLK 116
#define GCC_MDSS_ESC0_CLK 117
#define GCC_MDSS_MDP_CLK 118
#define GCC_MDSS_PCLK0_CLK 119
#define GCC_MDSS_VSYNC_CLK 120
#define GCC_MSS_CFG_AHB_CLK 121
#define GCC_MSS_Q6_BIMC_AXI_CLK 122
#define GCC_OXILI_AHB_CLK 123
#define GCC_OXILI_GFX3D_CLK 124
#define GCC_PDM2_CLK 125
#define GCC_PDM_AHB_CLK 126
#define GCC_SDCC1_AHB_CLK 127
#define GCC_SDCC1_APPS_CLK 128
#define GCC_SDCC2_AHB_CLK 129
#define GCC_SDCC2_APPS_CLK 130
#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 131
#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 132
#define GCC_ULTAUDIO_AVSYNC_XO_CLK 133
#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 134
#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 135
#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 136
#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 137
#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 138
#define GCC_ULTAUDIO_STC_XO_CLK 139
#define GCC_USB2A_PHY_SLEEP_CLK 140
#define GCC_USB_HS_AHB_CLK 141
#define GCC_USB_HS_PHY_CFG_AHB_CLK 142
#define GCC_USB_HS_SYSTEM_CLK 143
#define GCC_VENUS0_AHB_CLK 144
#define GCC_VENUS0_AXI_CLK 145
#define GCC_VENUS0_CORE0_VCODEC0_CLK 146
#define GCC_VENUS0_VCODEC0_CLK 147
/* Resets */
#define GCC_AUDIO_CORE_BCR 0
#define GCC_BLSP1_BCR 1
#define GCC_BLSP1_QUP1_BCR 2
#define GCC_BLSP1_QUP2_BCR 3
#define GCC_BLSP1_QUP3_BCR 4
#define GCC_BLSP1_QUP4_BCR 5
#define GCC_BLSP1_QUP5_BCR 6
#define GCC_BLSP1_QUP6_BCR 7
#define GCC_BLSP1_UART1_BCR 8
#define GCC_BLSP1_UART2_BCR 9
#define GCC_CAMSS_CSI0_BCR 10
#define GCC_CAMSS_CSI0PHY_BCR 11
#define GCC_CAMSS_CSI0PIX_BCR 12
#define GCC_CAMSS_CSI0RDI_BCR 13
#define GCC_CAMSS_CSI1_BCR 14
#define GCC_CAMSS_CSI1PHY_BCR 15
#define GCC_CAMSS_CSI1PIX_BCR 16
#define GCC_CAMSS_CSI1RDI_BCR 17
#define GCC_CAMSS_CSI_VFE0_BCR 18
#define GCC_CAMSS_GP0_BCR 19
#define GCC_CAMSS_GP1_BCR 20
#define GCC_CAMSS_ISPIF_BCR 21
#define GCC_CAMSS_MCLK0_BCR 22
#define GCC_CAMSS_MCLK1_BCR 23
#define GCC_CAMSS_PHY0_BCR 24
#define GCC_CAMSS_TOP_BCR 25
#define GCC_CAMSS_TOP_AHB_BCR 26
#define GCC_CAMSS_VFE_BCR 27
#define GCC_CRYPTO_BCR 28
#define GCC_MDSS_BCR 29
#define GCC_OXILI_BCR 30
#define GCC_PDM_BCR 31
#define GCC_PRNG_BCR 32
#define GCC_QUSB2_PHY_BCR 33
#define GCC_SDCC1_BCR 34
#define GCC_SDCC2_BCR 35
#define GCC_ULT_AUDIO_BCR 36
#define GCC_USB2A_PHY_BCR 37
#define GCC_USB2_HS_PHY_ONLY_BCR 38
#define GCC_USB_HS_BCR 39
#define GCC_VENUS0_BCR 40
/* Subsystem Restart */
#define GCC_MSS_RESTART 41
/* Power Domains */
#define MDSS_GDSC 0
#define OXILI_GDSC 1
#define VENUS_GDSC 2
#define VENUS_CORE0_GDSC 3
#define VFE_GDSC 4
#endif

1
include/dt-bindings/clock/qcom,gcc-sdm845.h
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@ -199,6 +199,7 @@
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
#define GCC_LPASS_Q6_AXI_CLK 190
#define GCC_LPASS_SWAY_CLK 191
#define GPLL6 192
/* GCC Resets */
#define GCC_MMSS_BCR 0

35
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h Normal file
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@ -0,0 +1,35 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC8280XP_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC8280XP_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL1 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CRC_AHB_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CX_SNOC_DVM_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_FREQ_MEASURE_CLK 9
#define GPU_CC_GMU_CLK_SRC 10
#define GPU_CC_GX_GMU_CLK 11
#define GPU_CC_GX_VSENSE_CLK 12
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 13
#define GPU_CC_HUB_AON_CLK 14
#define GPU_CC_HUB_CLK_SRC 15
#define GPU_CC_HUB_CX_INT_CLK 16
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 17
#define GPU_CC_SLEEP_CLK 18
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 19
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
#endif

2
include/dt-bindings/clock/qcom,lcc-ipq806x.h
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@ -19,4 +19,6 @@
#define SPDIF_CLK 10
#define AHBIX_CLK 11
#define LCC_PCM_RESET 0
#endif

5
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
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@ -24,6 +24,11 @@
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
/* LPASS AUDIO CC CSR */
#define LPASS_AUDIO_SWR_RX_CGCR 0
#define LPASS_AUDIO_SWR_TX_CGCR 1
#define LPASS_AUDIO_SWR_WSA_CGCR 2
/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL 0
#define LPASS_AON_CC_PLL_OUT_EVEN 1

2
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
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@ -19,6 +19,8 @@
#define LPASS_CORE_CC_LPM_CORE_CLK 9
#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
#define LPASS_CORE_CC_EXT_MCLK0_CLK 12
#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13
/* LPASS_CORE_CC power domains */
#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0

1
include/dt-bindings/clock/qcom,rpmcc.h
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@ -167,5 +167,6 @@
#define RPM_SMD_CPUSS_GNOC_A_CLK 121
#define RPM_SMD_MSS_CFG_AHB_CLK 122
#define RPM_SMD_MSS_CFG_AHB_A_CLK 123
#define RPM_SMD_BIMC_FREQ_LOG 124
#endif

36
include/dt-bindings/clock/qcom,sm6115-dispcc.h Normal file
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@ -0,0 +1,36 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
/* DISP_CC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_PLL0_OUT_MAIN 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_ESC0_CLK 8
#define DISP_CC_MDSS_ESC0_CLK_SRC 9
#define DISP_CC_MDSS_MDP_CLK 10
#define DISP_CC_MDSS_MDP_CLK_SRC 11
#define DISP_CC_MDSS_MDP_LUT_CLK 12
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 13
#define DISP_CC_MDSS_PCLK0_CLK 14
#define DISP_CC_MDSS_PCLK0_CLK_SRC 15
#define DISP_CC_MDSS_ROT_CLK 16
#define DISP_CC_MDSS_ROT_CLK_SRC 17
#define DISP_CC_MDSS_VSYNC_CLK 18
#define DISP_CC_MDSS_VSYNC_CLK_SRC 19
#define DISP_CC_SLEEP_CLK 20
#define DISP_CC_SLEEP_CLK_SRC 21
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#endif

234
include/dt-bindings/clock/qcom,sm6375-gcc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H
/* Clocks */
#define GPLL0 0
#define GPLL0_OUT_EVEN 1
#define GPLL0_OUT_ODD 2
#define GPLL1 3
#define GPLL10 4
#define GPLL11 5
#define GPLL3 6
#define GPLL3_OUT_EVEN 7
#define GPLL4 8
#define GPLL5 9
#define GPLL6 10
#define GPLL6_OUT_EVEN 11
#define GPLL7 12
#define GPLL8 13
#define GPLL8_OUT_EVEN 14
#define GPLL9 15
#define GPLL9_OUT_MAIN 16
#define GCC_AHB2PHY_CSI_CLK 17
#define GCC_AHB2PHY_USB_CLK 18
#define GCC_BIMC_GPU_AXI_CLK 19
#define GCC_BOOT_ROM_AHB_CLK 20
#define GCC_CAM_THROTTLE_NRT_CLK 21
#define GCC_CAM_THROTTLE_RT_CLK 22
#define GCC_CAMERA_AHB_CLK 23
#define GCC_CAMERA_XO_CLK 24
#define GCC_CAMSS_AXI_CLK 25
#define GCC_CAMSS_AXI_CLK_SRC 26
#define GCC_CAMSS_CAMNOC_ATB_CLK 27
#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 28
#define GCC_CAMSS_CCI_0_CLK 29
#define GCC_CAMSS_CCI_0_CLK_SRC 30
#define GCC_CAMSS_CCI_1_CLK 31
#define GCC_CAMSS_CCI_1_CLK_SRC 32
#define GCC_CAMSS_CPHY_0_CLK 33
#define GCC_CAMSS_CPHY_1_CLK 34
#define GCC_CAMSS_CPHY_2_CLK 35
#define GCC_CAMSS_CPHY_3_CLK 36
#define GCC_CAMSS_CSI0PHYTIMER_CLK 37
#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 38
#define GCC_CAMSS_CSI1PHYTIMER_CLK 39
#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 40
#define GCC_CAMSS_CSI2PHYTIMER_CLK 41
#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 42
#define GCC_CAMSS_CSI3PHYTIMER_CLK 43
#define GCC_CAMSS_CSI3PHYTIMER_CLK_SRC 44
#define GCC_CAMSS_MCLK0_CLK 45
#define GCC_CAMSS_MCLK0_CLK_SRC 46
#define GCC_CAMSS_MCLK1_CLK 47
#define GCC_CAMSS_MCLK1_CLK_SRC 48
#define GCC_CAMSS_MCLK2_CLK 49
#define GCC_CAMSS_MCLK2_CLK_SRC 50
#define GCC_CAMSS_MCLK3_CLK 51
#define GCC_CAMSS_MCLK3_CLK_SRC 52
#define GCC_CAMSS_MCLK4_CLK 53
#define GCC_CAMSS_MCLK4_CLK_SRC 54
#define GCC_CAMSS_NRT_AXI_CLK 55
#define GCC_CAMSS_OPE_AHB_CLK 56
#define GCC_CAMSS_OPE_AHB_CLK_SRC 57
#define GCC_CAMSS_OPE_CLK 58
#define GCC_CAMSS_OPE_CLK_SRC 59
#define GCC_CAMSS_RT_AXI_CLK 60
#define GCC_CAMSS_TFE_0_CLK 61
#define GCC_CAMSS_TFE_0_CLK_SRC 62
#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 63
#define GCC_CAMSS_TFE_0_CSID_CLK 64
#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 65
#define GCC_CAMSS_TFE_1_CLK 66
#define GCC_CAMSS_TFE_1_CLK_SRC 67
#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 68
#define GCC_CAMSS_TFE_1_CSID_CLK 69
#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 70
#define GCC_CAMSS_TFE_2_CLK 71
#define GCC_CAMSS_TFE_2_CLK_SRC 72
#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 73
#define GCC_CAMSS_TFE_2_CSID_CLK 74
#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 75
#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 76
#define GCC_CAMSS_TOP_AHB_CLK 77
#define GCC_CAMSS_TOP_AHB_CLK_SRC 78
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 79
#define GCC_CPUSS_AHB_CLK_SRC 80
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 81
#define GCC_CPUSS_GNOC_CLK 82
#define GCC_DISP_AHB_CLK 83
#define GCC_DISP_GPLL0_CLK_SRC 84
#define GCC_DISP_GPLL0_DIV_CLK_SRC 85
#define GCC_DISP_HF_AXI_CLK 86
#define GCC_DISP_SLEEP_CLK 87
#define GCC_DISP_THROTTLE_CORE_CLK 88
#define GCC_DISP_XO_CLK 89
#define GCC_GP1_CLK 90
#define GCC_GP1_CLK_SRC 91
#define GCC_GP2_CLK 92
#define GCC_GP2_CLK_SRC 93
#define GCC_GP3_CLK 94
#define GCC_GP3_CLK_SRC 95
#define GCC_GPU_CFG_AHB_CLK 96
#define GCC_GPU_GPLL0_CLK_SRC 97
#define GCC_GPU_GPLL0_DIV_CLK_SRC 98
#define GCC_GPU_MEMNOC_GFX_CLK 99
#define GCC_GPU_SNOC_DVM_GFX_CLK 100
#define GCC_GPU_THROTTLE_CORE_CLK 101
#define GCC_PDM2_CLK 102
#define GCC_PDM2_CLK_SRC 103
#define GCC_PDM_AHB_CLK 104
#define GCC_PDM_XO4_CLK 105
#define GCC_PRNG_AHB_CLK 106
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 107
#define GCC_QMIP_CAMERA_RT_AHB_CLK 108
#define GCC_QMIP_DISP_AHB_CLK 109
#define GCC_QMIP_GPU_CFG_AHB_CLK 110
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 111
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 112
#define GCC_QUPV3_WRAP0_CORE_CLK 113
#define GCC_QUPV3_WRAP0_S0_CLK 114
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 115
#define GCC_QUPV3_WRAP0_S1_CLK 116
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 117
#define GCC_QUPV3_WRAP0_S2_CLK 118
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 119
#define GCC_QUPV3_WRAP0_S3_CLK 120
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 121
#define GCC_QUPV3_WRAP0_S4_CLK 122
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 123
#define GCC_QUPV3_WRAP0_S5_CLK 124
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 125
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 126
#define GCC_QUPV3_WRAP1_CORE_CLK 127
#define GCC_QUPV3_WRAP1_S0_CLK 128
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 129
#define GCC_QUPV3_WRAP1_S1_CLK 130
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 131
#define GCC_QUPV3_WRAP1_S2_CLK 132
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 133
#define GCC_QUPV3_WRAP1_S3_CLK 134
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 135
#define GCC_QUPV3_WRAP1_S4_CLK 136
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 137
#define GCC_QUPV3_WRAP1_S5_CLK 138
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 139
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 140
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 141
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 142
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 143
#define GCC_RX5_PCIE_CLKREF_EN_CLK 144
#define GCC_SDCC1_AHB_CLK 145
#define GCC_SDCC1_APPS_CLK 146
#define GCC_SDCC1_APPS_CLK_SRC 147
#define GCC_SDCC1_ICE_CORE_CLK 148
#define GCC_SDCC1_ICE_CORE_CLK_SRC 149
#define GCC_SDCC2_AHB_CLK 150
#define GCC_SDCC2_APPS_CLK 151
#define GCC_SDCC2_APPS_CLK_SRC 152
#define GCC_SYS_NOC_CPUSS_AHB_CLK 153
#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 154
#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 155
#define GCC_UFS_MEM_CLKREF_CLK 156
#define GCC_UFS_PHY_AHB_CLK 157
#define GCC_UFS_PHY_AXI_CLK 158
#define GCC_UFS_PHY_AXI_CLK_SRC 159
#define GCC_UFS_PHY_ICE_CORE_CLK 160
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161
#define GCC_UFS_PHY_PHY_AUX_CLK 162
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 163
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 165
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167
#define GCC_USB30_PRIM_MASTER_CLK 168
#define GCC_USB30_PRIM_MASTER_CLK_SRC 169
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 170
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 172
#define GCC_USB30_PRIM_SLEEP_CLK 173
#define GCC_USB3_PRIM_CLKREF_CLK 174
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176
#define GCC_USB3_PRIM_PHY_PIPE_CLK 177
#define GCC_VCODEC0_AXI_CLK 178
#define GCC_VENUS_AHB_CLK 179
#define GCC_VENUS_CTL_AXI_CLK 180
#define GCC_VIDEO_AHB_CLK 181
#define GCC_VIDEO_AXI0_CLK 182
#define GCC_VIDEO_THROTTLE_CORE_CLK 183
#define GCC_VIDEO_VCODEC0_SYS_CLK 184
#define GCC_VIDEO_VENUS_CLK_SRC 185
#define GCC_VIDEO_VENUS_CTL_CLK 186
#define GCC_VIDEO_XO_CLK 187
/* Resets */
#define GCC_CAMSS_OPE_BCR 0
#define GCC_CAMSS_TFE_BCR 1
#define GCC_CAMSS_TOP_BCR 2
#define GCC_GPU_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_PDM_BCR 5
#define GCC_PRNG_BCR 6
#define GCC_QUPV3_WRAPPER_0_BCR 7
#define GCC_QUPV3_WRAPPER_1_BCR 8
#define GCC_QUSB2PHY_PRIM_BCR 9
#define GCC_QUSB2PHY_SEC_BCR 10
#define GCC_SDCC1_BCR 11
#define GCC_SDCC2_BCR 12
#define GCC_UFS_PHY_BCR 13
#define GCC_USB30_PRIM_BCR 14
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15
#define GCC_VCODEC0_BCR 16
#define GCC_VENUS_BCR 17
#define GCC_VIDEO_INTERFACE_BCR 18
#define GCC_USB3_DP_PHY_PRIM_BCR 19
#define GCC_USB3_PHY_PRIM_SP0_BCR 20
/* GDSCs */
#define USB30_PRIM_GDSC 0
#define UFS_PHY_GDSC 1
#define CAMSS_TOP_GDSC 2
#define VENUS_GDSC 3
#define VCODEC0_GDSC 4
#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 5
#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6
#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 7
#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 8
#endif

103
include/dt-bindings/clock/qcom,sm8450-dispcc.h Normal file
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@ -0,0 +1,103 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_AHB1_CLK 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define DISP_CC_MDSS_BYTE1_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK_SRC 8
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_INTF_CLK 10
#define DISP_CC_MDSS_DPTX0_AUX_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13
#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 25
#define DISP_CC_MDSS_DPTX1_LINK_CLK 26
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 27
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 28
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 29
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 30
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 31
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 32
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 33
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 34
#define DISP_CC_MDSS_DPTX2_AUX_CLK 35
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 36
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 37
#define DISP_CC_MDSS_DPTX2_LINK_CLK 38
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 39
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 40
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 41
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 43
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 44
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 45
#define DISP_CC_MDSS_DPTX3_AUX_CLK 46
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 47
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 48
#define DISP_CC_MDSS_DPTX3_LINK_CLK 49
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54
#define DISP_CC_MDSS_ESC0_CLK 55
#define DISP_CC_MDSS_ESC0_CLK_SRC 56
#define DISP_CC_MDSS_ESC1_CLK 57
#define DISP_CC_MDSS_ESC1_CLK_SRC 58
#define DISP_CC_MDSS_MDP1_CLK 59
#define DISP_CC_MDSS_MDP_CLK 60
#define DISP_CC_MDSS_MDP_CLK_SRC 61
#define DISP_CC_MDSS_MDP_LUT1_CLK 62
#define DISP_CC_MDSS_MDP_LUT_CLK 63
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64
#define DISP_CC_MDSS_PCLK0_CLK 65
#define DISP_CC_MDSS_PCLK0_CLK_SRC 66
#define DISP_CC_MDSS_PCLK1_CLK 67
#define DISP_CC_MDSS_PCLK1_CLK_SRC 68
#define DISP_CC_MDSS_ROT1_CLK 69
#define DISP_CC_MDSS_ROT_CLK 70
#define DISP_CC_MDSS_ROT_CLK_SRC 71
#define DISP_CC_MDSS_RSCC_AHB_CLK 72
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 73
#define DISP_CC_MDSS_VSYNC1_CLK 74
#define DISP_CC_MDSS_VSYNC_CLK 75
#define DISP_CC_MDSS_VSYNC_CLK_SRC 76
#define DISP_CC_PLL0 77
#define DISP_CC_PLL1 78
#define DISP_CC_SLEEP_CLK 79
#define DISP_CC_SLEEP_CLK_SRC 80
#define DISP_CC_XO_CLK 81
#define DISP_CC_XO_CLK_SRC 82
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

1
include/linux/soc/qcom/smd-rpm.h
View File

@ -41,6 +41,7 @@ struct qcom_smd_rpm;
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
#define QCOM_SMD_RPM_MMXI_CLK 0x69786d6d
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,