i7core_edac: Registers all supported MC functions
Now, it will try to register on all supported Memory Controller
functions.
It should be noticed that dev3, function 2 is present only on chips with
Registered DIMM's, according to the datasheet. So, the driver doesn't
return -ENODEV is all functions but this one were successfully
registered and enabled:
EDAC i7core: Registered device 8086:2c18 fn=3 0
EDAC i7core: Registered device 8086:2c19 fn=3 1
EDAC i7core: Device not found: PCI ID 8086:2c1a (dev 3, func 2)
EDAC i7core: Registered device 8086:2c1c fn=3 4
EDAC i7core: Registered device 8086:2c20 fn=4 0
EDAC i7core: Registered device 8086:2c21 fn=4 1
EDAC i7core: Registered device 8086:2c22 fn=4 2
EDAC i7core: Registered device 8086:2c23 fn=4 3
EDAC i7core: Registered device 8086:2c28 fn=5 0
EDAC i7core: Registered device 8086:2c29 fn=5 1
EDAC i7core: Registered device 8086:2c2a fn=5 2
EDAC i7core: Registered device 8086:2c2b fn=5 3
EDAC i7core: Registered device 8086:2c30 fn=6 0
EDAC i7core: Registered device 8086:2c31 fn=6 1
EDAC i7core: Registered device 8086:2c32 fn=6 2
EDAC i7core: Registered device 8086:2c33 fn=6 3
EDAC i7core: Driver loaded.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
0b2b7b7ec0
commit
8f33190757
@ -128,7 +128,8 @@
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*/
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#define NUM_CHANS 3
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#define NUM_FUNCS 1
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#define NUM_MCR_FUNCS 4
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#define NUM_CHAN_FUNCS 3
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struct i7core_info {
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u32 mc_control;
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@ -153,9 +154,16 @@ struct i7core_channel {
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u32 dimms;
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};
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struct pci_id_descr {
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int dev;
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int func;
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int dev_id;
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struct pci_dev *pdev;
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};
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struct i7core_pvt {
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struct pci_dev *pci_mcr; /* Dev 3:0 */
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struct pci_dev *pci_ch[NUM_CHANS][NUM_FUNCS];
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struct pci_dev *pci_mcr[NUM_MCR_FUNCS];
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struct pci_dev *pci_ch[NUM_CHANS][NUM_CHAN_FUNCS];
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struct i7core_info info;
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struct i7core_inject inject;
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struct i7core_channel channel[NUM_CHANS];
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@ -167,11 +175,47 @@ struct i7core_dev_info {
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u16 fsb_mapping_errors; /* DID for the branchmap,control */
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};
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static int chan_pci_ids[NUM_CHANS] = {
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PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL, /* Dev 4 */
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PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL, /* Dev 5 */
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PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL, /* Dev 6 */
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#define PCI_DESCR(device, function, device_id) \
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.dev = (device), \
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.func = (function), \
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.dev_id = (device_id)
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struct pci_id_descr pci_devs[] = {
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/* Memory controller */
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{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
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{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
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{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM is supported */
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{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
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/* Channel 0 */
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{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
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{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
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{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
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{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
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/* Channel 1 */
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{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
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{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
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{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
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{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
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/* Channel 2 */
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{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
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};
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#define N_DEVS ARRAY_SIZE(pci_devs)
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/*
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* pci_device_id table for which devices we are looking for
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* This should match the first device at pci_devs table
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*/
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static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR)},
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{0,} /* 0 terminated list. */
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};
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/* Table of devices attributes supported by this driver */
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static const struct i7core_dev_info i7core_devs[] = {
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@ -242,9 +286,12 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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struct i7core_pvt *pvt = mci->pvt_info;
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int i;
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pci_read_config_dword(pvt->pci_mcr, MC_CONTROL, &pvt->info.mc_control);
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pci_read_config_dword(pvt->pci_mcr, MC_STATUS, &pvt->info.mc_status);
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pci_read_config_dword(pvt->pci_mcr, MC_MAX_DOD, &pvt->info.max_dod);
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if (!pvt->pci_mcr[0])
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return -ENODEV;
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pci_read_config_dword(pvt->pci_mcr[0], MC_CONTROL, &pvt->info.mc_control);
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pci_read_config_dword(pvt->pci_mcr[0], MC_STATUS, &pvt->info.mc_status);
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pci_read_config_dword(pvt->pci_mcr[0], MC_MAX_DOD, &pvt->info.max_dod);
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if (ECC_ENABLED(pvt))
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debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt)?8:4);
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@ -303,14 +350,19 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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we're disabling error injection on all write calls to the sysfs nodes that
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controls the error code injection.
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*/
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static void disable_inject(struct mem_ctl_info *mci)
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static int disable_inject(struct mem_ctl_info *mci)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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pvt->inject.enable = 0;
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if (!pvt->pci_ch[pvt->inject.channel][0])
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return -ENODEV;
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pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
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MC_CHANNEL_ERROR_MASK, 0);
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return 0;
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}
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/*
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@ -550,6 +602,9 @@ static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
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int rc;
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long enable;
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if (!pvt->pci_ch[pvt->inject.channel][0])
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return 0;
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rc = strict_strtoul(data, 10, &enable);
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if ((rc < 0))
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return 0;
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@ -684,17 +739,12 @@ static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
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* i7core_put_devices 'put' all the devices that we have
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* reserved via 'get'
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*/
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static void i7core_put_devices(struct mem_ctl_info *mci)
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static void i7core_put_devices(void)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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int i, n;
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int i;
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pci_dev_put(pvt->pci_mcr);
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/* Release all PCI device functions at MTR channel controllers */
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for (i = 0; i < NUM_CHANS; i++)
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for (n = 0; n < NUM_FUNCS; n++)
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pci_dev_put(pvt->pci_ch[i][n]);
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for (i = 0; i < N_DEVS; i++)
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pci_dev_put(pci_devs[i].pdev);
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}
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/*
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@ -703,50 +753,67 @@ static void i7core_put_devices(struct mem_ctl_info *mci)
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*
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* Need to 'get' device 16 func 1 and func 2
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*/
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static int i7core_get_devices(struct mem_ctl_info *mci, int dev_idx)
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static int i7core_get_devices(struct mem_ctl_info *mci, struct pci_dev *mcidev)
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{
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struct i7core_pvt *pvt;
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struct pci_dev *pdev;
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int i, n, func;
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struct i7core_pvt *pvt = mci->pvt_info;
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int rc, i,func;
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struct pci_dev *pdev = NULL;
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pvt = mci->pvt_info;
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memset(pvt, 0, sizeof(*pvt));
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR,
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NULL);
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if (!pdev) {
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i7core_printk(KERN_ERR,
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"Couldn't get PCI ID %04x:%04x function 0\n",
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PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR);
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return -ENODEV;
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}
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pvt->pci_mcr=pdev;
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/* Retrieve all needed functions at MTR channel controllers */
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for (i = 0; i < NUM_CHANS; i++) {
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pdev = NULL;
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for (n = 0; n < NUM_FUNCS; n++) {
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for (i = 0; i < N_DEVS; i++) {
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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chan_pci_ids[i], pdev);
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pci_devs[i].dev_id, NULL);
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if (!pdev) {
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/* End of list, leave */
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i7core_printk(KERN_ERR,
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"Device not found: PCI ID %04x:%04x "
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"found only %d functions "
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"(broken BIOS?)\n",
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PCI_VENDOR_ID_INTEL,
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chan_pci_ids[i], n);
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i7core_put_devices(mci);
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return -ENODEV;
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"(dev %d, func %d)\n",
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PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
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pci_devs[i].dev,pci_devs[i].func);
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if ((pci_devs[i].dev == 3) && (pci_devs[i].func == 2))
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continue; /* Only on chips with RDIMMs */
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else
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i7core_put_devices();
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}
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func = PCI_FUNC(pdev->devfn);
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pvt->pci_ch[i][func] = pdev;
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}
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}
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i7core_printk(KERN_INFO, "Driver loaded.\n");
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pci_devs[i].pdev = pdev;
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/* Get dimm basic config */
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get_dimm_config(mci);
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rc = pci_enable_device(pdev);
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if (rc < 0) {
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i7core_printk(KERN_ERR,
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"Couldn't enable PCI ID %04x:%04x "
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"(dev %d, func %d)\n",
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PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
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pci_devs[i].dev, pci_devs[i].func);
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i7core_put_devices();
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return rc;
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}
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/* Sanity check */
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if (PCI_FUNC(pdev->devfn) != pci_devs[i].func) {
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i7core_printk(KERN_ERR,
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"Device PCI ID %04x:%04x "
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"has function %d instead of %d\n",
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PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
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PCI_FUNC(pdev->devfn), pci_devs[i].func);
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i7core_put_devices();
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return -EINVAL;
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}
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i7core_printk(KERN_INFO,
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"Registered device %0x:%0x fn=%0x %0x\n",
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PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
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PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
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func = PCI_FUNC(pdev->devfn);
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if (pci_devs[i].dev < 4) {
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pvt->pci_mcr[func] = pdev;
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} else {
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pvt->pci_ch[pci_devs[i].dev - 4][func] = pdev;
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}
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}
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i7core_printk(KERN_INFO, "Driver loaded.\n");
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return 0;
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}
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@ -763,7 +830,6 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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{
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struct mem_ctl_info *mci;
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struct i7core_pvt *pvt;
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int rc;
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int num_channels;
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int num_csrows;
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int num_dimms_per_channel;
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@ -772,20 +838,6 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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if (dev_idx >= ARRAY_SIZE(i7core_devs))
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return -EINVAL;
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/* wake up device */
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rc = pci_enable_device(pdev);
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if (rc == -EIO)
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return rc;
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debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
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__func__,
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pdev->bus->number,
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PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
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/* We only are looking for func 0 of the set */
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if (PCI_FUNC(pdev->devfn) != 0)
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return -ENODEV;
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num_channels = NUM_CHANS;
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/* FIXME: FAKE data, since we currently don't now how to get this */
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@ -808,10 +860,6 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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// pvt->maxch = num_channels;
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// pvt->maxdimmperch = num_dimms_per_channel;
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/* 'get' the pci devices we want to reserve for our use */
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if (i7core_get_devices(mci, dev_idx))
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goto fail0;
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mci->mc_idx = 0;
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mci->mtype_cap = MEM_FLAG_FB_DDR2; /* FIXME: it uses DDR3 */
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mci->edac_ctl_cap = EDAC_FLAG_NONE;
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@ -823,6 +871,10 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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mci->ctl_page_to_phys = NULL;
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mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
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/* 'get' the pci devices we want to reserve for our use */
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if (i7core_get_devices(mci, pdev))
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goto fail0;
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/* add this new MC control structure to EDAC's list of MCs */
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if (edac_mc_add_mc(mci)) {
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debugf0("MC: " __FILE__
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@ -852,10 +904,13 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
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pvt->inject.page = -1;
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pvt->inject.col = -1;
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/* Get dimm basic config */
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get_dimm_config(mci);
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return 0;
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fail1:
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i7core_put_devices(mci);
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i7core_put_devices();
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fail0:
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edac_mc_free(mci);
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@ -880,21 +935,11 @@ static void __devexit i7core_remove(struct pci_dev *pdev)
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return;
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/* retrieve references to resources, and free those resources */
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i7core_put_devices(mci);
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i7core_put_devices();
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edac_mc_free(mci);
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}
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/*
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* pci_device_id table for which devices we are looking for
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*
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* The "E500P" device is the first device supported.
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*/
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static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR)},
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{0,} /* 0 terminated list. */
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};
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MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
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/*
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Loading…
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Block a user