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arm64: dts: hip05: Append gpio nodes

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There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Kefeng Wang 2016-01-29 16:39:04 +08:00 committed by Wei Xu
parent abf9c25d55
commit 8f41d122bf
1 changed files with 38 additions and 0 deletions
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38
arch/arm64/boot/dts/hisilicon/hip05.dtsi
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@ -322,5 +322,43 @@
reg-io-width = <4>;
status = "disabled";
};
peri_gpio0: gpio@802e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x802e0000 0x0 0x10000>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
};
};
peri_gpio1: gpio@802f0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x802f0000 0x0 0x10000>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};