From 8f6372a4d69045b8a7dd371bd3c269ad1bf85e08 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 29 Jan 2024 19:55:33 +0200 Subject: [PATCH] drm/i915/mtl: Add DP FEC BS jitter WA Add a workaround to fix BS (blank start) to BS jitter fixes on non-UHBR MST/FEC and UHBR links. Bspec doesn't provide an actual WA ID for this. Bspec: 65448, 50054 Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-7-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1bf13975867e..c1d8f08814ec 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -440,6 +440,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; u32 set = 0; + if (DISPLAY_VER(dev_priv) == 14) + set |= DP_FEC_BS_JITTER_WA; + intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), clear, set); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52111f79ff73..3f34efcd7d6c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4628,6 +4628,7 @@ #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) +#define DP_FEC_BS_JITTER_WA REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)