AT91 clk driver changes for 5.17:
- Lan966x Generic Clock Controller driver and associated DT bindings - Lan966x clock driver extended to support clock gating -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYbCxYwAKCRAfOrpwrNPN DFRwAP9nV1gAI7KGsIGDMBjJpphj9TuZ8u3+PIvxi7pBHPM+lwD/RSJPGTYj4Hpi S/MCdFjE4STmKo83Ii3k3/nrPPEuAwQ= =BQQ9 -----END PGP SIGNATURE----- Merge tag 'clk-at91-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-at91 Pull AT91 clk driver updates from Nicolas Ferre: - Lan966x Generic Clock Controller driver and associated DT bindings - Lan966x clock driver extended to support clock gating * tag 'clk-at91-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: lan966x: Extend lan966x clock driver for clock gating support dt-bindings: clock: lan966x: Extend includes with clock gates dt-bindings: clock: lan966x: Extend for clock gate support clk: gate: Add devm_clk_hw_register_gate() clk: lan966x: Add lan966x SoC clock driver dt-bindings: clock: lan966x: Add LAN966X Clock Controller dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs
This commit is contained in:
Stephen Boyd
commit
8f6b28c5b1
@ -0,0 +1,60 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip LAN966X Generic Clock Controller
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maintainers:
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- Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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description: |
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The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
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ddr_clk and sys_clk. This clock controller generates and supplies
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clock to various peripherals within the SoC.
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properties:
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compatible:
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const: microchip,lan966x-gck
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reg:
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minItems: 1
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items:
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- description: Generic clock registers
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- description: Optional gate clock registers
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clocks:
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items:
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- description: CPU clock source
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- description: DDR clock source
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- description: System clock source
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clock-names:
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items:
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- const: cpu
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- const: ddr
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- const: sys
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clks: clock-controller@e00c00a8 {
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compatible = "microchip,lan966x-gck";
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#clock-cells = <1>;
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clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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clock-names = "cpu", "ddr", "sys";
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reg = <0xe00c00a8 0x38>;
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};
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...
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@ -221,6 +221,13 @@ config COMMON_CLK_GEMINI
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This driver supports the SoC clocks on the Cortina Systems Gemini
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platform, also known as SL3516 or CS3516.
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config COMMON_CLK_LAN966X
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bool "Generic Clock Controller driver for LAN966X SoC"
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help
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This driver provides support for Generic Clock Controller(GCK) on
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LAN966X SoC. GCK generates and supplies clock to various peripherals
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within the SoC.
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config COMMON_CLK_ASPEED
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bool "Clock driver for Aspeed BMC SoCs"
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depends on ARCH_ASPEED || COMPILE_TEST
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@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
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obj-$(CONFIG_LMK04832) += clk-lmk04832.o
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obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
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obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
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@ -7,6 +7,7 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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@ -222,3 +223,37 @@ void clk_hw_unregister_gate(struct clk_hw *hw)
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kfree(gate);
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}
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EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);
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static void devm_clk_hw_release_gate(struct device *dev, void *res)
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{
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clk_hw_unregister_gate(*(struct clk_hw **)res);
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}
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struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
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struct device_node *np, const char *name,
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const char *parent_name, const struct clk_hw *parent_hw,
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const struct clk_parent_data *parent_data,
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unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct clk_hw **ptr, *hw;
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ptr = devres_alloc(devm_clk_hw_release_gate, sizeof(*ptr), GFP_KERNEL);
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if (!ptr)
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return ERR_PTR(-ENOMEM);
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hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,
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parent_data, flags, reg, bit_idx,
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clk_gate_flags, lock);
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if (!IS_ERR(hw)) {
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*ptr = hw;
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devres_add(dev, ptr);
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} else {
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devres_free(ptr);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);
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293
drivers/clk/clk-lan966x.c
Normal file
293
drivers/clk/clk-lan966x.c
Normal file
@ -0,0 +1,293 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Microchip LAN966x SoC Clock driver.
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*
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* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/microchip,lan966x.h>
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#define GCK_ENA BIT(0)
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#define GCK_SRC_SEL GENMASK(9, 8)
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#define GCK_PRESCALER GENMASK(23, 16)
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#define DIV_MAX 255
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static const char *clk_names[N_CLOCKS] = {
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"qspi0", "qspi1", "qspi2", "sdmmc0",
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"pi", "mcan0", "mcan1", "flexcom0",
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"flexcom1", "flexcom2", "flexcom3",
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"flexcom4", "timer1", "usb_refclk",
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};
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struct lan966x_gck {
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struct clk_hw hw;
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void __iomem *reg;
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};
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#define to_lan966x_gck(hw) container_of(hw, struct lan966x_gck, hw)
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static const struct clk_parent_data lan966x_gck_pdata[] = {
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{ .fw_name = "cpu", },
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{ .fw_name = "ddr", },
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{ .fw_name = "sys", },
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};
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static struct clk_init_data init = {
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.parent_data = lan966x_gck_pdata,
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.num_parents = ARRAY_SIZE(lan966x_gck_pdata),
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};
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struct clk_gate_soc_desc {
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const char *name;
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int bit_idx;
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};
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static const struct clk_gate_soc_desc clk_gate_desc[] = {
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{ "uhphs", 11 },
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{ "udphs", 10 },
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{ "mcramc", 9 },
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{ "hmatrix", 8 },
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{ }
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};
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static DEFINE_SPINLOCK(clk_gate_lock);
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static void __iomem *base;
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static int lan966x_gck_enable(struct clk_hw *hw)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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val |= GCK_ENA;
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writel(val, gck->reg);
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return 0;
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}
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static void lan966x_gck_disable(struct clk_hw *hw)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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val &= ~GCK_ENA;
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writel(val, gck->reg);
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}
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static int lan966x_gck_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 div, val = readl(gck->reg);
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if (rate == 0 || parent_rate == 0)
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return -EINVAL;
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/* Set Prescalar */
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div = parent_rate / rate;
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val &= ~GCK_PRESCALER;
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val |= FIELD_PREP(GCK_PRESCALER, (div - 1));
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writel(val, gck->reg);
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return 0;
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}
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static long lan966x_gck_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int div;
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if (rate == 0 || *parent_rate == 0)
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return -EINVAL;
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if (rate >= *parent_rate)
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return *parent_rate;
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div = DIV_ROUND_CLOSEST(*parent_rate, rate);
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return *parent_rate / div;
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}
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static unsigned long lan966x_gck_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 div, val = readl(gck->reg);
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div = FIELD_GET(GCK_PRESCALER, val);
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return parent_rate / (div + 1);
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}
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static int lan966x_gck_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_hw *parent;
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int i;
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for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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/* Allowed prescaler divider range is 0-255 */
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if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {
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req->best_parent_hw = parent;
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req->best_parent_rate = clk_hw_get_rate(parent);
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return 0;
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}
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}
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return -EINVAL;
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}
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static u8 lan966x_gck_get_parent(struct clk_hw *hw)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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return FIELD_GET(GCK_SRC_SEL, val);
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}
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static int lan966x_gck_set_parent(struct clk_hw *hw, u8 index)
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{
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struct lan966x_gck *gck = to_lan966x_gck(hw);
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u32 val = readl(gck->reg);
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val &= ~GCK_SRC_SEL;
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val |= FIELD_PREP(GCK_SRC_SEL, index);
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writel(val, gck->reg);
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return 0;
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}
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static const struct clk_ops lan966x_gck_ops = {
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.enable = lan966x_gck_enable,
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.disable = lan966x_gck_disable,
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.set_rate = lan966x_gck_set_rate,
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.round_rate = lan966x_gck_round_rate,
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.recalc_rate = lan966x_gck_recalc_rate,
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.determine_rate = lan966x_gck_determine_rate,
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.set_parent = lan966x_gck_set_parent,
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.get_parent = lan966x_gck_get_parent,
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};
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static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i)
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{
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struct lan966x_gck *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return ERR_PTR(-ENOMEM);
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priv->reg = base + (i * 4);
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priv->hw.init = &init;
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ret = devm_clk_hw_register(dev, &priv->hw);
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if (ret)
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return ERR_PTR(ret);
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return &priv->hw;
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};
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static int lan966x_gate_clk_register(struct device *dev,
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struct clk_hw_onecell_data *hw_data,
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void __iomem *gate_base)
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{
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int i;
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for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) {
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int idx = i - GCK_GATE_UHPHS;
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hw_data->hws[i] =
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devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name,
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"lan966x", 0, base,
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clk_gate_desc[idx].bit_idx,
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0, &clk_gate_lock);
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if (IS_ERR(hw_data->hws[i]))
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return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),
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"failed to register %s clock\n",
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clk_gate_desc[idx].name);
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}
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return 0;
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}
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static int lan966x_clk_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *hw_data;
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struct device *dev = &pdev->dev;
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void __iomem *gate_base;
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struct resource *res;
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int i, ret;
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hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS),
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GFP_KERNEL);
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if (!hw_data)
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return -ENOMEM;
|
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|
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base = devm_platform_ioremap_resource(pdev, 0);
|
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if (IS_ERR(base))
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return PTR_ERR(base);
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init.ops = &lan966x_gck_ops;
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hw_data->num = GCK_GATE_UHPHS;
|
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for (i = 0; i < GCK_GATE_UHPHS; i++) {
|
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init.name = clk_names[i];
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hw_data->hws[i] = lan966x_gck_clk_register(dev, i);
|
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if (IS_ERR(hw_data->hws[i])) {
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dev_err(dev, "failed to register %s clock\n",
|
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init.name);
|
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return PTR_ERR(hw_data->hws[i]);
|
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}
|
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}
|
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
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if (res) {
|
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gate_base = devm_ioremap_resource(&pdev->dev, res);
|
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if (IS_ERR(gate_base))
|
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return PTR_ERR(gate_base);
|
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hw_data->num = N_CLOCKS;
|
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|
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ret = lan966x_gate_clk_register(dev, hw_data, gate_base);
|
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if (ret)
|
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return ret;
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);
|
||||
}
|
||||
|
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static const struct of_device_id lan966x_clk_dt_ids[] = {
|
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{ .compatible = "microchip,lan966x-gck", },
|
||||
{ }
|
||||
};
|
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MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);
|
||||
|
||||
static struct platform_driver lan966x_clk_driver = {
|
||||
.probe = lan966x_clk_probe,
|
||||
.driver = {
|
||||
.name = "lan966x-clk",
|
||||
.of_match_table = lan966x_clk_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(lan966x_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>");
|
||||
MODULE_DESCRIPTION("LAN966X clock driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
34
include/dt-bindings/clock/microchip,lan966x.h
Normal file
34
include/dt-bindings/clock/microchip,lan966x.h
Normal file
@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2021 Microchip Inc.
|
||||
*
|
||||
* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_LAN966X_H
|
||||
#define _DT_BINDINGS_CLK_LAN966X_H
|
||||
|
||||
#define GCK_ID_QSPI0 0
|
||||
#define GCK_ID_QSPI1 1
|
||||
#define GCK_ID_QSPI2 2
|
||||
#define GCK_ID_SDMMC0 3
|
||||
#define GCK_ID_PI 4
|
||||
#define GCK_ID_MCAN0 5
|
||||
#define GCK_ID_MCAN1 6
|
||||
#define GCK_ID_FLEXCOM0 7
|
||||
#define GCK_ID_FLEXCOM1 8
|
||||
#define GCK_ID_FLEXCOM2 9
|
||||
#define GCK_ID_FLEXCOM3 10
|
||||
#define GCK_ID_FLEXCOM4 11
|
||||
#define GCK_ID_TIMER 12
|
||||
#define GCK_ID_USB_REFCLK 13
|
||||
|
||||
/* Gate clocks */
|
||||
#define GCK_GATE_UHPHS 14
|
||||
#define GCK_GATE_UDPHS 15
|
||||
#define GCK_GATE_MCRAMC 16
|
||||
#define GCK_GATE_HMATRIX 17
|
||||
|
||||
#define N_CLOCKS 18
|
||||
|
||||
#endif
|
||||
@ -490,6 +490,13 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data,
|
||||
unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
@ -544,6 +551,22 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
|
||||
(flags), (reg), (bit_idx), \
|
||||
(clk_gate_flags), (lock))
|
||||
/**
|
||||
* devm_clk_hw_register_gate - register a gate clock with the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of this clock's parent
|
||||
* @flags: framework-specific flags for this clock
|
||||
* @reg: register address to control gating of this clock
|
||||
* @bit_idx: which bit in the register controls gating of this clock
|
||||
* @clk_gate_flags: gate-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
|
||||
clk_gate_flags, lock) \
|
||||
__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (bit_idx), \
|
||||
(clk_gate_flags), (lock))
|
||||
void clk_unregister_gate(struct clk *clk);
|
||||
void clk_hw_unregister_gate(struct clk_hw *hw);
|
||||
int clk_gate_is_enabled(struct clk_hw *hw);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user