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perf/core improvements and fixes:

Browse Source 
x86/insn:
 
   Adrian Hunter:
 
   - Add some more Intel instructions to the opcode map:
 
         cldemote, encls, enclu, enclv, enqcmd, enqcmds, movdir64b,
         movdiri, pconfig, tpause, umonitor, umwait, wbnoinvd.
 
   - The instruction decoding can be tested using the perf tools'
     "x86 instruction decoder - new instructions" test as folllows:
 
     $ perf test -v "new " 2>&1 | grep -i cldemote
     Decoded ok: 0f 1c 00                    cldemote (%eax)
     Decoded ok: 0f 1c 05 78 56 34 12        cldemote 0x12345678
     Decoded ok: 0f 1c 84 c8 78 56 34 12     cldemote 0x12345678(%eax,%ecx,8)
     Decoded ok: 0f 1c 00                    cldemote (%rax)
     Decoded ok: 41 0f 1c 00                 cldemote (%r8)
     Decoded ok: 0f 1c 04 25 78 56 34 12     cldemote 0x12345678
     Decoded ok: 0f 1c 84 c8 78 56 34 12     cldemote 0x12345678(%rax,%rcx,8)
     Decoded ok: 41 0f 1c 84 c8 78 56 34 12  cldemote 0x12345678(%r8,%rcx,8)
     $ perf test -v "new " 2>&1 | grep -i tpause
     Decoded ok: 66 0f ae f3                 tpause %ebx
     Decoded ok: 66 0f ae f3                 tpause %ebx
     Decoded ok: 66 41 0f ae f0              tpause %r8d
 
 callchains:
 
   Adrian Hunter:
 
   - Fix segfault in thread__resolve_callchain_sample().
 
 perf probe:
 
   - Line fixes to show only lines where probes can be used with 'perf probe -L',
     and when reporting them via 'perf probe -l'.
 
   - Support multiprobe events.
 
 perf scripts python:
 
   Adrian Hunter:
 
   - Fix use of TRUE with SQLite < 3.23 in exported-sql-viewer.py.
 
 perf maps:
 
   - Trim 'struct map' by removing the rb_node member for sorting
     by map name, as that is only needed for processing kernel maps,
     and only when classifying symbols by section at load time.
     Sort them by name using qsort() and do lookups using bsearch()
     when map_groups__find_by_name() is used.
 
 perf parse:
 
   Ian Rogers:
 
   - Report initial event parsing error, providing a less cryptic message
     to state that a PMU wasn't found in the system.
 
 perf vendor events:
 
   James Clark:
 
   - Fix commas so that PMU event files for arm64, power8 and power nine
     become valid JSON.
 
 libtraceevent:
 
   Konstantin Khlebnikov:
 
   - Fix parsing of event %o and %X argument types.
 
 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Merge tag 'perf-core-for-mingo-5.5-20191119' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core

Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:

x86/insn:

  Adrian Hunter:

  - Add some more Intel instructions to the opcode map:

        cldemote, encls, enclu, enclv, enqcmd, enqcmds, movdir64b,
        movdiri, pconfig, tpause, umonitor, umwait, wbnoinvd.

  - The instruction decoding can be tested using the perf tools'
    "x86 instruction decoder - new instructions" test as folllows:

    $ perf test -v "new " 2>&1 | grep -i cldemote
    Decoded ok: 0f 1c 00                    cldemote (%eax)
    Decoded ok: 0f 1c 05 78 56 34 12        cldemote 0x12345678
    Decoded ok: 0f 1c 84 c8 78 56 34 12     cldemote 0x12345678(%eax,%ecx,8)
    Decoded ok: 0f 1c 00                    cldemote (%rax)
    Decoded ok: 41 0f 1c 00                 cldemote (%r8)
    Decoded ok: 0f 1c 04 25 78 56 34 12     cldemote 0x12345678
    Decoded ok: 0f 1c 84 c8 78 56 34 12     cldemote 0x12345678(%rax,%rcx,8)
    Decoded ok: 41 0f 1c 84 c8 78 56 34 12  cldemote 0x12345678(%r8,%rcx,8)
    $ perf test -v "new " 2>&1 | grep -i tpause
    Decoded ok: 66 0f ae f3                 tpause %ebx
    Decoded ok: 66 0f ae f3                 tpause %ebx
    Decoded ok: 66 41 0f ae f0              tpause %r8d

callchains:

  Adrian Hunter:

  - Fix segfault in thread__resolve_callchain_sample().

perf probe:

  - Line fixes to show only lines where probes can be used with 'perf probe -L',
    and when reporting them via 'perf probe -l'.

  - Support multiprobe events.

perf scripts python:

  Adrian Hunter:

  - Fix use of TRUE with SQLite < 3.23 in exported-sql-viewer.py.

perf maps:

  - Trim 'struct map' by removing the rb_node member for sorting
    by map name, as that is only needed for processing kernel maps,
    and only when classifying symbols by section at load time.
    Sort them by name using qsort() and do lookups using bsearch()
    when map_groups__find_by_name() is used.

perf parse:

  Ian Rogers:

  - Report initial event parsing error, providing a less cryptic message
    to state that a PMU wasn't found in the system.

perf vendor events:

  James Clark:

  - Fix commas so that PMU event files for arm64, power8 and power nine
    become valid JSON.

libtraceevent:

  Konstantin Khlebnikov:

  - Fix parsing of event %o and %X argument types.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar 2019-11-19 12:59:03 +01:00
commit 8f6ee51d77
66 changed files with 2889 additions and 2367 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/x86/lib/x86-opcode-map.txt
View File

@ -333,7 +333,7 @@ AVXcode: 1
06: CLTS
07: SYSRET (o64)
08: INVD
09: WBINVD
09: WBINVD | WBNOINVD (F3)
0a:
0b: UD2 (1B)
0c:
@ -364,7 +364,7 @@ AVXcode: 1
# a ModR/M byte.
1a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev
1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv
1c:
1c: Grp20 (1A),(1C)
1d:
1e:
1f: NOP Ev
@ -792,6 +792,8 @@ f3: Grp17 (1A)
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3)
f9: MOVDIRI My,Gy
EndTable
Table: 3-byte opcode 2 (0x0f 0x3a)
@ -943,9 +945,9 @@ GrpTable: Grp6
EndTable
GrpTable: Grp7
0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)
1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)
3: LIDT Ms
4: SMSW Mw/Rv
5: rdpkru (110),(11B) | wrpkru (111),(11B)
@ -1020,7 +1022,7 @@ GrpTable: Grp15
3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
4: XSAVE | ptwrite Ey (F3),(11B)
5: XRSTOR | lfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B)
7: clflush | clflushopt (66) | sfence (11B)
EndTable
@ -1051,6 +1053,10 @@ GrpTable: Grp19
6: vscatterpf1qps/d Wx (66),(ev)
EndTable
GrpTable: Grp20
0: cldemote Mb
EndTable
# AMD's Prefetch Group
GrpTable: GrpP
0: PREFETCH

18
tools/arch/x86/lib/x86-opcode-map.txt
View File

@ -333,7 +333,7 @@ AVXcode: 1
06: CLTS
07: SYSRET (o64)
08: INVD
09: WBINVD
09: WBINVD | WBNOINVD (F3)
0a:
0b: UD2 (1B)
0c:
@ -364,7 +364,7 @@ AVXcode: 1
# a ModR/M byte.
1a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev
1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv
1c:
1c: Grp20 (1A),(1C)
1d:
1e:
1f: NOP Ev
@ -792,6 +792,8 @@ f3: Grp17 (1A)
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3)
f9: MOVDIRI My,Gy
EndTable
Table: 3-byte opcode 2 (0x0f 0x3a)
@ -943,9 +945,9 @@ GrpTable: Grp6
EndTable
GrpTable: Grp7
0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)
1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)
3: LIDT Ms
4: SMSW Mw/Rv
5: rdpkru (110),(11B) | wrpkru (111),(11B)
@ -1020,7 +1022,7 @@ GrpTable: Grp15
3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
4: XSAVE | ptwrite Ey (F3),(11B)
5: XRSTOR | lfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B)
7: clflush | clflushopt (66) | sfence (11B)
EndTable
@ -1051,6 +1053,10 @@ GrpTable: Grp19
6: vscatterpf1qps/d Wx (66),(ev)
EndTable
GrpTable: Grp20
0: cldemote Mb
EndTable
# AMD's Prefetch Group
GrpTable: GrpP
0: PREFETCH

7
tools/lib/traceevent/event-parse.c
View File

@ -4395,8 +4395,10 @@ static struct tep_print_arg *make_bprint_args(char *fmt, void *data, int size, s
/* fall through */
case 'd':
case 'u':
case 'x':
case 'i':
case 'x':
case 'X':
case 'o':
switch (ls) {
case 0:
vsize = 4;
@ -5078,10 +5080,11 @@ static void pretty_print(struct trace_seq *s, void *data, int size, struct tep_e
/* fall through */
case 'd':
case 'u':
case 'i':
case 'x':
case 'X':
case 'u':
case 'o':
if (!arg) {
do_warning_event(event, "no argument match");
event->flags |= TEP_EVENT_FL_FAILED;

4
tools/perf/arch/powerpc/util/kvm-stat.c
View File

@ -113,10 +113,10 @@ static int is_tracepoint_available(const char *str, struct evlist *evlist)
struct parse_events_error err;
int ret;
err.str = NULL;
bzero(&err, sizeof(err));
ret = parse_events(evlist, str, &err);
if (err.str)
pr_err("%s : %s\n", str, err.str);
parse_events_print_error(&err, "tracepoint");
return ret;
}

52
tools/perf/arch/x86/tests/insn-x86-dat-32.c
View File

@ -1647,6 +1647,12 @@
"0f ae 30 \txsaveopt (%eax)",},
{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
"0f ae f0 \tmfence ",},
{{0x0f, 0x1c, 0x00, }, 3, 0, "", "",
"0f 1c 00 \tcldemote (%eax)",},
{{0x0f, 0x1c, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1c 05 78 56 34 12 \tcldemote 0x12345678",},
{{0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%eax,%ecx,8)",},
{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
"0f c7 20 \txsavec (%eax)",},
{{0x0f, 0xc7, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
@ -1677,3 +1683,49 @@
"f3 0f ae 25 78 56 34 12 \tptwritel 0x12345678",},
{{0xf3, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae a4 c8 78 56 34 12 \tptwritel 0x12345678(%eax,%ecx,8)",},
{{0x66, 0x0f, 0xae, 0xf3, }, 4, 0, "", "",
"66 0f ae f3 \ttpause %ebx",},
{{0x67, 0xf3, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"67 f3 0f ae f0 \tumonitor %ax",},
{{0xf3, 0x0f, 0xae, 0xf0, }, 4, 0, "", "",
"f3 0f ae f0 \tumonitor %eax",},
{{0xf2, 0x0f, 0xae, 0xf0, }, 4, 0, "", "",
"f2 0f ae f0 \tumwait %eax",},
{{0x0f, 0x38, 0xf9, 0x03, }, 4, 0, "", "",
"0f 38 f9 03 \tmovdiri %eax,(%ebx)",},
{{0x0f, 0x38, 0xf9, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 38 f9 88 78 56 34 12 \tmovdiri %ecx,0x12345678(%eax)",},
{{0x66, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"66 0f 38 f8 18 \tmovdir64b (%eax),%ebx",},
{{0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%eax),%ecx",},
{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x1c, }, 6, 0, "", "",
"67 66 0f 38 f8 1c \tmovdir64b (%si),%bx",},
{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "",
"67 66 0f 38 f8 8c 34 12 \tmovdir64b 0x1234(%si),%cx",},
{{0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"f2 0f 38 f8 18 \tenqcmd (%eax),%ebx",},
{{0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%eax),%ecx",},
{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x1c, }, 6, 0, "", "",
"67 f2 0f 38 f8 1c \tenqcmd (%si),%bx",},
{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "",
"67 f2 0f 38 f8 8c 34 12 \tenqcmd 0x1234(%si),%cx",},
{{0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"f3 0f 38 f8 18 \tenqcmds (%eax),%ebx",},
{{0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%eax),%ecx",},
{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x1c, }, 6, 0, "", "",
"67 f3 0f 38 f8 1c \tenqcmds (%si),%bx",},
{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "",
"67 f3 0f 38 f8 8c 34 12 \tenqcmds 0x1234(%si),%cx",},
{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",
"0f 01 cf \tencls ",},
{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",
"0f 01 d7 \tenclu ",},
{{0x0f, 0x01, 0xc0, }, 3, 0, "", "",
"0f 01 c0 \tenclv ",},
{{0x0f, 0x01, 0xc5, }, 3, 0, "", "",
"0f 01 c5 \tpconfig ",},
{{0xf3, 0x0f, 0x09, }, 3, 0, "", "",
"f3 0f 09 \twbnoinvd ",},

62
tools/perf/arch/x86/tests/insn-x86-dat-64.c
View File

@ -1667,6 +1667,16 @@
"41 0f ae 30 \txsaveopt (%r8)",},
{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
"0f ae f0 \tmfence ",},
{{0x0f, 0x1c, 0x00, }, 3, 0, "", "",
"0f 1c 00 \tcldemote (%rax)",},
{{0x41, 0x0f, 0x1c, 0x00, }, 4, 0, "", "",
"41 0f 1c 00 \tcldemote (%r8)",},
{{0x0f, 0x1c, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1c 04 25 78 56 34 12 \tcldemote 0x12345678",},
{{0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
"0f c7 20 \txsavec (%rax)",},
{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "",
@ -1727,3 +1737,55 @@
"f3 48 0f ae a4 c8 78 56 34 12 \tptwriteq 0x12345678(%rax,%rcx,8)",},
{{0xf3, 0x49, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 49 0f ae a4 c8 78 56 34 12 \tptwriteq 0x12345678(%r8,%rcx,8)",},
{{0x66, 0x0f, 0xae, 0xf3, }, 4, 0, "", "",
"66 0f ae f3 \ttpause %ebx",},
{{0x66, 0x41, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"66 41 0f ae f0 \ttpause %r8d",},
{{0x67, 0xf3, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"67 f3 0f ae f0 \tumonitor %eax",},
{{0xf3, 0x0f, 0xae, 0xf0, }, 4, 0, "", "",
"f3 0f ae f0 \tumonitor %rax",},
{{0x67, 0xf3, 0x41, 0x0f, 0xae, 0xf0, }, 6, 0, "", "",
"67 f3 41 0f ae f0 \tumonitor %r8d",},
{{0xf2, 0x0f, 0xae, 0xf0, }, 4, 0, "", "",
"f2 0f ae f0 \tumwait %eax",},
{{0xf2, 0x41, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"f2 41 0f ae f0 \tumwait %r8d",},
{{0x48, 0x0f, 0x38, 0xf9, 0x03, }, 5, 0, "", "",
"48 0f 38 f9 03 \tmovdiri %rax,(%rbx)",},
{{0x48, 0x0f, 0x38, 0xf9, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"48 0f 38 f9 88 78 56 34 12 \tmovdiri %rcx,0x12345678(%rax)",},
{{0x66, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"66 0f 38 f8 18 \tmovdir64b (%rax),%rbx",},
{{0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%rax),%rcx",},
{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "",
"67 66 0f 38 f8 18 \tmovdir64b (%eax),%ebx",},
{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"67 66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%eax),%ecx",},
{{0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"f2 0f 38 f8 18 \tenqcmd (%rax),%rbx",},
{{0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%rax),%rcx",},
{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "",
"67 f2 0f 38 f8 18 \tenqcmd (%eax),%ebx",},
{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"67 f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%eax),%ecx",},
{{0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"f3 0f 38 f8 18 \tenqcmds (%rax),%rbx",},
{{0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%rax),%rcx",},
{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "",
"67 f3 0f 38 f8 18 \tenqcmds (%eax),%ebx",},
{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"67 f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%eax),%ecx",},
{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",
"0f 01 cf \tencls ",},
{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",
"0f 01 d7 \tenclu ",},
{{0x0f, 0x01, 0xc0, }, 3, 0, "", "",
"0f 01 c0 \tenclv ",},
{{0x0f, 0x01, 0xc5, }, 3, 0, "", "",
"0f 01 c5 \tpconfig ",},
{{0xf3, 0x0f, 0x09, }, 3, 0, "", "",
"f3 0f 09 \twbnoinvd ",},

109
tools/perf/arch/x86/tests/insn-x86-dat-src.c
View File

@ -1320,6 +1320,14 @@ int main(void)
asm volatile("xsaveopt (%r8)");
asm volatile("mfence");
/* cldemote m8 */
asm volatile("cldemote (%rax)");
asm volatile("cldemote (%r8)");
asm volatile("cldemote (0x12345678)");
asm volatile("cldemote 0x12345678(%rax,%rcx,8)");
asm volatile("cldemote 0x12345678(%r8,%rcx,8)");
/* xsavec mem */
asm volatile("xsavec (%rax)");
@ -1364,6 +1372,48 @@ int main(void)
asm volatile("ptwriteq 0x12345678(%rax,%rcx,8)");
asm volatile("ptwriteq 0x12345678(%r8,%rcx,8)");
/* tpause */
asm volatile("tpause %ebx");
asm volatile("tpause %r8d");
/* umonitor */
asm volatile("umonitor %eax");
asm volatile("umonitor %rax");
asm volatile("umonitor %r8d");
/* umwait */
asm volatile("umwait %eax");
asm volatile("umwait %r8d");
/* movdiri */
asm volatile("movdiri %rax,(%rbx)");
asm volatile("movdiri %rcx,0x12345678(%rax)");
/* movdir64b */
asm volatile("movdir64b (%rax),%rbx");
asm volatile("movdir64b 0x12345678(%rax),%rcx");
asm volatile("movdir64b (%eax),%ebx");
asm volatile("movdir64b 0x12345678(%eax),%ecx");
/* enqcmd */
asm volatile("enqcmd (%rax),%rbx");
asm volatile("enqcmd 0x12345678(%rax),%rcx");
asm volatile("enqcmd (%eax),%ebx");
asm volatile("enqcmd 0x12345678(%eax),%ecx");
/* enqcmds */
asm volatile("enqcmds (%rax),%rbx");
asm volatile("enqcmds 0x12345678(%rax),%rcx");
asm volatile("enqcmds (%eax),%ebx");
asm volatile("enqcmds 0x12345678(%eax),%ecx");
#else /* #ifdef __x86_64__ */
/* bound r32, mem (same op code as EVEX prefix) */
@ -2656,6 +2706,12 @@ int main(void)
asm volatile("xsaveopt (%eax)");
asm volatile("mfence");
/* cldemote m8 */
asm volatile("cldemote (%eax)");
asm volatile("cldemote (0x12345678)");
asm volatile("cldemote 0x12345678(%eax,%ecx,8)");
/* xsavec mem */
asm volatile("xsavec (%eax)");
@ -2684,8 +2740,61 @@ int main(void)
asm volatile("ptwritel (0x12345678)");
asm volatile("ptwritel 0x12345678(%eax,%ecx,8)");
/* tpause */
asm volatile("tpause %ebx");
/* umonitor */
asm volatile("umonitor %ax");
asm volatile("umonitor %eax");
/* umwait */
asm volatile("umwait %eax");
/* movdiri */
asm volatile("movdiri %eax,(%ebx)");
asm volatile("movdiri %ecx,0x12345678(%eax)");
/* movdir64b */
asm volatile("movdir64b (%eax),%ebx");
asm volatile("movdir64b 0x12345678(%eax),%ecx");
asm volatile("movdir64b (%si),%bx");
asm volatile("movdir64b 0x1234(%si),%cx");
/* enqcmd */
asm volatile("enqcmd (%eax),%ebx");
asm volatile("enqcmd 0x12345678(%eax),%ecx");
asm volatile("enqcmd (%si),%bx");
asm volatile("enqcmd 0x1234(%si),%cx");
/* enqcmds */
asm volatile("enqcmds (%eax),%ebx");
asm volatile("enqcmds 0x12345678(%eax),%ecx");
asm volatile("enqcmds (%si),%bx");
asm volatile("enqcmds 0x1234(%si),%cx");
#endif /* #ifndef __x86_64__ */
/* SGX */
asm volatile("encls");
asm volatile("enclu");
asm volatile("enclv");
/* pconfig */
asm volatile("pconfig");
/* wbnoinvd */
asm volatile("wbnoinvd");
/* Following line is a marker for the awk script - do not change */
asm volatile("rdtsc"); /* Stop here */

29
tools/perf/builtin-record.c
View File

@ -2148,6 +2148,31 @@ static const char * const __record_usage[] = {
};
const char * const *record_usage = __record_usage;
static int build_id__process_mmap(struct perf_tool *tool, union perf_event *event,
struct perf_sample *sample, struct machine *machine)
{
/*
* We already have the kernel maps, put in place via perf_session__create_kernel_maps()
* no need to add them twice.
*/
if (!(event->header.misc & PERF_RECORD_MISC_USER))
return 0;
return perf_event__process_mmap(tool, event, sample, machine);
}
static int build_id__process_mmap2(struct perf_tool *tool, union perf_event *event,
struct perf_sample *sample, struct machine *machine)
{
/*
* We already have the kernel maps, put in place via perf_session__create_kernel_maps()
* no need to add them twice.
*/
if (!(event->header.misc & PERF_RECORD_MISC_USER))
return 0;
return perf_event__process_mmap2(tool, event, sample, machine);
}
/*
* XXX Ideally would be local to cmd_record() and passed to a record__new
* because we need to have access to it in record__exit, that is called
@ -2177,8 +2202,8 @@ static struct record record = {
.exit = perf_event__process_exit,
.comm = perf_event__process_comm,
.namespaces = perf_event__process_namespaces,
.mmap = perf_event__process_mmap,
.mmap2 = perf_event__process_mmap2,
.mmap = build_id__process_mmap,
.mmap2 = build_id__process_mmap2,
.ordered_events = true,
},
};

2
tools/perf/builtin-stat.c
View File

@ -1307,6 +1307,7 @@ static int add_default_attributes(void)
if (stat_config.null_run)
return 0;
bzero(&errinfo, sizeof(errinfo));
if (transaction_run) {
/* Handle -T as -M transaction. Once platform specific metrics
* support has been added to the json files, all archictures
@ -1364,6 +1365,7 @@ static int add_default_attributes(void)
return -1;
}
if (err) {
parse_events_print_error(&errinfo, smi_cost_attrs);
fprintf(stderr, "Cannot set up SMI cost events\n");
return -1;
}

16
tools/perf/builtin-trace.c
View File

@ -3016,11 +3016,18 @@ static bool evlist__add_vfs_getname(struct evlist *evlist)
{
bool found = false;
struct evsel *evsel, *tmp;
struct parse_events_error err = { .idx = 0, };
int ret = parse_events(evlist, "probe:vfs_getname*", &err);
struct parse_events_error err;
int ret;
if (ret)
bzero(&err, sizeof(err));
ret = parse_events(evlist, "probe:vfs_getname*", &err);
if (ret) {
free(err.str);
free(err.help);
free(err.first_str);
free(err.first_help);
return false;
}
evlist__for_each_entry_safe(evlist, evsel, tmp) {
if (!strstarts(perf_evsel__name(evsel), "probe:vfs_getname"))
@ -4832,8 +4839,9 @@ int cmd_trace(int argc, const char **argv)
* wrong in more detail.
*/
if (trace.perfconfig_events != NULL) {
struct parse_events_error parse_err = { .idx = 0, };
struct parse_events_error parse_err;
bzero(&parse_err, sizeof(parse_err));
err = parse_events(trace.evlist, trace.perfconfig_events, &parse_err);
if (err) {
parse_events_print_error(&parse_err, trace.perfconfig_events);

8
tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
View File

@ -1,12 +1,12 @@
[
{
"ArchStdEvent": "BR_IMMED_SPEC",
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC",
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC",
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"PublicDescription": "Mispredicted or not predicted branch speculatively executed",
@ -19,5 +19,5 @@
"EventCode": "0x12",
"EventName": "BR_PRED",
"BriefDescription": "Predictable branch"
},
}
]

14
tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
View File

@ -1,26 +1,26 @@
[
{
"ArchStdEvent": "BUS_ACCESS_RD",
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR",
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED",
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL",
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH",
"ArchStdEvent": "BUS_ACCESS_PERIPH"
},
{
"PublicDescription": "Bus access",
"EventCode": "0x19",
"EventName": "BUS_ACCESS",
"BriefDescription": "Bus access"
},
}
]

28
tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
View File

@ -1,42 +1,42 @@
[
{
"ArchStdEvent": "L1D_CACHE_RD",
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR",
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL",
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD",
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR",
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD",
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR",
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD",
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR",
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN",
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL",
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"PublicDescription": "Level 1 instruction cache refill",
@ -187,5 +187,5 @@
"EventCode": "0x116",
"EventName": "PAGE_WALK_L2_STAGE2_HIT",
"BriefDescription": "Page walk, L2 stage-2 hit"
},
}
]

2
tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
View File

@ -16,5 +16,5 @@
"EventCode": "0x110",
"EventName": "Wait_CYCLES",
"BriefDescription": "Wait state cycle"
},
}
]

26
tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
View File

@ -1,39 +1,39 @@
[
{
"ArchStdEvent": "EXC_UNDEF",
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC",
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT",
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT",
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ",
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ",
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_HVC",
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT",
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT",
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER",
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ",
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ",
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"PublicDescription": "Exception taken",
@ -46,5 +46,5 @@
"EventCode": "0x0a",
"EventName": "EXC_RETURN",
"BriefDescription": "Exception return"
},
}
]

28
tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
View File

@ -1,42 +1,42 @@
[
{
"ArchStdEvent": "LD_SPEC",
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC",
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC",
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC",
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC",
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC",
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC",
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC",
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC",
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC",
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC",
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC",
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC",
"ArchStdEvent": "RC_ST_SPEC"
},
{
"PublicDescription": "Instruction architecturally executed, software increment",
@ -85,5 +85,5 @@
"EventCode": "0x100",
"EventName": "NOP_SPEC",
"BriefDescription": "Speculatively executed, NOP"
},
}
]

10
tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json
View File

@ -1,14 +1,14 @@
[
{
"ArchStdEvent": "LDREX_SPEC",
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC",
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC",
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC",
},
"ArchStdEvent": "STREX_SPEC"
}
]

12
tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
View File

@ -1,18 +1,18 @@
[
{
"ArchStdEvent": "MEM_ACCESS_RD",
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR",
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC",
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC",
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC",
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"PublicDescription": "Data memory access",
@ -25,5 +25,5 @@
"EventCode": "0x1a",
"EventName": "MEM_ERROR",
"BriefDescription": "Memory error"
},
}
]

2
tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json
View File

@ -46,5 +46,5 @@
"EventCode": "0x10f",
"EventName": "FX_STALL",
"BriefDescription": "FX stalled"
},
}
]

2
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json
View File

@ -1,6 +1,6 @@
[
{
"ArchStdEvent": "BR_INDIRECT_SPEC",
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"EventCode": "0xC9",

4
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
View File

@ -1,8 +1,8 @@
[
{
"ArchStdEvent": "BUS_ACCESS_RD",
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR",
"ArchStdEvent": "BUS_ACCESS_WR"
}
]

4
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
View File

@ -1,9 +1,9 @@
[
{
"ArchStdEvent": "EXC_IRQ",
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ",
"ArchStdEvent": "EXC_FIQ"
},
{
"EventCode": "0xC6",

120
tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
View File

@ -1,179 +1,179 @@
[
{
"ArchStdEvent": "L1D_CACHE_RD",
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR",
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR",
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_WB_VICTIM",
"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L1D_CACHE_WB_CLEAN",
"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL",
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD",
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR",
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD",
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR",
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD",
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR",
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN",
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL",
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "BUS_ACCESS_RD",
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR",
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_SHARED",
"ArchStdEvent": "BUS_ACCESS_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
"ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
},
{
"ArchStdEvent": "BUS_ACCESS_NORMAL",
"ArchStdEvent": "BUS_ACCESS_NORMAL"
},
{
"ArchStdEvent": "BUS_ACCESS_PERIPH",
"ArchStdEvent": "BUS_ACCESS_PERIPH"
},
{
"ArchStdEvent": "MEM_ACCESS_RD",
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR",
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC",
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC",
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC",
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"ArchStdEvent": "LDREX_SPEC",
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC",
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC",
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "LD_SPEC",
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC",
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC",
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC",
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC",
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC",
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC",
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC",
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_SPEC",
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC",
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC",
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC",
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC",
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC",
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "EXC_UNDEF",
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC",
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT",
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT",
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ",
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ",
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_SMC",
"ArchStdEvent": "EXC_SMC"
},
{
"ArchStdEvent": "EXC_HVC",
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT",
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT",
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER",
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ",
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ",
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"ArchStdEvent": "RC_LD_SPEC",
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC",
},
"ArchStdEvent": "RC_ST_SPEC"
}
]

158
tools/perf/pmu-events/arch/arm64/armv8-recommended.json
View File

@ -154,297 +154,297 @@
"EventCode": "0x61",
"EventName": "BUS_ACCESS_WR",
"BriefDescription": "Bus access write"
}
},
{
"PublicDescription": "Bus access, Normal, Cacheable, Shareable",
"EventCode": "0x62",
"EventName": "BUS_ACCESS_SHARED",
"BriefDescription": "Bus access, Normal, Cacheable, Shareable"
}
},
{
"PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
"EventCode": "0x63",
"EventName": "BUS_ACCESS_NOT_SHARED",
"BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
}
},
{
"PublicDescription": "Bus access, Normal",
"EventCode": "0x64",
"EventName": "BUS_ACCESS_NORMAL",
"BriefDescription": "Bus access, Normal"
}
},
{
"PublicDescription": "Bus access, peripheral",
"EventCode": "0x65",
"EventName": "BUS_ACCESS_PERIPH",
"BriefDescription": "Bus access, peripheral"
}
},
{
"PublicDescription": "Data memory access, read",
"EventCode": "0x66",
"EventName": "MEM_ACCESS_RD",
"BriefDescription": "Data memory access, read"
}
},
{
"PublicDescription": "Data memory access, write",
"EventCode": "0x67",
"EventName": "MEM_ACCESS_WR",
"BriefDescription": "Data memory access, write"
}
},
{
"PublicDescription": "Unaligned access, read",
"EventCode": "0x68",
"EventName": "UNALIGNED_LD_SPEC",
"BriefDescription": "Unaligned access, read"
}
},
{
"PublicDescription": "Unaligned access, write",
"EventCode": "0x69",
"EventName": "UNALIGNED_ST_SPEC",
"BriefDescription": "Unaligned access, write"
}
},
{
"PublicDescription": "Unaligned access",
"EventCode": "0x6a",
"EventName": "UNALIGNED_LDST_SPEC",
"BriefDescription": "Unaligned access"
}
},
{
"PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX",
"EventCode": "0x6c",
"EventName": "LDREX_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX"
}
},
{
"PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass",
"EventCode": "0x6d",
"EventName": "STREX_PASS_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass"
}
},
{
"PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail",
"EventCode": "0x6e",
"EventName": "STREX_FAIL_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail"
}
},
{
"PublicDescription": "Exclusive operation speculatively executed, STREX or STX",
"EventCode": "0x6f",
"EventName": "STREX_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX or STX"
}
},
{
"PublicDescription": "Operation speculatively executed, load",
"EventCode": "0x70",
"EventName": "LD_SPEC",
"BriefDescription": "Operation speculatively executed, load"
}
},
{
"PublicDescription": "Operation speculatively executed, store"
"PublicDescription": "Operation speculatively executed, store",
"EventCode": "0x71",
"EventName": "ST_SPEC",
"BriefDescription": "Operation speculatively executed, store"
}
},
{
"PublicDescription": "Operation speculatively executed, load or store",
"EventCode": "0x72",
"EventName": "LDST_SPEC",
"BriefDescription": "Operation speculatively executed, load or store"
}
},
{
"PublicDescription": "Operation speculatively executed, integer data processing",
"EventCode": "0x73",
"EventName": "DP_SPEC",
"BriefDescription": "Operation speculatively executed, integer data processing"
}
},
{
"PublicDescription": "Operation speculatively executed, Advanced SIMD instruction",
"EventCode": "0x74",
"EventName": "ASE_SPEC",
"BriefDescription": "Operation speculatively executed, Advanced SIMD instruction",
}
"BriefDescription": "Operation speculatively executed, Advanced SIMD instruction"
},
{
"PublicDescription": "Operation speculatively executed, floating-point instruction",
"EventCode": "0x75",
"EventName": "VFP_SPEC",
"BriefDescription": "Operation speculatively executed, floating-point instruction"
}
},
{
"PublicDescription": "Operation speculatively executed, software change of the PC",
"EventCode": "0x76",
"EventName": "PC_WRITE_SPEC",
"BriefDescription": "Operation speculatively executed, software change of the PC"
}
},
{
"PublicDescription": "Operation speculatively executed, Cryptographic instruction",
"EventCode": "0x77",
"EventName": "CRYPTO_SPEC",
"BriefDescription": "Operation speculatively executed, Cryptographic instruction"
}
},
{
"PublicDescription": "Branch speculatively executed, immediate branch"
"PublicDescription": "Branch speculatively executed, immediate branch",
"EventCode": "0x78",
"EventName": "BR_IMMED_SPEC",
"BriefDescription": "Branch speculatively executed, immediate branch"
}
},
{
"PublicDescription": "Branch speculatively executed, procedure return"
"PublicDescription": "Branch speculatively executed, procedure return",
"EventCode": "0x79",
"EventName": "BR_RETURN_SPEC",
"BriefDescription": "Branch speculatively executed, procedure return"
}
},
{
"PublicDescription": "Branch speculatively executed, indirect branch"
"PublicDescription": "Branch speculatively executed, indirect branch",
"EventCode": "0x7a",
"EventName": "BR_INDIRECT_SPEC",
"BriefDescription": "Branch speculatively executed, indirect branch"
}
},
{
"PublicDescription": "Barrier speculatively executed, ISB"
"PublicDescription": "Barrier speculatively executed, ISB",
"EventCode": "0x7c",
"EventName": "ISB_SPEC",
"BriefDescription": "Barrier speculatively executed, ISB"
}
},
{
"PublicDescription": "Barrier speculatively executed, DSB"
"PublicDescription": "Barrier speculatively executed, DSB",
"EventCode": "0x7d",
"EventName": "DSB_SPEC",
"BriefDescription": "Barrier speculatively executed, DSB"
}
},
{
"PublicDescription": "Barrier speculatively executed, DMB"
"PublicDescription": "Barrier speculatively executed, DMB",
"EventCode": "0x7e",
"EventName": "DMB_SPEC",
"BriefDescription": "Barrier speculatively executed, DMB"
}
},
{
"PublicDescription": "Exception taken, Other synchronous"
"PublicDescription": "Exception taken, Other synchronous",
"EventCode": "0x81",
"EventName": "EXC_UNDEF",
"BriefDescription": "Exception taken, Other synchronous"
}
},
{
"PublicDescription": "Exception taken, Supervisor Call"
"PublicDescription": "Exception taken, Supervisor Call",
"EventCode": "0x82",
"EventName": "EXC_SVC",
"BriefDescription": "Exception taken, Supervisor Call"
}
},
{
"PublicDescription": "Exception taken, Instruction Abort"
"PublicDescription": "Exception taken, Instruction Abort",
"EventCode": "0x83",
"EventName": "EXC_PABORT",
"BriefDescription": "Exception taken, Instruction Abort"
}
},
{
"PublicDescription": "Exception taken, Data Abort and SError"
"PublicDescription": "Exception taken, Data Abort and SError",
"EventCode": "0x84",
"EventName": "EXC_DABORT",
"BriefDescription": "Exception taken, Data Abort and SError"
}
},
{
"PublicDescription": "Exception taken, IRQ"
"PublicDescription": "Exception taken, IRQ",
"EventCode": "0x86",
"EventName": "EXC_IRQ",
"BriefDescription": "Exception taken, IRQ"
}
},
{
"PublicDescription": "Exception taken, FIQ"
"PublicDescription": "Exception taken, FIQ",
"EventCode": "0x87",
"EventName": "EXC_FIQ",
"BriefDescription": "Exception taken, FIQ"
}
},
{
"PublicDescription": "Exception taken, Secure Monitor Call"
"PublicDescription": "Exception taken, Secure Monitor Call",
"EventCode": "0x88",
"EventName": "EXC_SMC",
"BriefDescription": "Exception taken, Secure Monitor Call"
}
},
{
"PublicDescription": "Exception taken, Hypervisor Call"
"PublicDescription": "Exception taken, Hypervisor Call",
"EventCode": "0x8a",
"EventName": "EXC_HVC",
"BriefDescription": "Exception taken, Hypervisor Call"
}
},
{
"PublicDescription": "Exception taken, Instruction Abort not taken locally"
"PublicDescription": "Exception taken, Instruction Abort not taken locally",
"EventCode": "0x8b",
"EventName": "EXC_TRAP_PABORT",
"BriefDescription": "Exception taken, Instruction Abort not taken locally"
}
},
{
"PublicDescription": "Exception taken, Data Abort or SError not taken locally"
"PublicDescription": "Exception taken, Data Abort or SError not taken locally",
"EventCode": "0x8c",
"EventName": "EXC_TRAP_DABORT",
"BriefDescription": "Exception taken, Data Abort or SError not taken locally"
}
},
{
"PublicDescription": "Exception taken, Other traps not taken locally"
"PublicDescription": "Exception taken, Other traps not taken locally",
"EventCode": "0x8d",
"EventName": "EXC_TRAP_OTHER",
"BriefDescription": "Exception taken, Other traps not taken locally"
}
},
{
"PublicDescription": "Exception taken, IRQ not taken locally"
"PublicDescription": "Exception taken, IRQ not taken locally",
"EventCode": "0x8e",
"EventName": "EXC_TRAP_IRQ",
"BriefDescription": "Exception taken, IRQ not taken locally"
}
},
{
"PublicDescription": "Exception taken, FIQ not taken locally"
"PublicDescription": "Exception taken, FIQ not taken locally",
"EventCode": "0x8f",
"EventName": "EXC_TRAP_FIQ",
"BriefDescription": "Exception taken, FIQ not taken locally"
}
},
{
"PublicDescription": "Release consistency operation speculatively executed, Load-Acquire"
"PublicDescription": "Release consistency operation speculatively executed, Load-Acquire",
"EventCode": "0x90",
"EventName": "RC_LD_SPEC",
"BriefDescription": "Release consistency operation speculatively executed, Load-Acquire"
}
},
{
"PublicDescription": "Release consistency operation speculatively executed, Store-Release"
"PublicDescription": "Release consistency operation speculatively executed, Store-Release",
"EventCode": "0x91",
"EventName": "RC_ST_SPEC",
"BriefDescription": "Release consistency operation speculatively executed, Store-Release"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache access, read"
"PublicDescription": "Attributable Level 3 data or unified cache access, read",
"EventCode": "0xa0",
"EventName": "L3D_CACHE_RD",
"BriefDescription": "Attributable Level 3 data or unified cache access, read"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache access, write"
"PublicDescription": "Attributable Level 3 data or unified cache access, write",
"EventCode": "0xa1",
"EventName": "L3D_CACHE_WR",
"BriefDescription": "Attributable Level 3 data or unified cache access, write"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache refill, read"
"PublicDescription": "Attributable Level 3 data or unified cache refill, read",
"EventCode": "0xa2",
"EventName": "L3D_CACHE_REFILL_RD",
"BriefDescription": "Attributable Level 3 data or unified cache refill, read"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache refill, write"
"PublicDescription": "Attributable Level 3 data or unified cache refill, write",
"EventCode": "0xa3",
"EventName": "L3D_CACHE_REFILL_WR",
"BriefDescription": "Attributable Level 3 data or unified cache refill, write"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
"PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim",
"EventCode": "0xa6",
"EventName": "L3D_CACHE_WB_VICTIM",
"BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
"PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean",
"EventCode": "0xa7",
"EventName": "L3D_CACHE_WB_CLEAN",
"BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
}
},
{
"PublicDescription": "Attributable Level 3 data or unified cache access, invalidate"
"PublicDescription": "Attributable Level 3 data or unified cache access, invalidate",
"EventCode": "0xa8",
"EventName": "L3D_CACHE_INVAL",
"BriefDescription": "Attributable Level 3 data or unified cache access, invalidate"

74
tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
View File

@ -1,113 +1,113 @@
[
{
"ArchStdEvent": "L1D_CACHE_RD",
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR",
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR",
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_INNER",
"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
},
{
"ArchStdEvent": "L1D_CACHE_WB_VICTIM",
"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L1D_CACHE_WB_CLEAN",
"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL",
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD",
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR",
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L1D_TLB_RD",
"ArchStdEvent": "L1D_TLB_RD"
},
{
"ArchStdEvent": "L1D_TLB_WR",
"ArchStdEvent": "L1D_TLB_WR"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_RD",
"ArchStdEvent": "L2D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_WR",
"ArchStdEvent": "L2D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_TLB_RD",
"ArchStdEvent": "L2D_TLB_RD"
},
{
"ArchStdEvent": "L2D_TLB_WR",
"ArchStdEvent": "L2D_TLB_WR"
},
{
"ArchStdEvent": "BUS_ACCESS_RD",
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR",
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "MEM_ACCESS_RD",
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR",
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "UNALIGNED_LD_SPEC",
"ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_ST_SPEC",
"ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC",
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"ArchStdEvent": "EXC_UNDEF",
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC",
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT",
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT",
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ",
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ",
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_SMC",
"ArchStdEvent": "EXC_SMC"
},
{
"ArchStdEvent": "EXC_HVC",
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT",
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT",
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER",
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ",
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ",
"ArchStdEvent": "EXC_TRAP_FIQ"
}
]

60
tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
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@ -1,122 +1,122 @@
[
{
"ArchStdEvent": "L1D_CACHE_RD",
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR",
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR",
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_WB_VICTIM",
"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L1D_CACHE_WB_CLEAN",
"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL",
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD",
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR",
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L1D_TLB_RD",
"ArchStdEvent": "L1D_TLB_RD"
},
{
"ArchStdEvent": "L1D_TLB_WR",
"ArchStdEvent": "L1D_TLB_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD",
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR",
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD",
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR",
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN",
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL",
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"PublicDescription": "Level 1 instruction cache prefetch access count",
"EventCode": "0x102e",
"EventName": "L1I_CACHE_PRF",
"BriefDescription": "L1I cache prefetch access count",
"BriefDescription": "L1I cache prefetch access count"
},
{
"PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
"EventCode": "0x102f",
"EventName": "L1I_CACHE_PRF_REFILL",
"BriefDescription": "L1I cache miss due to prefetch access count",
"BriefDescription": "L1I cache miss due to prefetch access count"
},
{
"PublicDescription": "Instruction queue is empty",
"EventCode": "0x1043",
"EventName": "IQ_IS_EMPTY",
"BriefDescription": "Instruction queue is empty",
"BriefDescription": "Instruction queue is empty"
},
{
"PublicDescription": "Instruction fetch stall cycles",
"EventCode": "0x1044",
"EventName": "IF_IS_STALL",
"BriefDescription": "Instruction fetch stall cycles",
"BriefDescription": "Instruction fetch stall cycles"
},
{
"PublicDescription": "Instructions can receive, but not send",
"EventCode": "0x2014",
"EventName": "FETCH_BUBBLE",
"BriefDescription": "Instructions can receive, but not send",
"BriefDescription": "Instructions can receive, but not send"
},
{
"PublicDescription": "Prefetch request from LSU",
"EventCode": "0x6013",
"EventName": "PRF_REQ",
"BriefDescription": "Prefetch request from LSU",
"BriefDescription": "Prefetch request from LSU"
},
{
"PublicDescription": "Hit on prefetched data",
"EventCode": "0x6014",
"EventName": "HIT_ON_PRF",
"BriefDescription": "Hit on prefetched data",
"BriefDescription": "Hit on prefetched data"
},
{
"PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
"EventCode": "0x7001",
"EventName": "EXE_STALL_CYCLE",
"BriefDescription": "Cycles of that the number of issue ups are less than 4",
"BriefDescription": "Cycles of that the number of issue ups are less than 4"
},
{
"PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
"EventCode": "0x7004",
"EventName": "MEM_STALL_ANYLOAD",
"BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
"BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved"
},
{
"PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
"EventCode": "0x7006",
"EventName": "MEM_STALL_L1MISS",
"BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
"BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill"
},
{
"PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
"EventCode": "0x7007",
"EventName": "MEM_STALL_L2MISS",
"BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
},
"BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache"
}
]

18
tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
View File

@ -4,55 +4,55 @@
"EventName": "uncore_hisi_ddrc.flux_wr",
"BriefDescription": "DDRC total write operations",
"PublicDescription": "DDRC total write operations",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x01",
"EventName": "uncore_hisi_ddrc.flux_rd",
"BriefDescription": "DDRC total read operations",
"PublicDescription": "DDRC total read operations",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x02",
"EventName": "uncore_hisi_ddrc.flux_wcmd",
"BriefDescription": "DDRC write commands",
"PublicDescription": "DDRC write commands",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x03",
"EventName": "uncore_hisi_ddrc.flux_rcmd",
"BriefDescription": "DDRC read commands",
"PublicDescription": "DDRC read commands",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x04",
"EventName": "uncore_hisi_ddrc.pre_cmd",
"BriefDescription": "DDRC precharge commands",
"PublicDescription": "DDRC precharge commands",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x05",
"EventName": "uncore_hisi_ddrc.act_cmd",
"BriefDescription": "DDRC active commands",
"PublicDescription": "DDRC active commands",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x06",
"EventName": "uncore_hisi_ddrc.rnk_chg",
"BriefDescription": "DDRC rank commands",
"PublicDescription": "DDRC rank commands",
"Unit": "hisi_sccl,ddrc",
"Unit": "hisi_sccl,ddrc"
},
{
"EventCode": "0x07",
"EventName": "uncore_hisi_ddrc.rw_chg",
"BriefDescription": "DDRC read and write changes",
"PublicDescription": "DDRC read and write changes",
"Unit": "hisi_sccl,ddrc",
},
"Unit": "hisi_sccl,ddrc"
}
]

22
tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
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@ -4,69 +4,69 @@
"EventName": "uncore_hisi_hha.rx_ops_num",
"BriefDescription": "The number of all operations received by the HHA",
"PublicDescription": "The number of all operations received by the HHA",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x01",
"EventName": "uncore_hisi_hha.rx_outer",
"BriefDescription": "The number of all operations received by the HHA from another socket",
"PublicDescription": "The number of all operations received by the HHA from another socket",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x02",
"EventName": "uncore_hisi_hha.rx_sccl",
"BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket",
"PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x03",
"EventName": "uncore_hisi_hha.rx_ccix",
"BriefDescription": "Count of the number of operations that HHA has received from CCIX",
"PublicDescription": "Count of the number of operations that HHA has received from CCIX",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x1c",
"EventName": "uncore_hisi_hha.rd_ddr_64b",
"BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
"PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x1d",
"EventName": "uncore_hisi_hha.wr_ddr_64b",
"BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
"PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x1e",
"EventName": "uncore_hisi_hha.rd_ddr_128b",
"BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
"PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x1f",
"EventName": "uncore_hisi_hha.wr_ddr_128b",
"BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
"PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x20",
"EventName": "uncore_hisi_hha.spill_num",
"BriefDescription": "Count of the number of spill operations that the HHA has sent",
"PublicDescription": "Count of the number of spill operations that the HHA has sent",
"Unit": "hisi_sccl,hha",
"Unit": "hisi_sccl,hha"
},
{
"EventCode": "0x21",
"EventName": "uncore_hisi_hha.spill_success",
"BriefDescription": "Count of the number of successful spill operations that the HHA has sent",
"PublicDescription": "Count of the number of successful spill operations that the HHA has sent",
"Unit": "hisi_sccl,hha",
},
"Unit": "hisi_sccl,hha"
}
]

28
tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
View File

@ -4,90 +4,90 @@
"EventName": "uncore_hisi_l3c.rd_cpipe",
"BriefDescription": "Total read accesses",
"PublicDescription": "Total read accesses",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x01",
"EventName": "uncore_hisi_l3c.wr_cpipe",
"BriefDescription": "Total write accesses",
"PublicDescription": "Total write accesses",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x02",
"EventName": "uncore_hisi_l3c.rd_hit_cpipe",
"BriefDescription": "Total read hits",
"PublicDescription": "Total read hits",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x03",
"EventName": "uncore_hisi_l3c.wr_hit_cpipe",
"BriefDescription": "Total write hits",
"PublicDescription": "Total write hits",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x04",
"EventName": "uncore_hisi_l3c.victim_num",
"BriefDescription": "l3c precharge commands",
"PublicDescription": "l3c precharge commands",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x20",
"EventName": "uncore_hisi_l3c.rd_spipe",
"BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
"PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x21",
"EventName": "uncore_hisi_l3c.wr_spipe",
"BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
"PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x22",
"EventName": "uncore_hisi_l3c.rd_hit_spipe",
"BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
"PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x23",
"EventName": "uncore_hisi_l3c.wr_hit_spipe",
"BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
"PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x29",
"EventName": "uncore_hisi_l3c.back_invalid",
"BriefDescription": "Count of the number of L3C back invalid operations",
"PublicDescription": "Count of the number of L3C back invalid operations",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x40",
"EventName": "uncore_hisi_l3c.retry_cpu",
"BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
"PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x41",
"EventName": "uncore_hisi_l3c.retry_ring",
"BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
"PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
"Unit": "hisi_sccl,l3c",
"Unit": "hisi_sccl,l3c"
},
{
"EventCode": "0x42",
"EventName": "uncore_hisi_l3c.prefetch_drop",
"BriefDescription": "Count of the number of prefetch drops from this L3C",
"PublicDescription": "Count of the number of prefetch drops from this L3C",
"Unit": "hisi_sccl,l3c",
},
"Unit": "hisi_sccl,l3c"
}
]

60
tools/perf/pmu-events/arch/powerpc/power8/cache.json
View File

@ -1,176 +1,176 @@
[
{,
{
"EventCode": "0x4c048",
"EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x3c048",
"EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x3c04c",
"EventName": "PM_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x1c042",
"EventName": "PM_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x200fe",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1c04e",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x3c040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x4c040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x1c040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x4c042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x300fe",
"EventName": "PM_DATA_FROM_L3MISS",
"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c04e",
"EventName": "PM_DATA_FROM_L3MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x3c042",
"EventName": "PM_DATA_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x1c044",
"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x1c04c",
"EventName": "PM_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x4c04a",
"EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x1c048",
"EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c046",
"EventName": "PM_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x1c04a",
"EventName": "PM_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x3001a",
"EventName": "PM_DATA_TABLEWALK_CYC",
"BriefDescription": "Tablwalk Cycles (could be 1 or 2 active)",
"PublicDescription": "Data Tablewalk Active"
},
{,
{
"EventCode": "0x4e04e",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0xd094",
"EventName": "PM_DSLB_MISS",
"BriefDescription": "Data SLB Miss - Total of all segment sizes",
"PublicDescription": "Data SLB Miss - Total of all segment sizesData SLB misses"
},
{,
{
"EventCode": "0x1002c",
"EventName": "PM_L1_DCACHE_RELOADED_ALL",
"BriefDescription": "L1 data cache reloaded for demand or prefetch",
"PublicDescription": ""
},
{,
{
"EventCode": "0x300f6",
"EventName": "PM_L1_DCACHE_RELOAD_VALID",
"BriefDescription": "DL1 reloaded due to Demand Load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3e054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1",
"PublicDescription": ""
},
{,
{
"EventCode": "0x100ee",
"EventName": "PM_LD_REF_L1",
"BriefDescription": "All L1 D cache load references counted at finish, gated by reject",
"PublicDescription": "Load Ref count combined for all units"
},
{,
{
"EventCode": "0x300f0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1",
"PublicDescription": ""
},
}
]

6
tools/perf/pmu-events/arch/powerpc/power8/floating-point.json
View File

@ -1,14 +1,14 @@
[
{,
{
"EventCode": "0x2000e",
"EventName": "PM_FXU_BUSY",
"BriefDescription": "fxu0 busy and fxu1 busy",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1000e",
"EventName": "PM_FXU_IDLE",
"BriefDescription": "fxu0 idle and fxu1 idle",
"PublicDescription": ""
},
}
]

158
tools/perf/pmu-events/arch/powerpc/power8/frontend.json
View File

@ -1,470 +1,470 @@
[
{,
{
"EventCode": "0x2505e",
"EventName": "PM_BACK_BR_CMPL",
"BriefDescription": "Branch instruction completed with a target address less than current instruction address",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10068",
"EventName": "PM_BRU_FIN",
"BriefDescription": "Branch Instruction Finished",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "two path branch",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40060",
"EventName": "PM_BR_CMPL",
"BriefDescription": "Branch Instruction completed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x400f6",
"EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts",
"PublicDescription": ""
},
{,
{
"EventCode": "0x200fa",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10018",
"EventName": "PM_IC_DEMAND_CYC",
"BriefDescription": "Cycles when a demand ifetch was pending",
"PublicDescription": "Demand ifetch pending"
},
{,
{
"EventCode": "0x100f6",
"EventName": "PM_IERAT_RELOAD",
"BriefDescription": "Number of I-ERAT reloads",
"PublicDescription": "IERAT Reloaded (Miss)"
},
{,
{
"EventCode": "0x4006a",
"EventName": "PM_IERAT_RELOAD_16M",
"BriefDescription": "IERAT Reloaded (Miss) for a 16M page",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20064",
"EventName": "PM_IERAT_RELOAD_4K",
"BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)",
"PublicDescription": "IERAT Reloaded (Miss) for a 4k page"
},
{,
{
"EventCode": "0x3006a",
"EventName": "PM_IERAT_RELOAD_64K",
"BriefDescription": "IERAT Reloaded (Miss) for a 64k page",
"PublicDescription": ""
},
{,
{
"EventCode": "0x14050",
"EventName": "PM_INST_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
},
{,
{
"EventCode": "0x2",
"EventName": "PM_INST_CMPL",
"BriefDescription": "Number of PowerPC Instructions that completed",
"PublicDescription": "PPC Instructions Finished (completed)"
},
{,
{
"EventCode": "0x200f2",
"EventName": "PM_INST_DISP",
"BriefDescription": "PPC Dispatched",
"PublicDescription": ""
},
{,
{
"EventCode": "0x44048",
"EventName": "PM_INST_FROM_DL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x34048",
"EventName": "PM_INST_FROM_DL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x3404c",
"EventName": "PM_INST_FROM_DL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x4404c",
"EventName": "PM_INST_FROM_DMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x14042",
"EventName": "PM_INST_FROM_L2",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x1404e",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x34040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x44040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x24040",
"EventName": "PM_INST_FROM_L2_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x14040",
"EventName": "PM_INST_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x300fa",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
"PublicDescription": "Inst from L3 miss"
},
{,
{
"EventCode": "0x4404e",
"EventName": "PM_INST_FROM_L3MISS_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x1404c",
"EventName": "PM_INST_FROM_LL4",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x24048",
"EventName": "PM_INST_FROM_LMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x2404c",
"EventName": "PM_INST_FROM_MEMORY",
"BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x4404a",
"EventName": "PM_INST_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x1404a",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x2404a",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x3404a",
"EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
{
"EventCode": "0x24050",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch"
},
{,
{
"EventCode": "0x24052",
"EventName": "PM_INST_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
},
{,
{
"EventCode": "0x14052",
"EventName": "PM_INST_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch"
},
{,
{
"EventCode": "0x1003a",
"EventName": "PM_INST_IMC_MATCH_CMPL",
"BriefDescription": "IMC Match Count ( Not architected in P8)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
"PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch"
},
{,
{
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch",
"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch"
},
{,
{
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch"
},
{,
{
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
},
{,
{
"EventCode": "0x44050",
"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch"
},
{,
{
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x35048",
"EventName": "PM_IPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3504c",
"EventName": "PM_IPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4504c",
"EventName": "PM_IPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15042",
"EventName": "PM_IPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1504e",
"EventName": "PM_IPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x25040",
"EventName": "PM_IPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15040",
"EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x45042",
"EventName": "PM_IPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4504e",
"EventName": "PM_IPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x35042",
"EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1504c",
"EventName": "PM_IPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x25048",
"EventName": "PM_IPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2504c",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4504a",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1504a",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2504a",
"EventName": "PM_IPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3504a",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0xd096",
"EventName": "PM_ISLB_MISS",
"BriefDescription": "I SLB Miss",
"PublicDescription": ""
},
{,
{
"EventCode": "0x400fc",
"EventName": "PM_ITLB_MISS",
"BriefDescription": "ITLB Reloaded (always zero on POWER6)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x200fd",
"EventName": "PM_L1_ICACHE_MISS",
"BriefDescription": "Demand iCache Miss",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40012",
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
"BriefDescription": "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30068",
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
"BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x300f4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished when both threads in run_cycles",
"PublicDescription": "Concurrent Run Instructions"
},
{,
{
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Instructions completed in transactional state",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4e014",
"EventName": "PM_TM_TX_PASS_RUN_INST",
"BriefDescription": "run instructions spent in successful transactions",
"PublicDescription": ""
},
}
]

266
tools/perf/pmu-events/arch/powerpc/power8/marked.json
View File

@ -1,794 +1,794 @@
[
{,
{
"EventCode": "0x3515e",
"EventName": "PM_MRK_BACK_BR_CMPL",
"BriefDescription": "Marked branch instruction completed with a target address less than current instruction address",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2013a",
"EventName": "PM_MRK_BRU_FIN",
"BriefDescription": "bru marked instr finish",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1016e",
"EventName": "PM_MRK_BR_CMPL",
"BriefDescription": "Branch Instruction completed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x301e4",
"EventName": "PM_MRK_BR_MPRED_CMPL",
"BriefDescription": "Marked Branch Mispredicted",
"PublicDescription": ""
},
{,
{
"EventCode": "0x101e2",
"EventName": "PM_MRK_BR_TAKEN_CMPL",
"BriefDescription": "Marked Branch Taken completed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d148",
"EventName": "PM_MRK_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d148",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d14c",
"EventName": "PM_MRK_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c12c",
"EventName": "PM_MRK_DATA_FROM_DL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d14c",
"EventName": "PM_MRK_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d12c",
"EventName": "PM_MRK_DATA_FROM_DMEM_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d142",
"EventName": "PM_MRK_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d14e",
"EventName": "PM_MRK_DATA_FROM_L2MISS",
"BriefDescription": "Data cache reload L2 miss",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c12e",
"EventName": "PM_MRK_DATA_FROM_L2MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c122",
"EventName": "PM_MRK_DATA_FROM_L2_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d140",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c120",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d140",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d120",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d140",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d120",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d140",
"EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c120",
"EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d142",
"EventName": "PM_MRK_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x201e4",
"EventName": "PM_MRK_DATA_FROM_L3MISS",
"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d12e",
"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d122",
"EventName": "PM_MRK_DATA_FROM_L3_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d142",
"EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c122",
"EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d142",
"EventName": "PM_MRK_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d122",
"EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d144",
"EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c124",
"EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d14c",
"EventName": "PM_MRK_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c12c",
"EventName": "PM_MRK_DATA_FROM_LL4_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d148",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d14c",
"EventName": "PM_MRK_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d12c",
"EventName": "PM_MRK_DATA_FROM_MEMORY_CYC",
"BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d14a",
"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d12a",
"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d148",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c128",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d146",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d126",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d14a",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c12a",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d14a",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d12a",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d14a",
"EventName": "PM_MRK_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c12a",
"EventName": "PM_MRK_DATA_FROM_RMEM_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event",
"PublicDescription": ""
},
{,
{
"EventCode": "0x301e6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d154",
"EventName": "PM_MRK_DERAT_MISS_16G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d154",
"EventName": "PM_MRK_DERAT_MISS_16M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d156",
"EventName": "PM_MRK_DERAT_MISS_4K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20132",
"EventName": "PM_MRK_DFU_FIN",
"BriefDescription": "Decimal Unit marked Instruction Finish",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4f148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3f148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3f14c",
"EventName": "PM_MRK_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4f14c",
"EventName": "PM_MRK_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f142",
"EventName": "PM_MRK_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f14e",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f140",
"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4f142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4f14e",
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3f142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f142",
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f144",
"EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f14c",
"EventName": "PM_MRK_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f148",
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f14c",
"EventName": "PM_MRK_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4f14a",
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f148",
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f146",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f14a",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f14a",
"EventName": "PM_MRK_DPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3f14a",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x401e4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d158",
"EventName": "PM_MRK_DTLB_MISS_16G",
"BriefDescription": "Marked Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d156",
"EventName": "PM_MRK_DTLB_MISS_16M",
"BriefDescription": "Marked Data TLB Miss page size 16M",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d156",
"EventName": "PM_MRK_DTLB_MISS_4K",
"BriefDescription": "Marked Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3d156",
"EventName": "PM_MRK_DTLB_MISS_64K",
"BriefDescription": "Marked Data TLB Miss page size 64K",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40154",
"EventName": "PM_MRK_FAB_RSP_BKILL",
"BriefDescription": "Marked store had to do a bkill",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f150",
"EventName": "PM_MRK_FAB_RSP_BKILL_CYC",
"BriefDescription": "cycles L2 RC took for a bkill",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3015e",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2f152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4015e",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1015e",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4f150",
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
"BriefDescription": "cycles L2 RC took for a rwitm",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2015e",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20134",
"EventName": "PM_MRK_FXU_FIN",
"BriefDescription": "fxu marked instr finish",
"PublicDescription": ""
},
{,
{
"EventCode": "0x401e0",
"EventName": "PM_MRK_INST_CMPL",
"BriefDescription": "marked instruction completed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20130",
"EventName": "PM_MRK_INST_DECODED",
"BriefDescription": "marked instruction decoded",
"PublicDescription": "marked instruction decoded. Name from ISU?"
},
{,
{
"EventCode": "0x101e0",
"EventName": "PM_MRK_INST_DISP",
"BriefDescription": "The thread has dispatched a randomly sampled marked instruction",
"PublicDescription": "Marked Instruction dispatched"
},
{,
{
"EventCode": "0x30130",
"EventName": "PM_MRK_INST_FIN",
"BriefDescription": "marked instruction finished",
"PublicDescription": "marked instr finish any unit"
},
{,
{
"EventCode": "0x401e6",
"EventName": "PM_MRK_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
"PublicDescription": "n/a"
},
{,
{
"EventCode": "0x10132",
"EventName": "PM_MRK_INST_ISSUED",
"BriefDescription": "Marked instruction issued",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40134",
"EventName": "PM_MRK_INST_TIMEO",
"BriefDescription": "marked Instruction finish timeout (instruction lost)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x101e4",
"EventName": "PM_MRK_L1_ICACHE_MISS",
"BriefDescription": "sampled Instruction suffered an icache Miss",
"PublicDescription": "Marked L1 Icache Miss"
},
{,
{
"EventCode": "0x101ea",
"EventName": "PM_MRK_L1_RELOAD_VALID",
"BriefDescription": "Marked demand reload",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3012a",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1013e",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss cycles",
"PublicDescription": "Marked Load exposed Miss (use edge detect to count #)"
},
{,
{
"EventCode": "0x201e2",
"EventName": "PM_MRK_LD_MISS_L1",
"BriefDescription": "Marked DL1 Demand Miss counted at exec time",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4013e",
"EventName": "PM_MRK_LD_MISS_L1_CYC",
"BriefDescription": "Marked ld latency",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr finish",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1d15e",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Marked run cycles",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3013e",
"EventName": "PM_MRK_STALL_CMPLU_CYC",
"BriefDescription": "Marked Group completion Stall",
"PublicDescription": "Marked Group Completion Stall cycles (use edge detect to count #)"
},
{,
{
"EventCode": "0x3e158",
"EventName": "PM_MRK_STCX_FAIL",
"BriefDescription": "marked stcx failed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10134",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "marked store completed and sent to nest",
"PublicDescription": "Marked store completed"
},
{,
{
"EventCode": "0x30134",
"EventName": "PM_MRK_ST_CMPL_INT",
"BriefDescription": "marked store finished with intervention",
"PublicDescription": "marked store complete (data home) with intervention"
},
{,
{
"EventCode": "0x3f150",
"EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
"BriefDescription": "cycles to drain st from core to L2",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3012c",
"EventName": "PM_MRK_ST_FWD",
"BriefDescription": "Marked st forwards",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1f150",
"EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
"BriefDescription": "cycles from L2 rc disp to l2 rc completion",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20138",
"EventName": "PM_MRK_ST_NEST",
"BriefDescription": "Marked store sent to nest",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30132",
"EventName": "PM_MRK_VSU_FIN",
"BriefDescription": "VSU marked instr finish",
"PublicDescription": "vsu (fpu) marked instr finish"
},
{,
{
"EventCode": "0x3d15e",
"EventName": "PM_MULT_MRK",
"BriefDescription": "mult marked instr",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1515c",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15156",
"EventName": "PM_SYNC_MRK_FX_DIVIDE",
"BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1515a",
"EventName": "PM_SYNC_MRK_L2MISS",
"BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15154",
"EventName": "PM_SYNC_MRK_L3MISS",
"BriefDescription": "Marked L3 misses that can throw a synchronous interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x15150",
"EventName": "PM_SYNC_MRK_PROBE_NOP",
"BriefDescription": "Marked probeNops which can cause synchronous interrupts",
"PublicDescription": ""
},
}
]

72
tools/perf/pmu-events/arch/powerpc/power8/memory.json
View File

@ -1,212 +1,212 @@
[
{,
{
"EventCode": "0x10050",
"EventName": "PM_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)"
},
{,
{
"EventCode": "0x1c050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load"
},
{,
{
"EventCode": "0x4c04c",
"EventName": "PM_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c048",
"EventName": "PM_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c04c",
"EventName": "PM_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c04a",
"EventName": "PM_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x3c04a",
"EventName": "PM_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
{
"EventCode": "0x2c050",
"EventName": "PM_DATA_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load"
},
{,
{
"EventCode": "0x2c052",
"EventName": "PM_DATA_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
},
{,
{
"EventCode": "0x1c052",
"EventName": "PM_DATA_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load"
},
{,
{
"EventCode": "0x1c054",
"EventName": "PM_DATA_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c052",
"EventName": "PM_DATA_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load",
"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor a demand load"
},
{,
{
"EventCode": "0x3c050",
"EventName": "PM_DATA_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load"
},
{,
{
"EventCode": "0x3c052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
},
{,
{
"EventCode": "0x4c050",
"EventName": "PM_DATA_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load"
},
{,
{
"EventCode": "0x3e04c",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4e04c",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3e04a",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20050",
"EventName": "PM_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20052",
"EventName": "PM_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
},
{,
{
"EventCode": "0x10052",
"EventName": "PM_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x18082",
"EventName": "PM_L3_CO_MEPF",
"BriefDescription": "L3 CO of line in Mep state ( includes casthrough",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c058",
"EventName": "PM_MEM_CO",
"BriefDescription": "Memory castouts from this lpar",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control",
"PublicDescription": ""
},
{,
{
"EventCode": "0x40056",
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1c05e",
"EventName": "PM_MEM_LOC_THRESH_LSU_MED",
"BriefDescription": "Local memory above theshold for data prefetch",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c058",
"EventName": "PM_MEM_PREF",
"BriefDescription": "Memory prefetch for this lpar. Includes L4",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10056",
"EventName": "PM_MEM_READ",
"BriefDescription": "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3c05e",
"EventName": "PM_MEM_RWITM",
"BriefDescription": "Memory rwitm for this lpar",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3006e",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles",
"PublicDescription": "Nest reference clocks"
},
{,
{
"EventCode": "0x10054",
"EventName": "PM_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x40052",
"EventName": "PM_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x30050",
"EventName": "PM_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x30052",
"EventName": "PM_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
},
{,
{
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
}
]

1150
tools/perf/pmu-events/arch/powerpc/power8/other.json
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118
tools/perf/pmu-events/arch/powerpc/power8/pipeline.json
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@ -1,350 +1,350 @@
[
{,
{
"EventCode": "0x100f2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished",
"PublicDescription": "1 or more ppc insts finished (completed)"
},
{,
{
"EventCode": "0x400f2",
"EventName": "PM_1PLUS_PPC_DISP",
"BriefDescription": "Cycles at least one Instr Dispatched",
"PublicDescription": "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521"
},
{,
{
"EventCode": "0x100fa",
"EventName": "PM_ANY_THRD_RUN_CYC",
"BriefDescription": "One of threads in run_cycles",
"PublicDescription": "Any thread in run_cycles (was one thread in run_cycles)"
},
{,
{
"EventCode": "0x4000a",
"EventName": "PM_CMPLU_STALL",
"BriefDescription": "Completion stall",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Completion stall by Dcache miss",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c018",
"EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
"PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict"
},
{,
{
"EventCode": "0x4c01a",
"EventName": "PM_CMPLU_STALL_DMISS_L3MISS",
"BriefDescription": "Completion stall due to cache miss resolving missed the L3",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c018",
"EventName": "PM_CMPLU_STALL_DMISS_LMEM",
"BriefDescription": "Completion stall due to cache miss that resolves in local memory",
"PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory"
},
{,
{
"EventCode": "0x2c01c",
"EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
"PublicDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"
},
{,
{
"EventCode": "0x4c012",
"EventName": "PM_CMPLU_STALL_ERAT_MISS",
"BriefDescription": "Completion stall due to LSU reject ERAT miss",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d016",
"EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency fixed point instruction",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2d016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Completion stall due to FXU",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30036",
"EventName": "PM_CMPLU_STALL_HWSYNC",
"BriefDescription": "completion stall due to hwsync",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4d014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Completion stall due to a Load finish",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10036",
"EventName": "PM_CMPLU_STALL_LWSYNC",
"BriefDescription": "completion stall due to isync/lwsync",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30006",
"EventName": "PM_CMPLU_STALL_OTHER_CMPL",
"BriefDescription": "Instructions core completed while this tread was stalled",
"PublicDescription": "Instructions core completed while this thread was stalled"
},
{,
{
"EventCode": "0x4c01c",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1001c",
"EventName": "PM_CMPLU_STALL_THRD",
"BriefDescription": "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
"PublicDescription": "Completion stall due to thread conflict"
},
{,
{
"EventCode": "0x1e",
"EventName": "PM_CYC",
"BriefDescription": "Cycles",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10006",
"EventName": "PM_DISP_HELD",
"BriefDescription": "Dispatch Held",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4003c",
"EventName": "PM_DISP_HELD_SYNC_HOLD",
"BriefDescription": "Dispatch held due to SYNC hold",
"PublicDescription": ""
},
{,
{
"EventCode": "0x200f8",
"EventName": "PM_EXT_INT",
"BriefDescription": "external interrupt",
"PublicDescription": ""
},
{,
{
"EventCode": "0x400f8",
"EventName": "PM_FLUSH",
"BriefDescription": "Flush (any type)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "Completion Flush",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3000c",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B",
"PublicDescription": "Frequency is being slewed down due to Power Management"
},
{,
{
"EventCode": "0x4000c",
"EventName": "PM_FREQ_UP",
"BriefDescription": "Power Management: Above Threshold A",
"PublicDescription": "Frequency is being slewed up due to Power Management"
},
{,
{
"EventCode": "0x2000a",
"EventName": "PM_HV_CYC",
"BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
"PublicDescription": "cycles in hypervisor mode"
},
{,
{
"EventCode": "0x3405e",
"EventName": "PM_IFETCH_THROTTLE",
"BriefDescription": "Cycles in which Instruction fetch throttle was active",
"PublicDescription": "Cycles instruction fecth was throttled in IFU"
},
{,
{
"EventCode": "0x10014",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed",
"PublicDescription": "IOPS Completed"
},
{,
{
"EventCode": "0x3c058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1002e",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10062",
"EventName": "PM_LD_L3MISS_PEND_CYC",
"BriefDescription": "Cycles L3 miss was pending for this thread",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished an instruction (up to 2 per cycle)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2003e",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "LSU empty (lmq and srq empty)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e05c",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4e05c",
"EventName": "PM_LSU_REJECT_LHS",
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e05c",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU reject due to LMQ full ( 4 per cycle)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1001a",
"EventName": "PM_LSU_SRQ_FULL_CYC",
"BriefDescription": "Storage Queue is full and is blocking dispatch",
"PublicDescription": "SRQ is Full"
},
{,
{
"EventCode": "0x40014",
"EventName": "PM_PROBE_NOP_DISP",
"BriefDescription": "ProbeNops dispatched",
"PublicDescription": ""
},
{,
{
"EventCode": "0x600f4",
"EventName": "PM_RUN_CYC",
"BriefDescription": "Run_cycles",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3006c",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2006c",
"EventName": "PM_RUN_CYC_SMT4_MODE",
"BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
"PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
},
{,
{
"EventCode": "0x1006c",
"EventName": "PM_RUN_CYC_ST_MODE",
"BriefDescription": "Cycles run latch is set and core is in ST mode",
"PublicDescription": ""
},
{,
{
"EventCode": "0x500fa",
"EventName": "PM_RUN_INST_CMPL",
"BriefDescription": "Run_Instructions",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed",
"PublicDescription": ""
},
{,
{
"EventCode": "0x20016",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Store completion count",
"PublicDescription": ""
},
{,
{
"EventCode": "0x200f0",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store Instructions Finished",
"PublicDescription": "Store Instructions Finished (store sent to nest)"
},
{,
{
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when a tablewalk (I or D) is active",
"PublicDescription": "Tablewalk Active"
},
{,
{
"EventCode": "0x300f8",
"EventName": "PM_TB_BIT_TRANS",
"BriefDescription": "timebase event",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2000c",
"EventName": "PM_THRD_ALL_RUN_CYC",
"BriefDescription": "All Threads in Run_cycles (was both threads in run_cycles)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30058",
"EventName": "PM_TLBIE_FIN",
"BriefDescription": "tlbie finished",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e012",
"EventName": "PM_TM_TX_PASS_RUN_CYC",
"BriefDescription": "cycles spent in successful transactions",
"PublicDescription": "run cycles spent in successful transactions"
},
}
]

48
tools/perf/pmu-events/arch/powerpc/power8/pmc.json
View File

@ -1,140 +1,140 @@
[
{,
{
"EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30010",
"EventName": "PM_PMC2_OVERFLOW",
"BriefDescription": "Overflow from counter 2",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30020",
"EventName": "PM_PMC2_REWIND",
"BriefDescription": "PMC2 Rewind Event (did not match condition)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10022",
"EventName": "PM_PMC2_SAVED",
"BriefDescription": "PMC2 Rewind Value saved",
"PublicDescription": "PMC2 Rewind Value saved (matched condition)"
},
{,
{
"EventCode": "0x40010",
"EventName": "PM_PMC3_OVERFLOW",
"BriefDescription": "Overflow from counter 3",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event",
"PublicDescription": "PMC4 Rewind Event (did not match condition)"
},
{,
{
"EventCode": "0x30022",
"EventName": "PM_PMC4_SAVED",
"BriefDescription": "PMC4 Rewind Value saved (matched condition)",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10024",
"EventName": "PM_PMC5_OVERFLOW",
"BriefDescription": "Overflow from counter 5",
"PublicDescription": ""
},
{,
{
"EventCode": "0x30024",
"EventName": "PM_PMC6_OVERFLOW",
"BriefDescription": "Overflow from counter 6",
"PublicDescription": ""
},
{,
{
"EventCode": "0x400f4",
"EventName": "PM_RUN_PURR",
"BriefDescription": "Run_PURR",
"PublicDescription": ""
},
{,
{
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR",
"PublicDescription": ""
},
{,
{
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF",
"PublicDescription": ""
},
{,
{
"EventCode": "0x301ea",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024",
"PublicDescription": ""
},
{,
{
"EventCode": "0x401ea",
"EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128",
"PublicDescription": ""
},
{,
{
"EventCode": "0x401ec",
"EventName": "PM_THRESH_EXC_2048",
"BriefDescription": "Threshold counter exceeded a value of 2048",
"PublicDescription": ""
},
{,
{
"EventCode": "0x101e8",
"EventName": "PM_THRESH_EXC_256",
"BriefDescription": "Threshold counter exceed a count of 256",
"PublicDescription": ""
},
{,
{
"EventCode": "0x201e6",
"EventName": "PM_THRESH_EXC_32",
"BriefDescription": "Threshold counter exceeded a value of 32",
"PublicDescription": ""
},
{,
{
"EventCode": "0x101e6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096",
"PublicDescription": ""
},
{,
{
"EventCode": "0x201e8",
"EventName": "PM_THRESH_EXC_512",
"BriefDescription": "Threshold counter exceeded a value of 512",
"PublicDescription": ""
},
{,
{
"EventCode": "0x301e8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "IFU non-branch finished",
"PublicDescription": "Threshold counter exceeded a value of 64"
},
{,
{
"EventCode": "0x101ec",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4016e",
"EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold",
"PublicDescription": ""
},
}
]

60
tools/perf/pmu-events/arch/powerpc/power8/translation.json
View File

@ -1,176 +1,176 @@
[
{,
{
"EventCode": "0x4c054",
"EventName": "PM_DERAT_MISS_16G",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3c054",
"EventName": "PM_DERAT_MISS_16M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1c056",
"EventName": "PM_DERAT_MISS_4K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c054",
"EventName": "PM_DERAT_MISS_64K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4e048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3e048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e042",
"EventName": "PM_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e04e",
"EventName": "PM_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e040",
"EventName": "PM_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e040",
"EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4e042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3e042",
"EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e042",
"EventName": "PM_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e044",
"EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e04c",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e048",
"EventName": "PM_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e04c",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4e04a",
"EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e048",
"EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e046",
"EventName": "PM_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x1e04a",
"EventName": "PM_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2e04a",
"EventName": "PM_DPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request",
"PublicDescription": ""
},
{,
{
"EventCode": "0x300fc",
"EventName": "PM_DTLB_MISS",
"BriefDescription": "Data PTEG reload",
"PublicDescription": "Data PTEG Reloaded (DTLB Miss)"
},
{,
{
"EventCode": "0x1c058",
"EventName": "PM_DTLB_MISS_16G",
"BriefDescription": "Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
{
"EventCode": "0x4c056",
"EventName": "PM_DTLB_MISS_16M",
"BriefDescription": "Data TLB Miss page size 16M",
"PublicDescription": ""
},
{,
{
"EventCode": "0x2c056",
"EventName": "PM_DTLB_MISS_4K",
"BriefDescription": "Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
{
"EventCode": "0x3c056",
"EventName": "PM_DTLB_MISS_64K",
"BriefDescription": "Data TLB Miss page size 64K",
"PublicDescription": ""
},
{,
{
"EventCode": "0x200f6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss",
"PublicDescription": "DERAT Reloaded (Miss)"
},
{,
{
"EventCode": "0x20066",
"EventName": "PM_TLB_MISS",
"BriefDescription": "TLB Miss (I + D)",
"PublicDescription": ""
},
}
]

44
tools/perf/pmu-events/arch/powerpc/power9/cache.json
View File

@ -1,107 +1,107 @@
[
{,
{
"EventCode": "0x300F4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
},
{,
{
"EventCode": "0x1E056",
"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
},
{,
{
"EventCode": "0x4D016",
"EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
},
{,
{
"EventCode": "0x2D016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
{,
{
"EventCode": "0x4D12A",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
},
{,
{
"EventCode": "0x1003C",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
},
{,
{
"EventCode": "0x4C014",
"EventName": "PM_CMPLU_STALL_LMQ_FULL",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
},
{,
{
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x4D014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
},
{,
{
"EventCode": "0x2404A",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x1404A",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x401EA",
"EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128"
},
{,
{
"EventCode": "0x400F6",
"EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts"
},
{,
{
"EventCode": "0x2F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x101E6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096"
},
{,
{
"EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4C016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
},
{,
{
"EventCode": "0x2C01A",
"EventName": "PM_CMPLU_STALL_LHS",
"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
},
{,
{
"EventCode": "0x401E4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss"
},
{,
{
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
}
]
]

14
tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
View File

@ -1,32 +1,32 @@
[
{,
{
"EventCode": "0x1415A",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
},
{,
{
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control"
},
{,
{
"EventCode": "0x2D028",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
},
{,
{
"EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
},
{,
{
"EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
},
{,
{
"EventCode": "0x4016E",
"EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold"
}
]
]

142
tools/perf/pmu-events/arch/powerpc/power9/frontend.json
View File

@ -1,355 +1,355 @@
[
{,
{
"EventCode": "0x25044",
"EventName": "PM_IPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
},
{,
{
"EventCode": "0x101E8",
"EventName": "PM_THRESH_EXC_256",
"BriefDescription": "Threshold counter exceed a count of 256"
},
{,
{
"EventCode": "0x4504E",
"EventName": "PM_IPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request"
},
{,
{
"EventCode": "0x1006A",
"EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it"
},
{,
{
"EventCode": "0x4E016",
"EventName": "PM_CMPLU_STALL_LSAQ_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch"
},
{,
{
"EventCode": "0x1001A",
"EventName": "PM_LSU_SRQ_FULL_CYC",
"BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource"
},
{,
{
"EventCode": "0x1E15E",
"EventName": "PM_MRK_L2_TM_REQ_ABORT",
"BriefDescription": "TM abort"
},
{,
{
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch"
},
{,
{
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2"
},
{,
{
"EventCode": "0x4C044",
"EventName": "PM_DATA_FROM_L31_ECO_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x1C044",
"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load"
},
{,
{
"EventCode": "0x44050",
"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
},
{,
{
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim"
},
{,
{
"EventCode": "0x30014",
"EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe"
},
{,
{
"EventCode": "0x3E054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
{
"EventCode": "0x2E01A",
"EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
"BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete"
},
{,
{
"EventCode": "0x2D01C",
"EventName": "PM_CMPLU_STALL_STCX",
"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2"
},
{,
{
"EventCode": "0x2C010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction"
},
{,
{
"EventCode": "0x2C042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load"
},
{,
{
"EventCode": "0x4E012",
"EventName": "PM_CMPLU_STALL_MTFPSCR",
"BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)"
},
{,
{
"EventCode": "0x100F2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished"
},
{,
{
"EventCode": "0x3001C",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)"
},
{,
{
"EventCode": "0x15046",
"EventName": "PM_IPTEG_FROM_L31_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request"
},
{,
{
"EventCode": "0x1015E",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention"
},
{,
{
"EventCode": "0x101EC",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded"
},
{,
{
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event"
},
{,
{
"EventCode": "0x301EA",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024"
},
{,
{
"EventCode": "0x34056",
"EventName": "PM_CMPLU_STALL_LSU_MFSPR",
"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned"
},
{,
{
"EventCode": "0x44056",
"EventName": "PM_VECTOR_ST_CMPL",
"BriefDescription": "Number of vector store instructions completed"
},
{,
{
"EventCode": "0x2C124",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load"
},
{,
{
"EventCode": "0x4C12A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
{
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Run instructions completed in transactional state (gated by the run latch)"
},
{,
{
"EventCode": "0x2C014",
"EventName": "PM_CMPLU_STALL_STORE_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish"
},
{,
{
"EventCode": "0x3515A",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch"
},
{,
{
"EventCode": "0x3015E",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty"
},
{,
{
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF"
},
{,
{
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4"
},
{,
{
"EventCode": "0x3E04A",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2F152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim"
},
{,
{
"EventCode": "0x10004",
"EventName": "PM_CMPLU_STALL_LRQ_OTHER",
"BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others"
},
{,
{
"EventCode": "0x4F150",
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
"BriefDescription": "cycles L2 RC took for a rwitm"
},
{,
{
"EventCode": "0x4E042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x1F054",
"EventName": "PM_TLB_HIT",
"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT"
},
{,
{
"EventCode": "0x2C01E",
"EventName": "PM_CMPLU_STALL_SYNC_PMU_INT",
"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt"
},
{,
{
"EventCode": "0x24050",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed"
},
{,
{
"EventCode": "0x1515C",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt"
},
{,
{
"EventCode": "0x300FA",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
},
{,
{
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request"
},
{,
{
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt"
},
{,
{
"EventCode": "0x1E050",
"EventName": "PM_CMPLU_STALL_TEND",
"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2"
},
{,
{
"EventCode": "0x1013E",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss (use edge detect to count #)"
},
{,
{
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request"
},
{,
{
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch"
},
{,
{
"EventCode": "0x4015E",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count"
},
{,
{
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request"
},
{,
{
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch"
},
{,
{
"EventCode": "0x30026",
"EventName": "PM_CMPLU_STALL_STORE_DATA",
"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data"
},
{,
{
"EventCode": "0x301E6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes"
},
{,
{
"EventCode": "0x24154",
"EventName": "PM_THRESH_ACC",
"BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs."
},
{,
{
"EventCode": "0x2015E",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty"
},
{,
{
"EventCode": "0x200FA",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken"
},
{,
{
"EventCode": "0x35044",
"EventName": "PM_IPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request"
},
{,
{
"EventCode": "0x4C010",
"EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration"
},
{,
{
"EventCode": "0x4C01C",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward"
},
{,
{
"EventCode": "0x3515C",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
},
{,
{
"EventCode": "0x2D14C",
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished"
},
{,
{
"EventCode": "0x1003A",
"EventName": "PM_CMPLU_STALL_LSU_FIN",
"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish"
},
{,
{
"EventCode": "0x3012A",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done"
},
{,
{
"EventCode": "0x45044",
"EventName": "PM_IPTEG_FROM_L31_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request"

250
tools/perf/pmu-events/arch/powerpc/power9/marked.json
View File

@ -1,625 +1,625 @@
[
{,
{
"EventCode": "0x3013E",
"EventName": "PM_MRK_STALL_CMPLU_CYC",
"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)"
},
{,
{
"EventCode": "0x4F056",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3MISS",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache"
},
{,
{
"EventCode": "0x24158",
"EventName": "PM_MRK_INST",
"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens"
},
{,
{
"EventCode": "0x1E046",
"EventName": "PM_DPTEG_FROM_L31_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x3C04A",
"EventName": "PM_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load"
},
{,
{
"EventCode": "0x2C01C",
"EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)"
},
{,
{
"EventCode": "0x44040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x2E050",
"EventName": "PM_DARQ0_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use"
},
{,
{
"EventCode": "0x2D02E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation"
},
{,
{
"EventCode": "0x3F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation"
},
{,
{
"EventCode": "0x2E01E",
"EventName": "PM_CMPLU_STALL_NTC_FLUSH",
"BriefDescription": "Completion stall due to ntc flush"
},
{,
{
"EventCode": "0x1F14C",
"EventName": "PM_MRK_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x20130",
"EventName": "PM_MRK_INST_DECODED",
"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only"
},
{,
{
"EventCode": "0x3F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4D058",
"EventName": "PM_VECTOR_FLOP_CMPL",
"BriefDescription": "Vector FP instruction completed"
},
{,
{
"EventCode": "0x14040",
"EventName": "PM_INST_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x4404E",
"EventName": "PM_INST_FROM_L3MISS_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch"
},
{,
{
"EventCode": "0x3003A",
"EventName": "PM_CMPLU_STALL_EXCEPTION",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete"
},
{,
{
"EventCode": "0x4F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x3E044",
"EventName": "PM_DPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x300F6",
"EventName": "PM_L1_DCACHE_RELOAD_VALID",
"BriefDescription": "DL1 reloaded due to Demand Load"
},
{,
{
"EventCode": "0x1415E",
"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load"
},
{,
{
"EventCode": "0x1E052",
"EventName": "PM_CMPLU_STALL_SLB",
"BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
},
{,
{
"EventCode": "0x4404C",
"EventName": "PM_INST_FROM_DMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x3000E",
"EventName": "PM_FXU_1PLUS_BUSY",
"BriefDescription": "At least one of the 4 FXU units is busy"
},
{,
{
"EventCode": "0x2C048",
"EventName": "PM_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load"
},
{,
{
"EventCode": "0x3000A",
"EventName": "PM_CMPLU_STALL_PM",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle"
},
{,
{
"EventCode": "0x1504E",
"EventName": "PM_IPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request"
},
{,
{
"EventCode": "0x1C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load"
},
{,
{
"EventCode": "0x30008",
"EventName": "PM_DISP_STARVED",
"BriefDescription": "Dispatched Starved"
},
{,
{
"EventCode": "0x14042",
"EventName": "PM_INST_FROM_L2",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x4000C",
"EventName": "PM_FREQ_UP",
"BriefDescription": "Power Management: Above Threshold A"
},
{,
{
"EventCode": "0x3C050",
"EventName": "PM_DATA_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load"
},
{,
{
"EventCode": "0x25040",
"EventName": "PM_IPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request"
},
{,
{
"EventCode": "0x10132",
"EventName": "PM_MRK_INST_ISSUED",
"BriefDescription": "Marked instruction issued"
},
{,
{
"EventCode": "0x1C046",
"EventName": "PM_DATA_FROM_L31_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x2C044",
"EventName": "PM_DATA_FROM_L31_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x2C04A",
"EventName": "PM_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load"
},
{,
{
"EventCode": "0x24044",
"EventName": "PM_INST_FROM_L31_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x4C050",
"EventName": "PM_DATA_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load"
},
{,
{
"EventCode": "0x2C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load"
},
{,
{
"EventCode": "0x2F148",
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4D01A",
"EventName": "PM_CMPLU_STALL_EIEIO",
"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2"
},
{,
{
"EventCode": "0x4F14E",
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation"
},
{,
{
"EventCode": "0x1F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation"
},
{,
{
"EventCode": "0x30068",
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
"BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)"
},
{,
{
"EventCode": "0x4C04A",
"EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load"
},
{,
{
"EventCode": "0x400FE",
"EventName": "PM_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load"
},
{,
{
"EventCode": "0x3F058",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache"
},
{,
{
"EventCode": "0x3C052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load"
},
{,
{
"EventCode": "0x4D142",
"EventName": "PM_MRK_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load"
},
{,
{
"EventCode": "0x30050",
"EventName": "PM_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x30028",
"EventName": "PM_CMPLU_STALL_SPEC_FINISH",
"BriefDescription": "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC"
},
{,
{
"EventCode": "0x400F4",
"EventName": "PM_RUN_PURR",
"BriefDescription": "Run_PURR"
},
{,
{
"EventCode": "0x3404C",
"EventName": "PM_INST_FROM_DL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x3D05A",
"EventName": "PM_NTC_ISSUE_HELD_OTHER",
"BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU"
},
{,
{
"EventCode": "0x2E048",
"EventName": "PM_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2D02A",
"EventName": "PM_RADIX_PWC_L3_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache"
},
{,
{
"EventCode": "0x1F05C",
"EventName": "PM_RADIX_PWC_L3_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache"
},
{,
{
"EventCode": "0x4D04A",
"EventName": "PM_DARQ0_0_3_ENTRIES",
"BriefDescription": "Cycles in which 3 or less DARQ entries (out of 12) are in use"
},
{,
{
"EventCode": "0x1404C",
"EventName": "PM_INST_FROM_LL4",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x200FD",
"EventName": "PM_L1_ICACHE_MISS",
"BriefDescription": "Demand iCache Miss"
},
{,
{
"EventCode": "0x34040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x20138",
"EventName": "PM_MRK_ST_NEST",
"BriefDescription": "Marked store sent to nest"
},
{,
{
"EventCode": "0x44048",
"EventName": "PM_INST_FROM_DL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x35046",
"EventName": "PM_IPTEG_FROM_L21_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request"
},
{,
{
"EventCode": "0x4C04E",
"EventName": "PM_DATA_FROM_L3MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load"
},
{,
{
"EventCode": "0x401E0",
"EventName": "PM_MRK_INST_CMPL",
"BriefDescription": "marked instruction completed"
},
{,
{
"EventCode": "0x2C128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
},
{,
{
"EventCode": "0x34044",
"EventName": "PM_INST_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x4E018",
"EventName": "PM_CMPLU_STALL_NTC_DISP_FIN",
"BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch."
},
{,
{
"EventCode": "0x2E05E",
"EventName": "PM_LMQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LMQ has no pending load misses for this thread"
},
{,
{
"EventCode": "0x4C122",
"EventName": "PM_DARQ1_0_3_ENTRIES",
"BriefDescription": "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use"
},
{,
{
"EventCode": "0x4F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation"
},
{,
{
"EventCode": "0x14046",
"EventName": "PM_INST_FROM_L31_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x3012C",
"EventName": "PM_MRK_ST_FWD",
"BriefDescription": "Marked st forwards"
},
{,
{
"EventCode": "0x101E0",
"EventName": "PM_MRK_INST_DISP",
"BriefDescription": "The thread has dispatched a randomly sampled marked instruction"
},
{,
{
"EventCode": "0x1D058",
"EventName": "PM_DARQ0_10_12_ENTRIES",
"BriefDescription": "Cycles in which 10 or more DARQ entries (out of 12) are in use"
},
{,
{
"EventCode": "0x300FE",
"EventName": "PM_DATA_FROM_L3MISS",
"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)"
},
{,
{
"EventCode": "0x30006",
"EventName": "PM_CMPLU_STALL_OTHER_CMPL",
"BriefDescription": "Instructions the core completed while this tread was stalled"
},
{,
{
"EventCode": "0x1005C",
"EventName": "PM_CMPLU_STALL_DP",
"BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector"
},
{,
{
"EventCode": "0x1E042",
"EventName": "PM_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x1016E",
"EventName": "PM_MRK_BR_CMPL",
"BriefDescription": "Branch Instruction completed"
},
{,
{
"EventCode": "0x2013A",
"EventName": "PM_MRK_BRU_FIN",
"BriefDescription": "bru marked instr finish"
},
{,
{
"EventCode": "0x4F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache"
},
{,
{
"EventCode": "0x400FC",
"EventName": "PM_ITLB_MISS",
"BriefDescription": "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed"
},
{,
{
"EventCode": "0x1E044",
"EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4D05A",
"EventName": "PM_NON_MATH_FLOP_CMPL",
"BriefDescription": "Non FLOP operation completed"
},
{,
{
"EventCode": "0x101E2",
"EventName": "PM_MRK_BR_TAKEN_CMPL",
"BriefDescription": "Marked Branch Taken completed"
},
{,
{
"EventCode": "0x3E158",
"EventName": "PM_MRK_STCX_FAIL",
"BriefDescription": "marked stcx failed"
},
{,
{
"EventCode": "0x1C048",
"EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x1C054",
"EventName": "PM_DATA_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load"
},
{,
{
"EventCode": "0x4405E",
"EventName": "PM_DARQ_STORE_REJECT",
"BriefDescription": "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio"
},
{,
{
"EventCode": "0x1C042",
"EventName": "PM_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load"
},
{,
{
"EventCode": "0x1D14C",
"EventName": "PM_MRK_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load"
},
{,
{
"EventCode": "0x1006C",
"EventName": "PM_RUN_CYC_ST_MODE",
"BriefDescription": "Cycles run latch is set and core is in ST mode"
},
{,
{
"EventCode": "0x3C044",
"EventName": "PM_DATA_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x4C052",
"EventName": "PM_DATA_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load"
},
{,
{
"EventCode": "0x20050",
"EventName": "PM_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x1F150",
"EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
"BriefDescription": "cycles from L2 rc disp to l2 rc completion"
},
{,
{
"EventCode": "0x4505A",
"EventName": "PM_SP_FLOP_CMPL",
"BriefDescription": "SP instruction completed"
},
{,
{
"EventCode": "0x4000A",
"EventName": "PM_ISQ_36_44_ENTRIES",
"BriefDescription": "Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core"
},
{,
{
"EventCode": "0x2C12E",
"EventName": "PM_MRK_DATA_FROM_LL4_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load"
},
{,
{
"EventCode": "0x2C058",
"EventName": "PM_MEM_PREF",
"BriefDescription": "Memory prefetch for this thread. Includes L4"
},
{,
{
"EventCode": "0x40012",
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
"BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch"
},
{,
{
"EventCode": "0x3003C",
"EventName": "PM_CMPLU_STALL_NESTED_TEND",
"BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay"
},
{,
{
"EventCode": "0x3D05C",
"EventName": "PM_DISP_HELD_HB_FULL",
"BriefDescription": "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)"
},
{,
{
"EventCode": "0x30052",
"EventName": "PM_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x2E044",
"EventName": "PM_DPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x34048",
"EventName": "PM_INST_FROM_DL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x45042",
"EventName": "PM_IPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request"
},
{,
{
"EventCode": "0x15042",
"EventName": "PM_IPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request"
},
{,
{
"EventCode": "0x1C05E",
"EventName": "PM_MEM_LOC_THRESH_LSU_MED",
"BriefDescription": "Local memory above threshold for data prefetch"
},
{,
{
"EventCode": "0x40134",
"EventName": "PM_MRK_INST_TIMEO",
"BriefDescription": "marked Instruction finish timeout (instruction lost)"
},
{,
{
"EventCode": "0x1002C",
"EventName": "PM_L1_DCACHE_RELOADED_ALL",
"BriefDescription": "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well"
},
{,
{
"EventCode": "0x30130",
"EventName": "PM_MRK_INST_FIN",
"BriefDescription": "marked instruction finished"
},
{,
{
"EventCode": "0x1F14A",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x3504E",
"EventName": "PM_DARQ0_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use"
},
{,
{
"EventCode": "0x30064",
"EventName": "PM_DARQ_STORE_XMIT",
"BriefDescription": "The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core"
},
{,
{
"EventCode": "0x45046",
"EventName": "PM_IPTEG_FROM_L21_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request"
},
{,
{
"EventCode": "0x2C016",
"EventName": "PM_CMPLU_STALL_PASTE",
"BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response from L2"
},
{,
{
"EventCode": "0x24156",
"EventName": "PM_MRK_STCX_FIN",
"BriefDescription": "Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed"
},
{,
{
"EventCode": "0x15150",
"EventName": "PM_SYNC_MRK_PROBE_NOP",
"BriefDescription": "Marked probeNops which can cause synchronous interrupts"
},
{,
{
"EventCode": "0x301E4",
"EventName": "PM_MRK_BR_MPRED_CMPL",
"BriefDescription": "Marked Branch Mispredicted"

52
tools/perf/pmu-events/arch/powerpc/power9/memory.json
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@ -1,127 +1,127 @@
[
{,
{
"EventCode": "0x3006E",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
},
{,
{
"EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1"
},
{,
{
"EventCode": "0x2005A",
"EventName": "PM_DARQ1_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
},
{,
{
"EventCode": "0x3C048",
"EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
},
{,
{
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR"
},
{,
{
"EventCode": "0x200F6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss"
},
{,
{
"EventCode": "0x4C048",
"EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
},
{,
{
"EventCode": "0x1D15E",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
},
{,
{
"EventCode": "0x4003E",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed"
},
{,
{
"EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
},
{,
{
"EventCode": "0x4D02C",
"EventName": "PM_PMC1_REWIND",
"BriefDescription": "PMC1 rewind event"
},
{,
{
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
},
{,
{
"EventCode": "0x3404A",
"EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x301E2",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Marked store completed and sent to nest"
},
{,
{
"EventCode": "0x1C050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
},
{,
{
"EventCode": "0x4C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
},
{,
{
"EventCode": "0x2E05C",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
},
{,
{
"EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
},
{,
{
"EventCode": "0x3C058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished"
},
{,
{
"EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
},
{,
{
"EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
},
{,
{
"EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
},
{,
{
"EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
},
{,
{
"EventCode": "0x4D056",
"EventName": "PM_NON_FMA_FLOP_CMPL",
"BriefDescription": "Non FMA instruction completed"
},
{,
{
"EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
}
]
]

934
tools/perf/pmu-events/arch/powerpc/power9/other.json
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212
tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
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@ -1,530 +1,530 @@
[
{,
{
"EventCode": "0x4D04C",
"EventName": "PM_DFU_BUSY",
"BriefDescription": "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity"
},
{,
{
"EventCode": "0x100F6",
"EventName": "PM_IERAT_RELOAD",
"BriefDescription": "Number of I-ERAT reloads"
},
{,
{
"EventCode": "0x201E2",
"EventName": "PM_MRK_LD_MISS_L1",
"BriefDescription": "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
{
"EventCode": "0x40010",
"EventName": "PM_PMC3_OVERFLOW",
"BriefDescription": "Overflow from counter 3"
},
{,
{
"EventCode": "0x1005A",
"EventName": "PM_CMPLU_STALL_DFLONG",
"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle"
},
{,
{
"EventCode": "0x4D140",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x3F14C",
"EventName": "PM_MRK_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x1E040",
"EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x24052",
"EventName": "PM_FXU_IDLE",
"BriefDescription": "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle"
},
{,
{
"EventCode": "0x1E054",
"EventName": "PM_CMPLU_STALL",
"BriefDescription": "Nothing completed and ICT not empty"
},
{,
{
"EventCode": "0x2",
"EventName": "PM_INST_CMPL",
"BriefDescription": "Number of PowerPC Instructions that completed."
},
{,
{
"EventCode": "0x3D058",
"EventName": "PM_VSU_DP_FSQRT_FDIV",
"BriefDescription": "vector versions of fdiv,fsqrt"
},
{,
{
"EventCode": "0x10006",
"EventName": "PM_DISP_HELD",
"BriefDescription": "Dispatch Held"
},
{,
{
"EventCode": "0x200F8",
"EventName": "PM_EXT_INT",
"BriefDescription": "external interrupt"
},
{,
{
"EventCode": "0x20008",
"EventName": "PM_ICT_EMPTY_CYC",
"BriefDescription": "Cycles in which the ICT is completely empty. No itags are assigned to any thread"
},
{,
{
"EventCode": "0x4F146",
"EventName": "PM_MRK_DPTEG_FROM_L21_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x10056",
"EventName": "PM_MEM_READ",
"BriefDescription": "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4"
},
{,
{
"EventCode": "0x3C04C",
"EventName": "PM_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load"
},
{,
{
"EventCode": "0x4E046",
"EventName": "PM_DPTEG_FROM_L21_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2E016",
"EventName": "PM_NTC_ISSUE_HELD_ARB",
"BriefDescription": "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)"
},
{,
{
"EventCode": "0x15156",
"EventName": "PM_SYNC_MRK_FX_DIVIDE",
"BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt"
},
{,
{
"EventCode": "0x1C056",
"EventName": "PM_DERAT_MISS_4K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
},
{,
{
"EventCode": "0x2F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4C15C",
"EventName": "PM_MRK_DERAT_MISS_16G_1G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radix mode)"
},
{,
{
"EventCode": "0x10024",
"EventName": "PM_PMC5_OVERFLOW",
"BriefDescription": "Overflow from counter 5"
},
{,
{
"EventCode": "0x4505E",
"EventName": "PM_FLOP_CMPL",
"BriefDescription": "Floating Point Operation Finished"
},
{,
{
"EventCode": "0x2C018",
"EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"
},
{,
{
"EventCode": "0x4006A",
"EventName": "PM_IERAT_RELOAD_16M",
"BriefDescription": "IERAT Reloaded (Miss) for a 16M page"
},
{,
{
"EventCode": "0x4E010",
"EventName": "PM_ICT_NOSLOT_IC_L3MISS",
"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache"
},
{,
{
"EventCode": "0x4D01C",
"EventName": "PM_ICT_NOSLOT_DISP_HELD_SYNC",
"BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch"
},
{,
{
"EventCode": "0x2D01A",
"EventName": "PM_ICT_NOSLOT_IC_MISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss"
},
{,
{
"EventCode": "0x4F14A",
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x30058",
"EventName": "PM_TLBIE_FIN",
"BriefDescription": "tlbie finished"
},
{,
{
"EventCode": "0x100F8",
"EventName": "PM_ICT_NOSLOT_CYC",
"BriefDescription": "Number of cycles the ICT has no itags assigned to this thread"
},
{,
{
"EventCode": "0x3E042",
"EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x1F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x1F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation"
},
{,
{
"EventCode": "0x1D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
{
"EventCode": "0x10050",
"EventName": "PM_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x45058",
"EventName": "PM_IC_MISS_CMPL",
"BriefDescription": "Non-speculative icache miss, counted at completion"
},
{,
{
"EventCode": "0x2D150",
"EventName": "PM_MRK_DERAT_MISS_4K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K"
},
{,
{
"EventCode": "0x34058",
"EventName": "PM_ICT_NOSLOT_BR_MPRED_ICMISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss and branch mispred"
},
{,
{
"EventCode": "0x10022",
"EventName": "PM_PMC2_SAVED",
"BriefDescription": "PMC2 Rewind Value saved"
},
{,
{
"EventCode": "0x2000A",
"EventName": "PM_HV_CYC",
"BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration"
},
{,
{
"EventCode": "0x1F144",
"EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x300FC",
"EventName": "PM_DTLB_MISS",
"BriefDescription": "Data PTEG reload"
},
{,
{
"EventCode": "0x2C046",
"EventName": "PM_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load"
},
{,
{
"EventCode": "0x20052",
"EventName": "PM_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x3F05A",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache"
},
{,
{
"EventCode": "0x1E04A",
"EventName": "PM_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x10064",
"EventName": "PM_ICT_NOSLOT_DISP_HELD_TBEGIN",
"BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch"
},
{,
{
"EventCode": "0x2E046",
"EventName": "PM_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4F14C",
"EventName": "PM_MRK_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2E042",
"EventName": "PM_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2D012",
"EventName": "PM_CMPLU_STALL_DFU",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle"
},
{,
{
"EventCode": "0x3C054",
"EventName": "PM_DERAT_MISS_16M_2M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M (HPT mode) or 2M (Radix mode)"
},
{,
{
"EventCode": "0x4C04C",
"EventName": "PM_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load"
},
{,
{
"EventCode": "0x30022",
"EventName": "PM_PMC4_SAVED",
"BriefDescription": "PMC4 Rewind Value saved (matched condition)"
},
{,
{
"EventCode": "0x200F4",
"EventName": "PM_RUN_CYC",
"BriefDescription": "Run_cycles"
},
{,
{
"EventCode": "0x400F2",
"EventName": "PM_1PLUS_PPC_DISP",
"BriefDescription": "Cycles at least one Instr Dispatched"
},
{,
{
"EventCode": "0x3D148",
"EventName": "PM_MRK_DATA_FROM_L21_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x2F146",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4E01A",
"EventName": "PM_ICT_NOSLOT_DISP_HELD",
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason"
},
{,
{
"EventCode": "0x401EC",
"EventName": "PM_THRESH_EXC_2048",
"BriefDescription": "Threshold counter exceeded a value of 2048"
},
{,
{
"EventCode": "0x35150",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
{
"EventCode": "0x3E052",
"EventName": "PM_ICT_NOSLOT_IC_L3",
"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from the local L3"
},
{,
{
"EventCode": "0x2405A",
"EventName": "PM_NTC_FIN",
"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack"
},
{,
{
"EventCode": "0x40052",
"EventName": "PM_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x30056",
"EventName": "PM_TM_ABORTS",
"BriefDescription": "Number of TM transactions aborted"
},
{,
{
"EventCode": "0x2404C",
"EventName": "PM_INST_FROM_MEMORY",
"BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x30024",
"EventName": "PM_PMC6_OVERFLOW",
"BriefDescription": "Overflow from counter 6"
},
{,
{
"EventCode": "0x10068",
"EventName": "PM_BRU_FIN",
"BriefDescription": "Branch Instruction Finished"
},
{,
{
"EventCode": "0x3D154",
"EventName": "PM_MRK_DERAT_MISS_16M_2M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M (hpt mode) or 2M (radix mode)"
},
{,
{
"EventCode": "0x30020",
"EventName": "PM_PMC2_REWIND",
"BriefDescription": "PMC2 Rewind Event (did not match condition)"
},
{,
{
"EventCode": "0x40064",
"EventName": "PM_DUMMY2_REMOVE_ME",
"BriefDescription": "Space holder for LS_PC_RELOAD_RA"
},
{,
{
"EventCode": "0x3F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4D01E",
"EventName": "PM_ICT_NOSLOT_BR_MPRED",
"BriefDescription": "Ict empty for this thread due to branch mispred"
},
{,
{
"EventCode": "0x1F148",
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x3E046",
"EventName": "PM_DPTEG_FROM_L21_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x14052",
"EventName": "PM_INST_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch"
},
{,
{
"EventCode": "0xD0A8",
"EventName": "PM_DSLB_MISS",
"BriefDescription": "gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))"
},
{,
{
"EventCode": "0x4C058",
"EventName": "PM_MEM_CO",
"BriefDescription": "Memory castouts from this thread"
},
{,
{
"EventCode": "0x40004",
"EventName": "PM_FXU_FIN",
"BriefDescription": "The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete."
},
{,
{
"EventCode": "0x2C054",
"EventName": "PM_DERAT_MISS_64K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K"
},
{,
{
"EventCode": "0x10018",
"EventName": "PM_IC_DEMAND_CYC",
"BriefDescription": "Icache miss demand cycles"
},
{,
{
"EventCode": "0x2D14E",
"EventName": "PM_MRK_DATA_FROM_L21_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x3405C",
"EventName": "PM_CMPLU_STALL_DPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
},
{,
{
"EventCode": "0x4D052",
"EventName": "PM_2FLOP_CMPL",
"BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg "
},
{,
{
"EventCode": "0x1F142",
"EventName": "PM_MRK_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x40062",
"EventName": "PM_DUMMY1_REMOVE_ME",
"BriefDescription": "Space holder for L2_PC_PM_MK_LDST_SCOPE_PRED_STATUS"
},
{,
{
"EventCode": "0x4C012",
"EventName": "PM_CMPLU_STALL_ERAT_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a translation miss"
},
{,
{
"EventCode": "0x4D050",
"EventName": "PM_VSU_NON_FLOP_CMPL",
"BriefDescription": "Non FLOP operation completed"
},
{,
{
"EventCode": "0x2E012",
"EventName": "PM_TM_TX_PASS_RUN_CYC",
"BriefDescription": "cycles spent in successful transactions"
},
{,
{
"EventCode": "0x4D04E",
"EventName": "PM_VSU_FSQRT_FDIV",
"BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only"
},
{,
{
"EventCode": "0x4C120",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load"
},
{,
{
"EventCode": "0x10062",
"EventName": "PM_LD_L3MISS_PEND_CYC",
"BriefDescription": "Cycles L3 miss was pending for this thread"
},
{,
{
"EventCode": "0x2F14C",
"EventName": "PM_MRK_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x14050",
"EventName": "PM_INST_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch"
},
{,
{
"EventCode": "0x2000E",
"EventName": "PM_FXU_BUSY",
"BriefDescription": "Cycles in which all 4 FXUs are busy. The FXU is running at capacity"
},
{,
{
"EventCode": "0x20066",
"EventName": "PM_TLB_MISS",
"BriefDescription": "TLB Miss (I + D)"
},
{,
{
"EventCode": "0x10054",
"EventName": "PM_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x4D124",
"EventName": "PM_MRK_DATA_FROM_L31_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x400F8",
"EventName": "PM_FLUSH",
"BriefDescription": "Flush (any type)"
},
{,
{
"EventCode": "0x30004",
"EventName": "PM_CMPLU_STALL_EMQ_FULL",
"BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full"
},
{,
{
"EventCode": "0x1D154",
"EventName": "PM_MRK_DATA_FROM_L21_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load"

48
tools/perf/pmu-events/arch/powerpc/power9/pmc.json
View File

@ -1,117 +1,117 @@
[
{,
{
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased"
},
{,
{
"EventCode": "0x40056",
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium"
},
{,
{
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event"
},
{,
{
"EventCode": "0x4F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x301E8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "Threshold counter exceeded a value of 64"
},
{,
{
"EventCode": "0x4E04E",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
{
"EventCode": "0x1F14E",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4D018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit"
},
{,
{
"EventCode": "0x45052",
"EventName": "PM_4FLOP_CMPL",
"BriefDescription": "4 FLOP instruction completed"
},
{,
{
"EventCode": "0x3D142",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
},
{,
{
"EventCode": "0x4C01E",
"EventName": "PM_CMPLU_STALL_CRYPTO",
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
},
{,
{
"EventCode": "0x3000C",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B"
},
{,
{
"EventCode": "0x4D128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
},
{,
{
"EventCode": "0x4D054",
"EventName": "PM_8FLOP_CMPL",
"BriefDescription": "8 FLOP instruction completed"
},
{,
{
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when an instruction tablewalk is active"
},
{,
{
"EventCode": "0x2C012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
},
{,
{
"EventCode": "0x2E04C",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x3F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x4F142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state"
},
{,
{
"EventCode": "0x1E04C",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x45050",
"EventName": "PM_1FLOP_CMPL",
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
}
]
]

92
tools/perf/pmu-events/arch/powerpc/power9/translation.json
View File

@ -1,227 +1,227 @@
[
{,
{
"EventCode": "0x1E",
"EventName": "PM_CYC",
"BriefDescription": "Processor cycles"
},
{,
{
"EventCode": "0x30010",
"EventName": "PM_PMC2_OVERFLOW",
"BriefDescription": "Overflow from counter 2"
},
{,
{
"EventCode": "0x3C046",
"EventName": "PM_DATA_FROM_L21_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x4D05C",
"EventName": "PM_DP_QP_FLOP_CMPL",
"BriefDescription": "Double-Precion or Quad-Precision instruction completed"
},
{,
{
"EventCode": "0x4E04C",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x20016",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store finish count. Includes speculative activity"
},
{,
{
"EventCode": "0x1504A",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
},
{,
{
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr PPC finish"
},
{,
{
"EventCode": "0x3C05C",
"EventName": "PM_CMPLU_STALL_VFXU",
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
{,
{
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
},
{,
{
"EventCode": "0x2011C",
"EventName": "PM_MRK_NTC_CYC",
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)"
},
{,
{
"EventCode": "0x3E048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x2E018",
"EventName": "PM_CMPLU_STALL_VFXLONG",
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)"
},
{,
{
"EventCode": "0x1C04E",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load"
},
{,
{
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
},
{,
{
"EventCode": "0x34046",
"EventName": "PM_INST_FROM_L21_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x1E058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed"
},
{,
{
"EventCode": "0x300F0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1"
},
{,
{
"EventCode": "0x4C046",
"EventName": "PM_DATA_FROM_L21_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load"
},
{,
{
"EventCode": "0x2504A",
"EventName": "PM_IPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
},
{,
{
"EventCode": "0x2003E",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)"
},
{,
{
"EventCode": "0x201E6",
"EventName": "PM_THRESH_EXC_32",
"BriefDescription": "Threshold counter exceeded a value of 32"
},
{,
{
"EventCode": "0x4405C",
"EventName": "PM_CMPLU_STALL_VDP",
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector"
},
{,
{
"EventCode": "0x4D010",
"EventName": "PM_PMC1_SAVED",
"BriefDescription": "PMC1 Rewind Value saved"
},
{,
{
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x200FE",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
},
{,
{
"EventCode": "0x2D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
{
"EventCode": "0x10028",
"EventName": "PM_STALL_END_ICT_EMPTY",
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread"
},
{,
{
"EventCode": "0x2504C",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request"
},
{,
{
"EventCode": "0x4504A",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
},
{,
{
"EventCode": "0x1404E",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x4E048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x200F0",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
},
{,
{
"EventCode": "0x4E05C",
"EventName": "PM_LSU_REJECT_LHS",
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)"
},
{,
{
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x3E04C",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
{
"EventCode": "0x1F15E",
"EventName": "PM_MRK_PROBE_NOP_CMPL",
"BriefDescription": "Marked probeNops completed"
},
{,
{
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished"
},
{,
{
"EventCode": "0x1D142",
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
{
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)"
},
{,
{
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
},
{,
{
"EventCode": "0x3504A",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request"
},
{,
{
"EventCode": "0x3C05A",
"EventName": "PM_CMPLU_STALL_VDPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
},
{,
{
"EventCode": "0x2E01C",
"EventName": "PM_CMPLU_STALL_TLBIE",
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2"
}
]
]

12
tools/perf/scripts/python/exported-sql-viewer.py
View File

@ -637,7 +637,7 @@ class CallGraphRootItem(CallGraphLevelItemBase):
self.query_done = True
if_has_calls = ""
if IsSelectable(glb.db, "comms", columns = "has_calls"):
if_has_calls = " WHERE has_calls = TRUE"
if_has_calls = " WHERE has_calls = " + glb.dbref.TRUE
query = QSqlQuery(glb.db)
QueryExec(query, "SELECT id, comm FROM comms" + if_has_calls)
while query.next():
@ -918,7 +918,7 @@ class CallTreeRootItem(CallGraphLevelItemBase):
self.query_done = True
if_has_calls = ""
if IsSelectable(glb.db, "comms", columns = "has_calls"):
if_has_calls = " WHERE has_calls = TRUE"
if_has_calls = " WHERE has_calls = " + glb.dbref.TRUE
query = QSqlQuery(glb.db)
QueryExec(query, "SELECT id, comm FROM comms" + if_has_calls)
while query.next():
@ -1290,7 +1290,7 @@ class SwitchGraphData(GraphData):
QueryExec(query, "SELECT id, c_time"
" FROM comms"
" WHERE c_thread_id = " + str(thread_id) +
" AND exec_flag = TRUE"
" AND exec_flag = " + self.collection.glb.dbref.TRUE +
" AND c_time >= " + str(start_time) +
" AND c_time <= " + str(end_time) +
" ORDER BY c_time, id")
@ -5016,6 +5016,12 @@ class DBRef():
def __init__(self, is_sqlite3, dbname):
self.is_sqlite3 = is_sqlite3
self.dbname = dbname
self.TRUE = "TRUE"
self.FALSE = "FALSE"
# SQLite prior to version 3.23 does not support TRUE and FALSE
if self.is_sqlite3:
self.TRUE = "1"
self.FALSE = "0"
def Open(self, connection_name):
dbname = self.dbname

2
tools/perf/tests/map_groups.c
View File

@ -25,7 +25,7 @@ static int check_maps(struct map_def *merged, unsigned int size, struct map_grou
TEST_ASSERT_VAL("wrong map start", map->start == merged[i].start);
TEST_ASSERT_VAL("wrong map end", map->end == merged[i].end);
TEST_ASSERT_VAL("wrong map name", !strcmp(map->dso->name, merged[i].name));
TEST_ASSERT_VAL("wrong map refcnt", refcount_read(&map->refcnt) == 2);
TEST_ASSERT_VAL("wrong map refcnt", refcount_read(&map->refcnt) == 1);
i++;
}

3
tools/perf/tests/parse-events.c
View File

@ -1768,10 +1768,11 @@ static struct terms_test test__terms[] = {
static int test_event(struct evlist_test *e)
{
struct parse_events_error err = { .idx = 0, };
struct parse_events_error err;
struct evlist *evlist;
int ret;
bzero(&err, sizeof(err));
if (e->valid && !e->valid()) {
pr_debug("... SKIP");
return 0;

62
tools/perf/util/dwarf-aux.c
View File

@ -59,6 +59,51 @@ const char *cu_get_comp_dir(Dwarf_Die *cu_die)
return dwarf_formstring(&attr);
}
/* Unlike dwarf_getsrc_die(), cu_getsrc_die() only returns statement line */
static Dwarf_Line *cu_getsrc_die(Dwarf_Die *cu_die, Dwarf_Addr addr)
{
Dwarf_Addr laddr;
Dwarf_Lines *lines;
Dwarf_Line *line;
size_t nlines, l, u, n;
bool flag;
if (dwarf_getsrclines(cu_die, &lines, &nlines) != 0 ||
nlines == 0)
return NULL;
/* Lines are sorted by address, use binary search */
l = 0; u = nlines - 1;
while (l < u) {
n = u - (u - l) / 2;
line = dwarf_onesrcline(lines, n);
if (!line || dwarf_lineaddr(line, &laddr) != 0)
return NULL;
if (addr < laddr)
u = n - 1;
else
l = n;
}
/* Going backward to find the lowest line */
do {
line = dwarf_onesrcline(lines, --l);
if (!line || dwarf_lineaddr(line, &laddr) != 0)
return NULL;
} while (laddr == addr);
l++;
/* Going foward to find the statement line */
do {
line = dwarf_onesrcline(lines, l++);
if (!line || dwarf_lineaddr(line, &laddr) != 0 ||
dwarf_linebeginstatement(line, &flag) != 0)
return NULL;
if (laddr > addr)
return NULL;
} while (!flag);
return line;
}
/**
* cu_find_lineinfo - Get a line number and file name for given address
* @cu_die: a CU DIE
@ -72,17 +117,26 @@ int cu_find_lineinfo(Dwarf_Die *cu_die, unsigned long addr,
const char **fname, int *lineno)
{
Dwarf_Line *line;
Dwarf_Addr laddr;
Dwarf_Die die_mem;
Dwarf_Addr faddr;
line = dwarf_getsrc_die(cu_die, (Dwarf_Addr)addr);
if (line && dwarf_lineaddr(line, &laddr) == 0 &&
addr == (unsigned long)laddr && dwarf_lineno(line, lineno) == 0) {
if (die_find_realfunc(cu_die, (Dwarf_Addr)addr, &die_mem)
&& die_entrypc(&die_mem, &faddr) == 0 &&
faddr == addr) {
*fname = dwarf_decl_file(&die_mem);
dwarf_decl_line(&die_mem, lineno);
goto out;
}
line = cu_getsrc_die(cu_die, (Dwarf_Addr)addr);
if (line && dwarf_lineno(line, lineno) == 0) {
*fname = dwarf_linesrc(line, NULL, NULL);
if (!*fname)
/* line number is useless without filename */
*lineno = 0;
}
out:
return *lineno ?: -ENOENT;
}

43
tools/perf/util/machine.c
View File

@ -772,45 +772,16 @@ int machine__process_ksymbol(struct machine *machine __maybe_unused,
return machine__process_ksymbol_register(machine, event, sample);
}
static void dso__adjust_kmod_long_name(struct dso *dso, const char *filename)
{
const char *dup_filename;
if (!filename || !dso || !dso->long_name)
return;
if (dso->long_name[0] != '[')
return;
if (!strchr(filename, '/'))
return;
dup_filename = strdup(filename);
if (!dup_filename)
return;
dso__set_long_name(dso, dup_filename, true);
}
struct map *machine__findnew_module_map(struct machine *machine, u64 start,
const char *filename)
static struct map *machine__addnew_module_map(struct machine *machine, u64 start,
const char *filename)
{
struct map *map = NULL;
struct dso *dso = NULL;
struct kmod_path m;
struct dso *dso;
if (kmod_path__parse_name(&m, filename))
return NULL;
map = map_groups__find_by_name(&machine->kmaps, m.name);
if (map) {
/*
* If the map's dso is an offline module, give dso__load()
* a chance to find the file path of that module by fixing
* long_name.
*/
dso__adjust_kmod_long_name(map->dso, filename);
goto out;
}
dso = machine__findnew_module_dso(machine, &m, filename);
if (dso == NULL)
goto out;
@ -1409,7 +1380,7 @@ static int machine__create_module(void *arg, const char *name, u64 start,
if (arch__fix_module_text_start(&start, &size, name) < 0)
return -1;
map = machine__findnew_module_map(machine, start, name);
map = machine__addnew_module_map(machine, start, name);
if (map == NULL)
return -1;
map->end = start + size;
@ -1584,8 +1555,8 @@ static int machine__process_kernel_mmap_event(struct machine *machine,
strlen(machine->mmap_name) - 1) == 0;
if (event->mmap.filename[0] == '/' ||
(!is_kernel_mmap && event->mmap.filename[0] == '[')) {
map = machine__findnew_module_map(machine, event->mmap.start,
event->mmap.filename);
map = machine__addnew_module_map(machine, event->mmap.start,
event->mmap.filename);
if (map == NULL)
goto out_problem;
@ -2414,7 +2385,7 @@ static int thread__resolve_callchain_sample(struct thread *thread,
}
check_calls:
if (callchain_param.order != ORDER_CALLEE) {
if (chain && callchain_param.order != ORDER_CALLEE) {
err = find_prev_cpumode(chain, thread, cursor, parent, root_al,
&cpumode, chain->nr - first_call);
if (err)

2
tools/perf/util/machine.h
View File

@ -221,8 +221,6 @@ struct symbol *machine__find_kernel_symbol_by_name(struct machine *machine,
return map_groups__find_symbol_by_name(&machine->kmaps, name, mapp);
}
struct map *machine__findnew_module_map(struct machine *machine, u64 start,
const char *filename);
int arch__fix_module_text_start(u64 *start, u64 *size, const char *name);
int machine__load_kallsyms(struct machine *machine, const char *filename);

118
tools/perf/util/map.c
View File

@ -26,7 +26,6 @@
#include "ui/ui.h"
static void __maps__insert(struct maps *maps, struct map *map);
static void __maps__insert_name(struct maps *maps, struct map *map);
static inline int is_anon_memory(const char *filename, u32 flags)
{
@ -566,7 +565,6 @@ u64 map__objdump_2mem(struct map *map, u64 ip)
static void maps__init(struct maps *maps)
{
maps->entries = RB_ROOT;
maps->names = RB_ROOT;
init_rwsem(&maps->lock);
}
@ -574,12 +572,64 @@ void map_groups__init(struct map_groups *mg, struct machine *machine)
{
maps__init(&mg->maps);
mg->machine = machine;
mg->last_search_by_name = NULL;
mg->nr_maps = 0;
mg->maps_by_name = NULL;
refcount_set(&mg->refcnt, 1);
}
static void __map_groups__free_maps_by_name(struct map_groups *mg)
{
/*
* Free everything to try to do it from the rbtree in the next search
*/
zfree(&mg->maps_by_name);
mg->nr_maps_allocated = 0;
}
void map_groups__insert(struct map_groups *mg, struct map *map)
{
maps__insert(&mg->maps, map);
struct maps *maps = &mg->maps;
down_write(&maps->lock);
__maps__insert(maps, map);
++mg->nr_maps;
/*
* If we already performed some search by name, then we need to add the just
* inserted map and resort.
*/
if (mg->maps_by_name) {
if (mg->nr_maps > mg->nr_maps_allocated) {
int nr_allocate = mg->nr_maps * 2;
struct map **maps_by_name = realloc(mg->maps_by_name, nr_allocate * sizeof(map));
if (maps_by_name == NULL) {
__map_groups__free_maps_by_name(mg);
return;
}
mg->maps_by_name = maps_by_name;
mg->nr_maps_allocated = nr_allocate;
}
mg->maps_by_name[mg->nr_maps - 1] = map;
__map_groups__sort_by_name(mg);
}
up_write(&maps->lock);
}
void map_groups__remove(struct map_groups *mg, struct map *map)
{
struct maps *maps = &mg->maps;
down_write(&maps->lock);
if (mg->last_search_by_name == map)
mg->last_search_by_name = NULL;
__maps__remove(maps, map);
--mg->nr_maps;
if (mg->maps_by_name)
__map_groups__free_maps_by_name(mg);
up_write(&maps->lock);
}
static void __maps__purge(struct maps *maps)
@ -592,21 +642,10 @@ static void __maps__purge(struct maps *maps)
}
}
static void __maps__purge_names(struct maps *maps)
{
struct map *pos, *next;
maps__for_each_entry_by_name_safe(maps, pos, next) {
rb_erase_init(&pos->rb_node_name, &maps->names);
map__put(pos);
}
}
static void maps__exit(struct maps *maps)
{
down_write(&maps->lock);
__maps__purge(maps);
__maps__purge_names(maps);
up_write(&maps->lock);
}
@ -745,7 +784,6 @@ size_t map_groups__fprintf(struct map_groups *mg, FILE *fp)
static void __map_groups__insert(struct map_groups *mg, struct map *map)
{
__maps__insert(&mg->maps, map);
__maps__insert_name(&mg->maps, map);
}
int map_groups__fixup_overlappings(struct map_groups *mg, struct map *map, FILE *fp)
@ -902,42 +940,17 @@ static void __maps__insert(struct maps *maps, struct map *map)
map__get(map);
}
static void __maps__insert_name(struct maps *maps, struct map *map)
{
struct rb_node **p = &maps->names.rb_node;
struct rb_node *parent = NULL;
struct map *m;
int rc;
while (*p != NULL) {
parent = *p;
m = rb_entry(parent, struct map, rb_node_name);
rc = strcmp(m->dso->short_name, map->dso->short_name);
if (rc < 0)
p = &(*p)->rb_left;
else
p = &(*p)->rb_right;
}
rb_link_node(&map->rb_node_name, parent, p);
rb_insert_color(&map->rb_node_name, &maps->names);
map__get(map);
}
void maps__insert(struct maps *maps, struct map *map)
{
down_write(&maps->lock);
__maps__insert(maps, map);
__maps__insert_name(maps, map);
up_write(&maps->lock);
}
static void __maps__remove(struct maps *maps, struct map *map)
void __maps__remove(struct maps *maps, struct map *map)
{
rb_erase_init(&map->rb_node, &maps->entries);
map__put(map);
rb_erase_init(&map->rb_node_name, &maps->names);
map__put(map);
}
void maps__remove(struct maps *maps, struct map *map)
@ -994,29 +1007,6 @@ struct map *map__next(struct map *map)
return map ? __map__next(map) : NULL;
}
struct map *maps__first_by_name(struct maps *maps)
{
struct rb_node *first = rb_first(&maps->names);
if (first)
return rb_entry(first, struct map, rb_node_name);
return NULL;
}
static struct map *__map__next_by_name(struct map *map)
{
struct rb_node *next = rb_next(&map->rb_node_name);
if (next)
return rb_entry(next, struct map, rb_node_name);
return NULL;
}
struct map *map__next_by_name(struct map *map)
{
return map ? __map__next_by_name(map) : NULL;
}
struct kmap *__map__kmap(struct map *map)
{
if (!map->dso || !map->dso->kernel)

7
tools/perf/util/map.h
View File

@ -23,13 +23,11 @@ struct map {
struct rb_node rb_node;
struct list_head node;
};
struct rb_node rb_node_name;
u64 start;
u64 end;
bool erange_warned;
u32 priv;
bool erange_warned:1;
bool priv:1;
u32 prot;
u32 flags;
u64 pgoff;
u64 reloc;
u32 maj, min; /* only valid for MMAP2 record */
@ -43,6 +41,7 @@ struct map {
struct dso *dso;
refcount_t refcnt;
u32 flags;
};
struct kmap;

21
tools/perf/util/map_groups.h
View File

@ -16,12 +16,12 @@ struct thread;
struct maps {
struct rb_root entries;
struct rb_root names;
struct rw_semaphore lock;
};
void maps__insert(struct maps *maps, struct map *map);
void maps__remove(struct maps *maps, struct map *map);
void __maps__remove(struct maps *maps, struct map *map);
struct map *maps__find(struct maps *maps, u64 addr);
struct map *maps__first(struct maps *maps);
struct map *map__next(struct map *map);
@ -33,19 +33,15 @@ struct map *map__next(struct map *map);
for (map = maps__first(maps), next = map__next(map); map; map = next, next = map__next(map))
struct symbol *maps__find_symbol_by_name(struct maps *maps, const char *name, struct map **mapp);
struct map *maps__first_by_name(struct maps *maps);
struct map *map__next_by_name(struct map *map);
#define maps__for_each_entry_by_name(maps, map) \
for (map = maps__first_by_name(maps); map; map = map__next_by_name(map))
#define maps__for_each_entry_by_name_safe(maps, map, next) \
for (map = maps__first_by_name(maps), next = map__next_by_name(map); map; map = next, next = map__next_by_name(map))
struct map_groups {
struct maps maps;
struct machine *machine;
struct map *last_search_by_name;
struct map **maps_by_name;
refcount_t refcnt;
unsigned int nr_maps;
unsigned int nr_maps_allocated;
#ifdef HAVE_LIBUNWIND_SUPPORT
void *addr_space;
struct unwind_libunwind_ops *unwind_libunwind_ops;
@ -79,10 +75,7 @@ size_t map_groups__fprintf(struct map_groups *mg, FILE *fp);
void map_groups__insert(struct map_groups *mg, struct map *map);
static inline void map_groups__remove(struct map_groups *mg, struct map *map)
{
maps__remove(&mg->maps, map);
}
void map_groups__remove(struct map_groups *mg, struct map *map);
static inline struct map *map_groups__find(struct map_groups *mg, u64 addr)
{
@ -108,4 +101,6 @@ struct map *map_groups__find_by_name(struct map_groups *mg, const char *name);
int map_groups__merge_in(struct map_groups *kmaps, struct map *new_map);
void __map_groups__sort_by_name(struct map_groups *mg);
#endif // __PERF_MAP_GROUPS_H

2
tools/perf/util/metricgroup.c
View File

@ -523,7 +523,7 @@ int metricgroup__parse_groups(const struct option *opt,
if (ret)
return ret;
pr_debug("adding %s\n", extra_events.buf);
memset(&parse_error, 0, sizeof(struct parse_events_error));
bzero(&parse_error, sizeof(parse_error));
ret = parse_events(perf_evlist, extra_events.buf, &parse_error);
if (ret) {
parse_events_print_error(&parse_error, extra_events.buf);

78
tools/perf/util/parse-events.c
View File

@ -189,12 +189,29 @@ void parse_events__handle_error(struct parse_events_error *err, int idx,
free(help);
return;
}
WARN_ONCE(err->str, "WARNING: multiple event parsing errors\n");
err->idx = idx;
free(err->str);
err->str = str;
free(err->help);
err->help = help;
switch (err->num_errors) {
case 0:
err->idx = idx;
err->str = str;
err->help = help;
break;
case 1:
err->first_idx = err->idx;
err->idx = idx;
err->first_str = err->str;
err->str = str;
err->first_help = err->help;
err->help = help;
break;
default:
WARN_ONCE(1, "WARNING: multiple event parsing errors\n");
free(err->str);
err->str = str;
free(err->help);
err->help = help;
break;
}
err->num_errors++;
}
struct tracepoint_path *tracepoint_id_to_path(u64 config)
@ -1349,7 +1366,7 @@ int parse_events_add_pmu(struct parse_events_state *parse_state,
if (asprintf(&err_str,
"Cannot find PMU `%s'. Missing kernel support?",
name) >= 0)
parse_events__handle_error(err, -1, err_str, NULL);
parse_events__handle_error(err, 0, err_str, NULL);
return -EINVAL;
}
@ -2007,15 +2024,14 @@ static int get_term_width(void)
return ws.ws_col > MAX_WIDTH ? MAX_WIDTH : ws.ws_col;
}
void parse_events_print_error(struct parse_events_error *err,
const char *event)
static void __parse_events_print_error(int err_idx, const char *err_str,
const char *err_help, const char *event)
{
const char *str = "invalid or unsupported event: ";
char _buf[MAX_WIDTH];
char *buf = (char *) event;
int idx = 0;
if (err->str) {
if (err_str) {
/* -2 for extra '' in the final fprintf */
int width = get_term_width() - 2;
int len_event = strlen(event);
@ -2038,8 +2054,8 @@ void parse_events_print_error(struct parse_events_error *err,
buf = _buf;
/* We're cutting from the beginning. */
if (err->idx > max_err_idx)
cut = err->idx - max_err_idx;
if (err_idx > max_err_idx)
cut = err_idx - max_err_idx;
strncpy(buf, event + cut, max_len);
@ -2052,16 +2068,33 @@ void parse_events_print_error(struct parse_events_error *err,
buf[max_len] = 0;
}
idx = len_str + err->idx - cut;
idx = len_str + err_idx - cut;
}
fprintf(stderr, "%s'%s'\n", str, buf);
if (idx) {
fprintf(stderr, "%*s\\___ %s\n", idx + 1, "", err->str);
if (err->help)
fprintf(stderr, "\n%s\n", err->help);
zfree(&err->str);
zfree(&err->help);
fprintf(stderr, "%*s\\___ %s\n", idx + 1, "", err_str);
if (err_help)
fprintf(stderr, "\n%s\n", err_help);
}
}
void parse_events_print_error(struct parse_events_error *err,
const char *event)
{
if (!err->num_errors)
return;
__parse_events_print_error(err->idx, err->str, err->help, event);
zfree(&err->str);
zfree(&err->help);
if (err->num_errors > 1) {
fputs("\nInitial error:\n", stderr);
__parse_events_print_error(err->first_idx, err->first_str,
err->first_help, event);
zfree(&err->first_str);
zfree(&err->first_help);
}
}
@ -2071,8 +2104,11 @@ int parse_events_option(const struct option *opt, const char *str,
int unset __maybe_unused)
{
struct evlist *evlist = *(struct evlist **)opt->value;
struct parse_events_error err = { .idx = 0, };
int ret = parse_events(evlist, str, &err);
struct parse_events_error err;
int ret;
bzero(&err, sizeof(err));
ret = parse_events(evlist, str, &err);
if (ret) {
parse_events_print_error(&err, str);

4
tools/perf/util/parse-events.h
View File

@ -110,9 +110,13 @@ struct parse_events_term {
};
struct parse_events_error {
int num_errors; /* number of errors encountered */
int idx; /* index in the parsed string */
char *str; /* string to display at the index */
char *help; /* optional help string */
int first_idx;/* as above, but for the first encountered error */
char *first_str;
char *first_help;
};
struct parse_events_state {

19
tools/perf/util/probe-event.c
View File

@ -46,7 +46,7 @@
#define PERFPROBE_GROUP "probe"
bool probe_event_dry_run; /* Dry run flag */
struct probe_conf probe_conf;
struct probe_conf probe_conf = { .magic_num = DEFAULT_PROBE_MAGIC_NUM };
#define semantic_error(msg ...) pr_err("Semantic error :" msg)
@ -1679,6 +1679,14 @@ int parse_perf_probe_command(const char *cmd, struct perf_probe_event *pev)
if (ret < 0)
goto out;
/* Generate event name if needed */
if (!pev->event && pev->point.function && pev->point.line
&& !pev->point.lazy_line && !pev->point.offset) {
if (asprintf(&pev->event, "%s_L%d", pev->point.function,
pev->point.line) < 0)
return -ENOMEM;
}
/* Copy arguments and ensure return probe has no C argument */
pev->nargs = argc - 1;
pev->args = zalloc(sizeof(struct perf_probe_arg) * pev->nargs);
@ -2730,8 +2738,13 @@ static int probe_trace_event__set_name(struct probe_trace_event *tev,
if (tev->event == NULL || tev->group == NULL)
return -ENOMEM;
/* Add added event name to namelist */
strlist__add(namelist, event);
/*
* Add new event name to namelist if multiprobe event is NOT
* supported, since we have to use new event name for following
* probes in that case.
*/
if (!multiprobe_event_is_supported())
strlist__add(namelist, event);
return 0;
}

3
tools/perf/util/probe-event.h
View File

@ -16,10 +16,13 @@ struct probe_conf {
bool no_inlines;
bool cache;
int max_probes;
unsigned long magic_num;
};
extern struct probe_conf probe_conf;
extern bool probe_event_dry_run;
#define DEFAULT_PROBE_MAGIC_NUM 0xdeade12d /* u32: 3735937325 */
struct symbol;
/* kprobe-tracer and uprobe-tracer tracing point */

14
tools/perf/util/probe-file.c
View File

@ -1007,6 +1007,8 @@ enum ftrace_readme {
FTRACE_README_KRETPROBE_OFFSET,
FTRACE_README_UPROBE_REF_CTR,
FTRACE_README_USER_ACCESS,
FTRACE_README_MULTIPROBE_EVENT,
FTRACE_README_IMMEDIATE_VALUE,
FTRACE_README_END,
};
@ -1020,6 +1022,8 @@ static struct {
DEFINE_TYPE(FTRACE_README_KRETPROBE_OFFSET, "*place (kretprobe): *"),
DEFINE_TYPE(FTRACE_README_UPROBE_REF_CTR, "*ref_ctr_offset*"),
DEFINE_TYPE(FTRACE_README_USER_ACCESS, "*[u]<offset>*"),
DEFINE_TYPE(FTRACE_README_MULTIPROBE_EVENT, "*Create/append/*"),
DEFINE_TYPE(FTRACE_README_IMMEDIATE_VALUE, "*\\imm-value,*"),
};
static bool scan_ftrace_readme(enum ftrace_readme type)
@ -1085,3 +1089,13 @@ bool user_access_is_supported(void)
{
return scan_ftrace_readme(FTRACE_README_USER_ACCESS);
}
bool multiprobe_event_is_supported(void)
{
return scan_ftrace_readme(FTRACE_README_MULTIPROBE_EVENT);
}
bool immediate_value_is_supported(void)
{
return scan_ftrace_readme(FTRACE_README_IMMEDIATE_VALUE);
}

2
tools/perf/util/probe-file.h
View File

@ -71,6 +71,8 @@ bool probe_type_is_available(enum probe_type type);
bool kretprobe_offset_is_supported(void);
bool uprobe_ref_ctr_is_supported(void);
bool user_access_is_supported(void);
bool multiprobe_event_is_supported(void);
bool immediate_value_is_supported(void);
#else /* ! HAVE_LIBELF_SUPPORT */
static inline struct probe_cache *probe_cache__new(const char *tgt __maybe_unused, struct nsinfo *nsi __maybe_unused)
{

116
tools/perf/util/probe-finder.c
View File

@ -177,6 +177,17 @@ static int convert_variable_location(Dwarf_Die *vr_die, Dwarf_Addr addr,
if (dwarf_attr(vr_die, DW_AT_external, &attr) != NULL)
goto static_var;
/* Constant value */
if (dwarf_attr(vr_die, DW_AT_const_value, &attr) &&
immediate_value_is_supported()) {
Dwarf_Sword snum;
dwarf_formsdata(&attr, &snum);
ret = asprintf(&tvar->value, "\\%ld", (long)snum);
return ret < 0 ? -ENOMEM : 0;
}
/* TODO: handle more than 1 exprs */
if (dwarf_attr(vr_die, DW_AT_location, &attr) == NULL)
return -EINVAL; /* Broken DIE ? */
@ -525,6 +536,14 @@ next:
return 0;
}
static void print_var_not_found(const char *varname)
{
pr_err("Failed to find the location of the '%s' variable at this address.\n"
" Perhaps it has been optimized out.\n"
" Use -V with the --range option to show '%s' location range.\n",
varname, varname);
}
/* Show a variables in kprobe event format */
static int convert_variable(Dwarf_Die *vr_die, struct probe_finder *pf)
{
@ -536,11 +555,11 @@ static int convert_variable(Dwarf_Die *vr_die, struct probe_finder *pf)
ret = convert_variable_location(vr_die, pf->addr, pf->fb_ops,
&pf->sp_die, pf->machine, pf->tvar);
if (ret == -ENOENT && pf->skip_empty_arg)
/* This can be found in other place. skip it */
return 0;
if (ret == -ENOENT || ret == -EINVAL) {
pr_err("Failed to find the location of the '%s' variable at this address.\n"
" Perhaps it has been optimized out.\n"
" Use -V with the --range option to show '%s' location range.\n",
pf->pvar->var, pf->pvar->var);
print_var_not_found(pf->pvar->var);
} else if (ret == -ENOTSUP)
pr_err("Sorry, we don't support this variable location yet.\n");
else if (ret == 0 && pf->pvar->field) {
@ -587,6 +606,8 @@ static int find_variable(Dwarf_Die *sc_die, struct probe_finder *pf)
/* Search again in global variables */
if (!die_find_variable_at(&pf->cu_die, pf->pvar->var,
0, &vr_die)) {
if (pf->skip_empty_arg)
return 0;
pr_warning("Failed to find '%s' in this function.\n",
pf->pvar->var);
ret = -ENOENT;
@ -776,6 +797,39 @@ static Dwarf_Die *find_best_scope(struct probe_finder *pf, Dwarf_Die *die_mem)
return fsp.found ? die_mem : NULL;
}
static int verify_representive_line(struct probe_finder *pf, const char *fname,
int lineno, Dwarf_Addr addr)
{
const char *__fname, *__func = NULL;
Dwarf_Die die_mem;
int __lineno;
/* Verify line number and address by reverse search */
if (cu_find_lineinfo(&pf->cu_die, addr, &__fname, &__lineno) < 0)
return 0;
pr_debug2("Reversed line: %s:%d\n", __fname, __lineno);
if (strcmp(fname, __fname) || lineno == __lineno)
return 0;
pr_warning("This line is sharing the addrees with other lines.\n");
if (pf->pev->point.function) {
/* Find best match function name and lines */
pf->addr = addr;
if (find_best_scope(pf, &die_mem)
&& die_match_name(&die_mem, pf->pev->point.function)
&& dwarf_decl_line(&die_mem, &lineno) == 0) {
__func = dwarf_diename(&die_mem);
__lineno -= lineno;
}
}
pr_warning("Please try to probe at %s:%d instead.\n",
__func ? : __fname, __lineno);
return -ENOENT;
}
static int probe_point_line_walker(const char *fname, int lineno,
Dwarf_Addr addr, void *data)
{
@ -786,6 +840,9 @@ static int probe_point_line_walker(const char *fname, int lineno,
if (lineno != pf->lno || strtailcmp(fname, pf->fname) != 0)
return 0;
if (verify_representive_line(pf, fname, lineno, addr))
return -ENOENT;
pf->addr = addr;
sc_die = find_best_scope(pf, &die_mem);
if (!sc_die) {
@ -1337,6 +1394,44 @@ end:
return ret;
}
static int fill_empty_trace_arg(struct perf_probe_event *pev,
struct probe_trace_event *tevs, int ntevs)
{
char **valp;
char *type;
int i, j, ret;
for (i = 0; i < pev->nargs; i++) {
type = NULL;
for (j = 0; j < ntevs; j++) {
if (tevs[j].args[i].value) {
type = tevs[j].args[i].type;
break;
}
}
if (j == ntevs) {
print_var_not_found(pev->args[i].var);
return -ENOENT;
}
for (j = 0; j < ntevs; j++) {
valp = &tevs[j].args[i].value;
if (*valp)
continue;
ret = asprintf(valp, "\\%lx", probe_conf.magic_num);
if (ret < 0)
return -ENOMEM;
/* Note that type can be NULL */
if (type) {
tevs[j].args[i].type = strdup(type);
if (!tevs[j].args[i].type)
return -ENOMEM;
}
}
}
return 0;
}
/* Find probe_trace_events specified by perf_probe_event from debuginfo */
int debuginfo__find_trace_events(struct debuginfo *dbg,
struct perf_probe_event *pev,
@ -1355,7 +1450,13 @@ int debuginfo__find_trace_events(struct debuginfo *dbg,
tf.tevs = *tevs;
tf.ntevs = 0;
if (pev->nargs != 0 && immediate_value_is_supported())
tf.pf.skip_empty_arg = true;
ret = debuginfo__find_probes(dbg, &tf.pf);
if (ret >= 0 && tf.pf.skip_empty_arg)
ret = fill_empty_trace_arg(pev, tf.tevs, tf.ntevs);
if (ret < 0) {
for (i = 0; i < tf.ntevs; i++)
clear_probe_trace_event(&tf.tevs[i]);
@ -1698,12 +1799,19 @@ static int line_range_walk_cb(const char *fname, int lineno,
void *data)
{
struct line_finder *lf = data;
const char *__fname;
int __lineno;
int err;
if ((strtailcmp(fname, lf->fname) != 0) ||
(lf->lno_s > lineno || lf->lno_e < lineno))
return 0;
/* Make sure this line can be reversable */
if (cu_find_lineinfo(&lf->cu_die, addr, &__fname, &__lineno) > 0
&& (lineno != __lineno || strcmp(fname, __fname)))
return 0;
err = line_range_add_line(fname, lineno, lf->lr);
if (err < 0 && err != -EEXIST)
return err;

1
tools/perf/util/probe-finder.h
View File

@ -87,6 +87,7 @@ struct probe_finder {
unsigned int machine; /* Target machine arch */
struct perf_probe_arg *pvar; /* Current target variable */
struct probe_trace_arg *tvar; /* Current result variable */
bool skip_empty_arg; /* Skip non-exist args */
};
struct trace_event_finder {

84
tools/perf/util/symbol.c
View File

@ -1530,7 +1530,7 @@ static bool dso__is_compatible_symtab_type(struct dso *dso, bool kmod,
case DSO_BINARY_TYPE__SYSTEM_PATH_KMODULE_COMP:
/*
* kernel modules know their symtab type - it's set when
* creating a module dso in machine__findnew_module_map().
* creating a module dso in machine__addnew_module_map().
*/
return kmod && dso->symtab_type == type;
@ -1760,28 +1760,82 @@ out:
return ret;
}
static int map__strcmp(const void *a, const void *b)
{
const struct map *ma = *(const struct map **)a, *mb = *(const struct map **)b;
return strcmp(ma->dso->short_name, mb->dso->short_name);
}
static int map__strcmp_name(const void *name, const void *b)
{
const struct map *map = *(const struct map **)b;
return strcmp(name, map->dso->short_name);
}
void __map_groups__sort_by_name(struct map_groups *mg)
{
qsort(mg->maps_by_name, mg->nr_maps, sizeof(struct map *), map__strcmp);
}
static int map__groups__sort_by_name_from_rbtree(struct map_groups *mg)
{
struct map *map;
struct map **maps_by_name = realloc(mg->maps_by_name, mg->nr_maps * sizeof(map));
int i = 0;
if (maps_by_name == NULL)
return -1;
mg->maps_by_name = maps_by_name;
mg->nr_maps_allocated = mg->nr_maps;
maps__for_each_entry(&mg->maps, map)
maps_by_name[i++] = map;
__map_groups__sort_by_name(mg);
return 0;
}
static struct map *__map_groups__find_by_name(struct map_groups *mg, const char *name)
{
struct map **mapp;
if (mg->maps_by_name == NULL &&
map__groups__sort_by_name_from_rbtree(mg))
return NULL;
mapp = bsearch(name, mg->maps_by_name, mg->nr_maps, sizeof(*mapp), map__strcmp_name);
if (mapp)
return *mapp;
return NULL;
}
struct map *map_groups__find_by_name(struct map_groups *mg, const char *name)
{
struct maps *maps = &mg->maps;
struct map *map;
struct rb_node *node;
down_read(&maps->lock);
for (node = maps->names.rb_node; node; ) {
int rc;
map = rb_entry(node, struct map, rb_node_name);
rc = strcmp(map->dso->short_name, name);
if (rc < 0)
node = node->rb_left;
else if (rc > 0)
node = node->rb_right;
else
goto out_unlock;
if (mg->last_search_by_name && strcmp(mg->last_search_by_name->dso->short_name, name) == 0) {
map = mg->last_search_by_name;
goto out_unlock;
}
/*
* If we have mg->maps_by_name, then the name isn't in the rbtree,
* as mg->maps_by_name mirrors the rbtree when lookups by name are
* made.
*/
map = __map_groups__find_by_name(mg, name);
if (map || mg->maps_by_name != NULL)
goto out_unlock;
/* Fallback to traversing the rbtree... */
maps__for_each_entry(maps, map)
if (strcmp(map->dso->short_name, name) == 0) {
mg->last_search_by_name = map;
goto out_unlock;
}
map = NULL;