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wifi: rtw89: 8852c: Update bandedge parameters for better performance

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TSSI configures bandedge to TX proper waveform, these new bandedge
parameters improve the accuracy of transmit power compensation.
This helps to avoid throughput degradation.

Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230830092849.153251-2-pkshih@realtek.com
This commit is contained in:
Kuan-Chung Chen 2023-08-30 17:28:48 +08:00 committed by Kalle Valo
parent a763e92c78
commit 8f969ba1de
3 changed files with 15 additions and 3 deletions
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4
drivers/net/wireless/realtek/rtw89/reg.h
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@ -4619,6 +4619,8 @@
#define R_TXGAIN_SCALE 0x58F0 #define R_TXGAIN_SCALE 0x58F0
#define B_TXGAIN_SCALE_EN BIT(19) #define B_TXGAIN_SCALE_EN BIT(19)
#define B_TXGAIN_SCALE_OFT GENMASK(31, 24) #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
#define R_P0_DAC_COMP_POST_DPD_EN 0x58F8
#define B_P0_DAC_COMP_POST_DPD_EN BIT(31)
#define R_P0_TSSI_BASE 0x5C00 #define R_P0_TSSI_BASE 0x5C00
#define R_S0_DACKI 0x5E00 #define R_S0_DACKI 0x5E00
#define B_S0_DACKI_AR GENMASK(31, 28) #define B_S0_DACKI_AR GENMASK(31, 28)
@ -4675,6 +4677,8 @@
#define B_P1_TSSI_MV_MIX GENMASK(19, 11) #define B_P1_TSSI_MV_MIX GENMASK(19, 11)
#define B_P1_TSSI_MV_AVG GENMASK(13, 11) #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
#define B_P1_TSSI_MV_CLR BIT(14) #define B_P1_TSSI_MV_CLR BIT(14)
#define R_P1_DAC_COMP_POST_DPD_EN 0x78F8
#define B_P1_DAC_COMP_POST_DPD_EN BIT(31)
#define R_TSSI_THOF 0x7C00 #define R_TSSI_THOF 0x7C00
#define R_S1_DACKI 0x7E00 #define R_S1_DACKI 0x7E00
#define B_S1_DACKI_AR GENMASK(31, 28) #define B_S1_DACKI_AR GENMASK(31, 28)

5
drivers/net/wireless/realtek/rtw89/rtw8852c.c
View File

@ -1975,6 +1975,11 @@ static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
(enum rtw89_mac_idx)phy_idx, (enum rtw89_mac_idx)phy_idx,
tx_shape_ofdm); tx_shape_ofdm);
rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN,
B_P0_DAC_COMP_POST_DPD_EN);
rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN,
B_P1_DAC_COMP_POST_DPD_EN);
} }
static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,

9
drivers/net/wireless/realtek/rtw89/rtw8852c_table.c
View File

@ -56452,9 +56452,12 @@ const struct rtw89_txpwr_track_cfg rtw89_8852c_trk_cfg = {
const struct rtw89_phy_tssi_dbw_table rtw89_8852c_tssi_dbw_table = { const struct rtw89_phy_tssi_dbw_table rtw89_8852c_tssi_dbw_table = {
.data[RTW89_TSSI_BANDEDGE_FLAT] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, .data[RTW89_TSSI_BANDEDGE_FLAT] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
.data[RTW89_TSSI_BANDEDGE_LOW] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, .data[RTW89_TSSI_BANDEDGE_LOW] = {0x1d, 0x1d, 0x1d, 0x2f, 0xf, 0xf, 0x2f, 0x38,
.data[RTW89_TSSI_BANDEDGE_MID] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0x28, 0x18, 0x8, 0x8, 0x18, 0x28, 0x38},
.data[RTW89_TSSI_BANDEDGE_HIGH] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, .data[RTW89_TSSI_BANDEDGE_MID] = {0x24, 0x24, 0x24, 0x3b, 0x13, 0x13, 0x3b, 0x46,
0x32, 0x1e, 0xa, 0xa, 0x1e, 0x32, 0x46},
.data[RTW89_TSSI_BANDEDGE_HIGH] = {0x2a, 0x2a, 0x2a, 0x46, 0x17, 0x17, 0x46, 0x53,
0x3b, 0x24, 0xc, 0xc, 0x24, 0x3b, 0x53},
}; };
const struct rtw89_rfe_parms rtw89_8852c_dflt_parms = { const struct rtw89_rfe_parms rtw89_8852c_dflt_parms = {