ALSA: dice: Support for non SYT-Match sampling clock source mode
This commit allows this driver to handle devices with non SYT-Match sampling clock source. When sampling clock source is SYT-Match mode, devices handle 'presentation timestamp' in received packets and generates sampling clock according to the information. In this case, driver is synchronization master and must transfer correct value in SYT field of each packets in outgoing stream, then the outgoing stream is a master stream. On the other hand, non SYT-Match mode, devices do this. So drivers must pick up the value in SYT field of incoming packets and use the value for outgoing stream. Currently firewire-lib module achieve this work. Furthermore, without SYT-Match and internal clock source, the sampling rate should be fixed for the other devices connected to the handled device. This commit add a restriction of sampling rate at this situation. With these implementations, this driver has no need to set clock source. This commit remove set function. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -140,6 +140,8 @@ end:
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static int pcm_open(struct snd_pcm_substream *substream)
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{
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struct snd_dice *dice = substream->private_data;
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unsigned int source, rate;
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bool internal;
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int err;
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err = snd_dice_stream_lock_try(dice);
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@ -149,6 +151,39 @@ static int pcm_open(struct snd_pcm_substream *substream)
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err = init_hw_info(dice, substream);
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if (err < 0)
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goto err_locked;
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err = snd_dice_transaction_get_clock_source(dice, &source);
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if (err < 0)
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goto err_locked;
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switch (source) {
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case CLOCK_SOURCE_AES1:
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case CLOCK_SOURCE_AES2:
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case CLOCK_SOURCE_AES3:
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case CLOCK_SOURCE_AES4:
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case CLOCK_SOURCE_AES_ANY:
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case CLOCK_SOURCE_ADAT:
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case CLOCK_SOURCE_TDIF:
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case CLOCK_SOURCE_WC:
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internal = false;
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break;
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default:
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internal = true;
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break;
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}
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/*
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* When source of clock is not internal, available sampling rate is
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* limited at current sampling rate.
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*/
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if (!internal) {
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err = snd_dice_transaction_get_rate(dice, &rate);
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if (err < 0)
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goto err_locked;
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substream->runtime->hw.rate_min = rate;
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substream->runtime->hw.rate_max = rate;
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}
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snd_pcm_set_sync(substream);
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end:
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return err;
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err_locked:
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@ -161,9 +161,29 @@ end:
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static int get_sync_mode(struct snd_dice *dice, enum cip_flags *sync_mode)
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{
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/* Currently, clock source is fixed at SYT-Match mode. */
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*sync_mode = 0;
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return 0;
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u32 source;
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int err;
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err = snd_dice_transaction_get_clock_source(dice, &source);
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if (err < 0)
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goto end;
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switch (source) {
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/* So-called 'SYT Match' modes, sync_to_syt value of packets received */
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case CLOCK_SOURCE_ARX4: /* in 4th stream */
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case CLOCK_SOURCE_ARX3: /* in 3rd stream */
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case CLOCK_SOURCE_ARX2: /* in 2nd stream */
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err = -ENOSYS;
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break;
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case CLOCK_SOURCE_ARX1: /* in 1st stream, which this driver uses */
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*sync_mode = 0;
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break;
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default:
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*sync_mode = CIP_SYNC_TO_DEVICE;
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break;
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}
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end:
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return err;
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}
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int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate)
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@ -310,15 +330,6 @@ int snd_dice_stream_init_duplex(struct snd_dice *dice)
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goto end;
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err = init_stream(dice, &dice->rx_stream);
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if (err < 0)
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goto end;
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/* Currently, clock source is fixed at SYT-Match mode. */
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err = snd_dice_transaction_set_clock_source(dice, CLOCK_SOURCE_ARX1);
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if (err < 0) {
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destroy_stream(dice, &dice->rx_stream);
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destroy_stream(dice, &dice->tx_stream);
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}
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end:
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return err;
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}
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@ -137,11 +137,6 @@ int snd_dice_transaction_get_clock_source(struct snd_dice *dice,
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return err;
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}
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int snd_dice_transaction_set_clock_source(struct snd_dice *dice,
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unsigned int source)
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{
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return set_clock_info(dice, UINT_MAX, source);
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}
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int snd_dice_transaction_get_rate(struct snd_dice *dice, unsigned int *rate)
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{
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@ -152,8 +152,6 @@ static inline int snd_dice_transaction_read_sync(struct snd_dice *dice,
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buf, len);
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}
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int snd_dice_transaction_set_clock_source(struct snd_dice *dice,
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unsigned int source);
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int snd_dice_transaction_get_clock_source(struct snd_dice *dice,
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unsigned int *source);
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int snd_dice_transaction_set_rate(struct snd_dice *dice, unsigned int rate);
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