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clk: stm32mp1: remove intermediate pll clocks

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This patch is to prepare STM32MP1 clocks in trusted mode.
Integrate the mux clock into pll clock will facilitate to have a more
coherent clock tree in no trusted / trusted mode.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20210617051814.12018-4-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Gabriel Fernandez 2021-06-17 07:18:06 +02:00 committed by Stephen Boyd
parent 152efe5662
commit 9008fddee4
1 changed files with 42 additions and 23 deletions
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65
drivers/clk/clk-stm32mp1.c
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@ -731,6 +731,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
struct clk_mux mux;
};
#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@ -745,6 +746,8 @@ struct stm32_pll_obj {
#define FRAC_MASK 0x1FFF
#define FRAC_SHIFT 3
#define FRACLE BIT(16)
#define PLL_MUX_SHIFT 0
#define PLL_MUX_MASK 3
static int __pll_is_enabled(struct clk_hw *hw)
{
@ -856,16 +859,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
}
static u8 pll_get_parent(struct clk_hw *hw)
{
struct stm32_pll_obj *clk_elem = to_pll(hw);
struct clk_hw *mux_hw = &clk_elem->mux.hw;
__clk_hw_set_clk(mux_hw, hw);
return clk_mux_ops.get_parent(mux_hw);
}
static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable = pll_disable,
.recalc_rate = pll_recalc_rate,
.is_enabled = pll_is_enabled,
.get_parent = pll_get_parent,
};
static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
const char *parent_name,
const char * const *parent_names,
int num_parents,
void __iomem *reg,
void __iomem *mux_reg,
unsigned long flags,
spinlock_t *lock)
{
@ -881,8 +897,15 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
init.name = name;
init.ops = &pll_ops;
init.flags = flags;
init.parent_names = &parent_name;
init.num_parents = 1;
init.parent_names = parent_names;
init.num_parents = num_parents;
element->mux.lock = lock;
element->mux.reg = mux_reg;
element->mux.shift = PLL_MUX_SHIFT;
element->mux.mask = PLL_MUX_MASK;
element->mux.flags = CLK_MUX_READ_ONLY;
element->mux.reg = mux_reg;
element->hw.init = &init;
element->reg = reg;
@ -1074,6 +1097,7 @@ static const struct clk_ops rtc_div_clk_ops = {
struct stm32_pll_cfg {
u32 offset;
u32 muxoff;
};
static struct clk_hw *_clk_register_pll(struct device *dev,
@ -1083,8 +1107,11 @@ static struct clk_hw *_clk_register_pll(struct device *dev,
{
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
return clk_register_pll(dev, cfg->name, cfg->parent_name,
base + stm_pll_cfg->offset, cfg->flags, lock);
return clk_register_pll(dev, cfg->name, cfg->parent_names,
cfg->num_parents,
base + stm_pll_cfg->offset,
base + stm_pll_cfg->muxoff,
cfg->flags, lock);
}
struct stm32_cktim_cfg {
@ -1194,14 +1221,16 @@ _clk_stm32_register_composite(struct device *dev,
.func = _clk_hw_register_mux,\
}
#define PLL(_id, _name, _parent, _flags, _offset)\
#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
{\
.id = _id,\
.name = _name,\
.parent_name = _parent,\
.flags = _flags,\
.parent_names = _parents,\
.num_parents = ARRAY_SIZE(_parents),\
.flags = CLK_IGNORE_UNUSED | (_flags),\
.cfg = &(struct stm32_pll_cfg) {\
.offset = _offset,\
.offset = _offset_p,\
.muxoff = _offset_mux,\
},\
.func = _clk_register_pll,\
}
@ -1717,21 +1746,11 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
/* ref clock pll */
MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
0, 2, CLK_MUX_READ_ONLY),
MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
0, 2, CLK_MUX_READ_ONLY),
MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
0, 2, CLK_MUX_READ_ONLY),
/* PLLs */
PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
/* ODF */
COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,