drm/fourcc: Introduce format modifier for DG2 clear color
DG2 clear color render compression uses Tile4 layout. Therefore, we need to define a new format modifier for uAPI to support clear color rendering. v2: Display version is fixed. [Imre] KDoc is enhanced for cc modifier. [Nanley & Lionel] v3: Split out the modifier addition to a separate patch. Clarify the modifier layout description. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Mika Kahola <mika.kahola@intel.com> cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220411143405.1073845-4-imre.deak@intel.com
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@ -605,6 +605,20 @@ extern "C" {
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
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/*
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* Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
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*
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* The main surface is Tile 4 and at plane index 0. The CCS data is stored
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* outside of the GEM object in a reserved memory area dedicated for the
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* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
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* main surface pitch is required to be a multiple of four Tile 4 widths. The
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* clear color is stored at plane index 1 and the pitch should be ignored. The
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* format of the 256 bits of clear color data matches the one used for the
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* I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
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* for details.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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