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drm/armada: move write to dma_ctrl0 to armada_drm_crtc_plane_disable()

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Move the write to clear the DMA enable bit, and augment it with clearing
the graphics enable bit for the primary plane.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2015-07-15 18:11:25 +01:00
parent 5832680358
commit 9099ea19ca
2 changed files with 10 additions and 3 deletions
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12
drivers/gpu/drm/armada/armada_crtc.c
View File

@ -703,7 +703,7 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
struct drm_plane *plane) struct drm_plane *plane)
{ {
u32 sram_para1; u32 sram_para1, dma_ctrl0_mask;
/* /*
* Drop our reference on any framebuffer attached to this plane. * Drop our reference on any framebuffer attached to this plane.
@ -719,9 +719,17 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
/* Power down most RAMs and FIFOs if this is the primary plane */ /* Power down most RAMs and FIFOs if this is the primary plane */
if (plane->type == DRM_PLANE_TYPE_PRIMARY) if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
CFG_PDWN32x32 | CFG_PDWN64x66; CFG_PDWN32x32 | CFG_PDWN64x66;
dma_ctrl0_mask = CFG_GRA_ENA;
} else {
dma_ctrl0_mask = CFG_DMA_ENA;
}
spin_lock_irq(&dcrtc->irq_lock);
armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
spin_unlock_irq(&dcrtc->irq_lock);
armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
} }

1
drivers/gpu/drm/armada/armada_overlay.c
View File

@ -275,7 +275,6 @@ static int armada_ovl_plane_disable(struct drm_plane *plane)
spin_lock_irq(&dcrtc->irq_lock); spin_lock_irq(&dcrtc->irq_lock);
armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update); armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update);
armada_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
dplane->ctrl0 = 0; dplane->ctrl0 = 0;
spin_unlock_irq(&dcrtc->irq_lock); spin_unlock_irq(&dcrtc->irq_lock);