ice: dpll: implement phase related callbacks
Implement new callback ops related to measurement and adjustment of signal phase for pin-dpll in ice driver. Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arkadiusz Kubalewski
David S. Miller
parent
d7fbc0b7e8
commit
90e1c90750
@ -878,6 +878,199 @@ ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
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return 0;
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}
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/**
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* ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @phase_adjust: on success holds pin phase_adjust value
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* @extack: error reporting
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*
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* Dpll subsystem callback. Handler for getting phase adjust value of a pin.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s32 *phase_adjust,
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struct netlink_ext_ack *extack)
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{
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struct ice_dpll_pin *p = pin_priv;
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struct ice_pf *pf = p->pf;
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mutex_lock(&pf->dplls.lock);
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*phase_adjust = p->phase_adjust;
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mutex_unlock(&pf->dplls.lock);
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return 0;
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}
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/**
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* ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @phase_adjust: phase_adjust to be set
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* @extack: error reporting
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* @type: type of a pin
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*
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* Helper for dpll subsystem callback. Handler for setting phase adjust value
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* of a pin.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s32 phase_adjust,
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struct netlink_ext_ack *extack,
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enum ice_dpll_pin_type type)
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{
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struct ice_dpll_pin *p = pin_priv;
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struct ice_dpll *d = dpll_priv;
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struct ice_pf *pf = d->pf;
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u8 flag, flags_en = 0;
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int ret;
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mutex_lock(&pf->dplls.lock);
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switch (type) {
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case ICE_DPLL_PIN_TYPE_INPUT:
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flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
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if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
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flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
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if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
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flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
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ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
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0, phase_adjust);
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break;
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case ICE_DPLL_PIN_TYPE_OUTPUT:
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flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
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if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
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flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
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if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
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flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
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ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
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phase_adjust);
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break;
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default:
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ret = -EINVAL;
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}
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if (!ret)
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p->phase_adjust = phase_adjust;
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mutex_unlock(&pf->dplls.lock);
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if (ret)
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NL_SET_ERR_MSG_FMT(extack,
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"err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
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ret,
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ice_aq_str(pf->hw.adminq.sq_last_status),
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phase_adjust, p->idx, d->dpll_idx);
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return ret;
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}
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/**
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* ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @phase_adjust: phase_adjust to be set
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* @extack: error reporting
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*
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* Dpll subsystem callback. Wraps a handler for setting phase adjust on input
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* pin.
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*
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* Context: Calls a function which acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s32 phase_adjust,
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struct netlink_ext_ack *extack)
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{
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return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
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phase_adjust, extack,
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ICE_DPLL_PIN_TYPE_INPUT);
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}
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/**
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* ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @phase_adjust: phase_adjust to be set
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* @extack: error reporting
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*
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* Dpll subsystem callback. Wraps a handler for setting phase adjust on output
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* pin.
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*
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* Context: Calls a function which acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s32 phase_adjust,
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struct netlink_ext_ack *extack)
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{
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return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
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phase_adjust, extack,
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ICE_DPLL_PIN_TYPE_OUTPUT);
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}
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#define ICE_DPLL_PHASE_OFFSET_DIVIDER 100
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#define ICE_DPLL_PHASE_OFFSET_FACTOR \
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(DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
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/**
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* ice_dpll_phase_offset_get - callback for get dpll phase shift value
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @phase_offset: on success holds pin phase_offset value
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* @extack: error reporting
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*
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* Dpll subsystem callback. Handler for getting phase shift value between
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* dpll's input and output.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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s64 *phase_offset, struct netlink_ext_ack *extack)
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{
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struct ice_dpll *d = dpll_priv;
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struct ice_pf *pf = d->pf;
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mutex_lock(&pf->dplls.lock);
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if (d->active_input == pin)
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*phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
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else
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*phase_offset = 0;
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mutex_unlock(&pf->dplls.lock);
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return 0;
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}
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/**
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* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
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* @pin: pointer to a pin
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@ -993,6 +1186,9 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
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.prio_get = ice_dpll_input_prio_get,
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.prio_set = ice_dpll_input_prio_set,
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.direction_get = ice_dpll_input_direction,
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.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
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.phase_adjust_set = ice_dpll_input_phase_adjust_set,
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.phase_offset_get = ice_dpll_phase_offset_get,
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};
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static const struct dpll_pin_ops ice_dpll_output_ops = {
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@ -1001,6 +1197,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
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.state_on_dpll_get = ice_dpll_output_state_get,
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.state_on_dpll_set = ice_dpll_output_state_set,
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.direction_get = ice_dpll_output_direction,
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.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
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.phase_adjust_set = ice_dpll_output_phase_adjust_set,
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};
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static const struct dpll_device_ops ice_dpll_ops = {
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@ -1031,6 +1229,8 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
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*/
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static void ice_dpll_notify_changes(struct ice_dpll *d)
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{
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bool pin_notified = false;
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if (d->prev_dpll_state != d->dpll_state) {
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d->prev_dpll_state = d->dpll_state;
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dpll_device_change_ntf(d->dpll);
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@ -1039,7 +1239,14 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
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if (d->prev_input)
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dpll_pin_change_ntf(d->prev_input);
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d->prev_input = d->active_input;
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if (d->active_input)
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if (d->active_input) {
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dpll_pin_change_ntf(d->active_input);
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pin_notified = true;
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}
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}
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if (d->prev_phase_offset != d->phase_offset) {
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d->prev_phase_offset = d->phase_offset;
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if (!pin_notified && d->active_input)
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dpll_pin_change_ntf(d->active_input);
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}
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}
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@ -1065,7 +1272,7 @@ ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
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ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
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&d->input_idx, &d->ref_state, &d->eec_mode,
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&d->phase_shift, &d->dpll_state);
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&d->phase_offset, &d->dpll_state);
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dev_dbg(ice_pf_to_dev(pf),
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"update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
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@ -1656,6 +1863,15 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
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return ret;
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pins[i].prop.capabilities |=
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DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
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pins[i].prop.phase_range.min =
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pf->dplls.input_phase_adj_max;
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pins[i].prop.phase_range.max =
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-pf->dplls.input_phase_adj_max;
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} else {
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pins[i].prop.phase_range.min =
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pf->dplls.output_phase_adj_max;
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pins[i].prop.phase_range.max =
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-pf->dplls.output_phase_adj_max;
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}
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pins[i].prop.capabilities |=
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DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
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@ -19,6 +19,7 @@
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* @state: state of a pin
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* @prop: pin properties
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* @freq: current frequency of a pin
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* @phase_adjust: current phase adjust value
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*/
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struct ice_dpll_pin {
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struct dpll_pin *pin;
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@ -30,6 +31,7 @@ struct ice_dpll_pin {
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u8 state[ICE_DPLL_RCLK_NUM_MAX];
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struct dpll_pin_properties prop;
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u32 freq;
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s32 phase_adjust;
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};
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/** ice_dpll - store info required for DPLL control
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@ -40,7 +42,8 @@ struct ice_dpll_pin {
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* @prev_input_idx: previously selected input index
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* @ref_state: state of dpll reference signals
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* @eec_mode: eec_mode dpll is configured for
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* @phase_shift: phase shift delay of a dpll
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* @phase_offset: phase offset of active pin vs dpll signal
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* @prev_phase_offset: previous phase offset of active pin vs dpll signal
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* @input_prio: priorities of each input
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* @dpll_state: current dpll sync state
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* @prev_dpll_state: last dpll sync state
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@ -55,7 +58,8 @@ struct ice_dpll {
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u8 prev_input_idx;
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u8 ref_state;
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u8 eec_mode;
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s64 phase_shift;
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s64 phase_offset;
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s64 prev_phase_offset;
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u8 *input_prio;
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enum dpll_lock_status dpll_state;
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enum dpll_lock_status prev_dpll_state;
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@ -78,6 +82,8 @@ struct ice_dpll {
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* @cgu_state_acq_err_num: number of errors returned during periodic work
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* @base_rclk_idx: idx of first pin used for clock revocery pins
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* @clock_id: clock_id of dplls
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* @input_phase_adj_max: max phase adjust value for an input pins
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* @output_phase_adj_max: max phase adjust value for an output pins
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*/
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struct ice_dplls {
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struct kthread_worker *kworker;
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