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arm64: dts: rockchip: use BCLK to GPIO switch on rk3399

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We discoverd that the state of BCLK on, LRCLK off and SD_MODE on
may cause the speaker melting issue. Removing LRCLK while BCLK
is present can cause unexpected output behavior including a large
DC output voltage as described in the Max98357a datasheet.

In order to:
  1. prevent BCLK from turning on by other component.
  2. keep BCLK and LRCLK being present at the same time

This patch adjusts the device tree to allow BCLK to switch
to GPIO func before LRCLK output, and switch back during
LRCLK is output.

Signed-off-by: Judy Hsiao <judyhsiao@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Link: https://lore.kernel.org/r/20220708080726.4170711-1-judyhsiao@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Judy Hsiao 2022-07-08 08:07:26 +00:00 committed by Heiko Stuebner
parent 03d86fb5a5
commit 91419ae042
2 changed files with 34 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
View File

@ -768,6 +768,16 @@ camera: &i2c7 {
<4 RK_PA0 1 &pcfg_pull_none_6ma>;
};
&i2s0_8ch_bus_bclk_off {
rockchip,pins =
<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>,
<3 RK_PD1 1 &pcfg_pull_none_6ma>,
<3 RK_PD2 1 &pcfg_pull_none_6ma>,
<3 RK_PD3 1 &pcfg_pull_none_6ma>,
<3 RK_PD7 1 &pcfg_pull_none_6ma>,
<4 RK_PA0 1 &pcfg_pull_none_6ma>;
};
/* there is no external pull up, so need to set this pin pull up */
&sdmmc_cd_pin {
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;

25
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -1664,8 +1664,9 @@
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-names = "bclk_on", "bclk_off";
pinctrl-0 = <&i2s0_8ch_bus>;
pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
#sound-dai-cells = <0>;
status = "disabled";
@ -2409,6 +2410,19 @@
<3 RK_PD7 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none>;
};
i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
rockchip,pins =
<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PD1 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD4 1 &pcfg_pull_none>,
<3 RK_PD5 1 &pcfg_pull_none>,
<3 RK_PD6 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none>;
};
};
i2s1 {
@ -2420,6 +2434,15 @@
<4 RK_PA6 1 &pcfg_pull_none>,
<4 RK_PA7 1 &pcfg_pull_none>;
};
i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
rockchip,pins =
<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
<4 RK_PA4 1 &pcfg_pull_none>,
<4 RK_PA5 1 &pcfg_pull_none>,
<4 RK_PA6 1 &pcfg_pull_none>,
<4 RK_PA7 1 &pcfg_pull_none>;
};
};
sdio0 {