drm/amd/pm: enable gfx ulv feature control for SMU 13.0.0
Fulfill the interface for gfx ulv control. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -278,5 +278,8 @@ int smu_v13_0_run_btc(struct smu_context *smu);
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int smu_v13_0_deep_sleep_control(struct smu_context *smu,
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bool enablement);
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int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
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bool enablement);
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#endif
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#endif
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@ -2184,3 +2184,14 @@ int smu_v13_0_deep_sleep_control(struct smu_context *smu,
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return ret;
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}
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int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
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bool enablement)
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{
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int ret = 0;
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
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return ret;
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}
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@ -149,6 +149,7 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
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[SMU_FEATURE_DS_VCN_BIT] = {1, FEATURE_DS_VCN_BIT},
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[SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
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[SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
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[SMU_FEATURE_GFX_ULV_BIT] = {1, FEATURE_GFX_ULV_BIT},
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};
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static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
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@ -1580,6 +1581,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
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.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
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.set_tool_table_location = smu_v13_0_set_tool_table_location,
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.deep_sleep_control = smu_v13_0_deep_sleep_control,
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.gfx_ulv_control = smu_v13_0_gfx_ulv_control,
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};
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void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
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