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- Fix confusing output from /sys/kernel/debug/ras/daemon_active

Browse Source 
- Add another MCE severity error case to the Intel error severity
 table to promote UC and AR errors to panic severity and remove the
 corresponding code condition doing that.
 
 - Make sure the thresholding and deferred error interrupts on AMD SMCA
 systems clear the all registers reporting an error so that there are no
 multiple errors logged for the same event
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Merge tag 'ras_core_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 RAS updates from Borislav Petkov:

 - Fix confusing output from /sys/kernel/debug/ras/daemon_active

 - Add another MCE severity error case to the Intel error severity table
   to promote UC and AR errors to panic severity and remove the
   corresponding code condition doing that.

 - Make sure the thresholding and deferred error interrupts on AMD SMCA
   systems clear the all registers reporting an error so that there are
   no multiple errors logged for the same event

* tag 'ras_core_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  RAS: Fix return value from show_trace()
  x86/mce: Use severity table to handle uncorrected errors in kernel
  x86/MCE/AMD: Clear DFR errors found in THR handler
This commit is contained in:
Linus Torvalds 2022-12-12 14:51:56 -08:00
commit 9196a0ba9f
3 changed files with 26 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
arch/x86/kernel/cpu/mce/amd.c
View File

@ -788,6 +788,24 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
return status & MCI_STATUS_DEFERRED;
}
static bool _log_error_deferred(unsigned int bank, u32 misc)
{
if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
mca_msr_reg(bank, MCA_ADDR), misc))
return false;
/*
* Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers.
* Return true here to avoid accessing these registers.
*/
if (!mce_flags.smca)
return true;
/* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */
wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
return true;
}
/*
* We have three scenarios for checking for Deferred errors:
*
@ -799,20 +817,9 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
*/
static void log_error_deferred(unsigned int bank)
{
bool defrd;
defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
mca_msr_reg(bank, MCA_ADDR), 0);
if (!mce_flags.smca)
if (_log_error_deferred(bank, 0))
return;
/* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
if (defrd) {
wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
return;
}
/*
* Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
* for a valid error.
@ -832,7 +839,7 @@ static void amd_deferred_error_interrupt(void)
static void log_error_thresholding(unsigned int bank, u64 misc)
{
_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc);
_log_error_deferred(bank, misc);
}
static void log_and_reset_block(struct threshold_block *block)

8
arch/x86/kernel/cpu/mce/severity.c
View File

@ -202,6 +202,11 @@ static struct severity {
PANIC, "Overflowed uncorrected",
BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
),
MCESEV(
PANIC, "Uncorrected in kernel",
BITSET(MCI_STATUS_UC),
KERNEL
),
MCESEV(
UC, "Uncorrected",
BITSET(MCI_STATUS_UC)
@ -391,9 +396,6 @@ static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char
*msg = s->msg;
s->covered = 1;
if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL)
return MCE_PANIC_SEVERITY;
return s->sev;
}
}

2
drivers/ras/debugfs.c
View File

@ -15,7 +15,7 @@ EXPORT_SYMBOL_GPL(ras_userspace_consumers);
static int trace_show(struct seq_file *m, void *v)
{
return atomic_read(&trace_count);
return 0;
}
static int trace_open(struct inode *inode, struct file *file)