arm64: dts: ti: k3-am642-evm: Add boot phase tags marking
[ Upstream commit 33830e077797ce4d7317b83a145f03bfde06ad4c ] bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for AM642-evm boot devices. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230911172902.1057417-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Stable-dep-of: 379c7752bbd0 ("arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC") Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -35,6 +35,7 @@
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};
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memory@80000000 {
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bootph-all;
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device_type = "memory";
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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@ -108,6 +109,7 @@
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evm_12v0: regulator-0 {
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/* main DC jack */
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bootph-all;
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compatible = "regulator-fixed";
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regulator-name = "evm_12v0";
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regulator-min-microvolt = <12000000>;
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@ -129,6 +131,7 @@
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vsys_3v3: regulator-2 {
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/* output of LM5140 */
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bootph-all;
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compatible = "regulator-fixed";
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regulator-name = "vsys_3v3";
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regulator-min-microvolt = <3300000>;
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@ -140,6 +143,7 @@
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vdd_mmc1: regulator-3 {
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/* TPS2051BD */
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bootph-all;
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compatible = "regulator-fixed";
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regulator-name = "vdd_mmc1";
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regulator-min-microvolt = <3300000>;
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@ -161,6 +165,7 @@
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};
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vtt_supply: regulator-5 {
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bootph-all;
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compatible = "regulator-fixed";
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regulator-name = "vtt";
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pinctrl-names = "default";
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@ -251,6 +256,7 @@
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};
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main_uart0_pins_default: main-uart0-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
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AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
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@ -269,6 +275,7 @@
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};
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main_i2c0_pins_default: main-i2c0-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
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AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
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@ -276,6 +283,7 @@
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};
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main_i2c1_pins_default: main-i2c1-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
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AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
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@ -283,6 +291,7 @@
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};
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mdio1_pins_default: mdio1-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
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AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
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@ -290,6 +299,7 @@
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};
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rgmii1_pins_default: rgmii1-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
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AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
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@ -307,6 +317,7 @@
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};
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rgmii2_pins_default: rgmii2-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
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AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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@ -324,6 +335,7 @@
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};
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main_usb0_pins_default: main-usb0-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
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>;
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@ -366,6 +378,7 @@
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};
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ddr_vtt_pins_default: ddr-vtt-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
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>;
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@ -373,6 +386,7 @@
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};
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&main_uart0 {
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bootph-all;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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@ -387,6 +401,7 @@
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};
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&main_i2c0 {
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bootph-all;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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@ -400,12 +415,14 @@
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};
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&main_i2c1 {
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bootph-all;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@22 {
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bootph-all;
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compatible = "ti,tca6424";
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reg = <0x22>;
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gpio-controller;
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@ -438,6 +455,10 @@
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};
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};
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&main_gpio0 {
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bootph-all;
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};
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/* mcu_gpio0 is reserved for mcu firmware usage */
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&mcu_gpio0 {
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status = "reserved";
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@ -467,6 +488,7 @@
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&sdhci1 {
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/* SD/MMC */
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bootph-all;
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vmmc-supply = <&vdd_mmc1>;
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pinctrl-names = "default";
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bus-width = <4>;
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@ -476,11 +498,13 @@
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};
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&usbss0 {
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bootph-all;
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ti,vbus-divider;
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ti,usb2-only;
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};
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&usb0 {
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bootph-all;
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dr_mode = "otg";
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maximum-speed = "high-speed";
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pinctrl-names = "default";
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@ -488,11 +512,13 @@
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};
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&cpsw3g {
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bootph-all;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
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};
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&cpsw_port1 {
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bootph-all;
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy0>;
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};
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@ -503,11 +529,13 @@
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};
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&cpsw3g_mdio {
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bootph-all;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mdio1_pins_default>;
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cpsw3g_phy0: ethernet-phy@0 {
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bootph-all;
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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