mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
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set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Huang Shijie
David Woodhouse
parent
3946860409
commit
921de864b7
@ -349,10 +349,32 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan)
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clk_disable_unprepare(mxs_dma->clk);
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}
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/*
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* How to use the flags for ->device_prep_slave_sg() :
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* [1] If there is only one DMA command in the DMA chain, the code should be:
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* ......
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* ->device_prep_slave_sg(DMA_CTRL_ACK);
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* ......
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* [2] If there are two DMA commands in the DMA chain, the code should be
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* ......
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* ->device_prep_slave_sg(0);
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* ......
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* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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* ......
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* [3] If there are more than two DMA commands in the DMA chain, the code
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* should be:
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* ......
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* ->device_prep_slave_sg(0); // First
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* ......
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* ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
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* ......
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* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
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* ......
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*/
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static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long append)
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unsigned long flags)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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@ -360,6 +382,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
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struct scatterlist *sg;
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int i, j;
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u32 *pio;
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bool append = flags & DMA_PREP_INTERRUPT;
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int idx = append ? mxs_chan->desc_count : 0;
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if (mxs_chan->status == DMA_IN_PROGRESS && !append)
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@ -386,7 +409,6 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
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ccw->bits |= CCW_CHAIN;
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ccw->bits &= ~CCW_IRQ;
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ccw->bits &= ~CCW_DEC_SEM;
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ccw->bits &= ~CCW_WAIT4END;
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} else {
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idx = 0;
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}
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@ -401,7 +423,8 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
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ccw->bits = 0;
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ccw->bits |= CCW_IRQ;
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ccw->bits |= CCW_DEC_SEM;
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ccw->bits |= CCW_WAIT4END;
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if (flags & DMA_CTRL_ACK)
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ccw->bits |= CCW_WAIT4END;
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ccw->bits |= CCW_HALT_ON_TERM;
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ccw->bits |= CCW_TERM_FLUSH;
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ccw->bits |= BF_CCW(sg_len, PIO_NUM);
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@ -432,7 +455,8 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
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ccw->bits &= ~CCW_CHAIN;
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ccw->bits |= CCW_IRQ;
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ccw->bits |= CCW_DEC_SEM;
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ccw->bits |= CCW_WAIT4END;
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if (flags & DMA_CTRL_ACK)
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ccw->bits |= CCW_WAIT4END;
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}
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}
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}
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@ -305,7 +305,7 @@ static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
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}
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static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
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struct mxs_mmc_host *host, unsigned int append)
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struct mxs_mmc_host *host, unsigned long flags)
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{
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struct dma_async_tx_descriptor *desc;
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struct mmc_data *data = host->data;
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@ -325,7 +325,7 @@ static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
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}
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desc = host->dmach->device->device_prep_slave_sg(host->dmach,
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sgl, sg_len, host->slave_dirn, append);
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sgl, sg_len, host->slave_dirn, flags);
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if (desc) {
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desc->callback = mxs_mmc_dma_irq_callback;
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desc->callback_param = host;
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@ -358,7 +358,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
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host->ssp_pio_words[2] = cmd1;
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host->dma_dir = DMA_NONE;
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host->slave_dirn = DMA_TRANS_NONE;
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desc = mxs_mmc_prep_dma(host, 0);
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desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
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if (!desc)
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goto out;
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@ -398,7 +398,7 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
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host->ssp_pio_words[2] = cmd1;
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host->dma_dir = DMA_NONE;
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host->slave_dirn = DMA_TRANS_NONE;
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desc = mxs_mmc_prep_dma(host, 0);
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desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
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if (!desc)
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goto out;
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@ -526,7 +526,7 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
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host->data = data;
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host->dma_dir = dma_data_dir;
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host->slave_dirn = slave_dirn;
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desc = mxs_mmc_prep_dma(host, 1);
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desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc)
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goto out;
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@ -849,7 +849,9 @@ int gpmi_send_command(struct gpmi_nand_data *this)
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sg_init_one(sgl, this->cmd_buffer, this->command_length);
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dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
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desc = channel->device->device_prep_slave_sg(channel,
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sgl, 1, DMA_MEM_TO_DEV, 1);
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sgl, 1, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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pr_err("step 2 error\n");
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return -1;
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@ -891,7 +893,8 @@ int gpmi_send_data(struct gpmi_nand_data *this)
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/* [2] send DMA request */
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prepare_data_dma(this, DMA_TO_DEVICE);
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desc = channel->device->device_prep_slave_sg(channel, &this->data_sgl,
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1, DMA_MEM_TO_DEV, 1);
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1, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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pr_err("step 2 error\n");
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return -1;
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@ -927,7 +930,8 @@ int gpmi_read_data(struct gpmi_nand_data *this)
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/* [2] : send DMA request */
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prepare_data_dma(this, DMA_FROM_DEVICE);
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desc = channel->device->device_prep_slave_sg(channel, &this->data_sgl,
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1, DMA_DEV_TO_MEM, 1);
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1, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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pr_err("step 2 error\n");
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return -1;
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@ -974,7 +978,8 @@ int gpmi_send_page(struct gpmi_nand_data *this,
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desc = channel->device->device_prep_slave_sg(channel,
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(struct scatterlist *)pio,
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ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
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ARRAY_SIZE(pio), DMA_TRANS_NONE,
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DMA_CTRL_ACK);
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if (!desc) {
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pr_err("step 2 error\n");
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return -1;
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@ -1038,7 +1043,8 @@ int gpmi_read_page(struct gpmi_nand_data *this,
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pio[5] = auxiliary;
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desc = channel->device->device_prep_slave_sg(channel,
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(struct scatterlist *)pio,
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ARRAY_SIZE(pio), DMA_TRANS_NONE, 1);
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ARRAY_SIZE(pio), DMA_TRANS_NONE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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pr_err("step 2 error\n");
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return -1;
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@ -1057,7 +1063,8 @@ int gpmi_read_page(struct gpmi_nand_data *this,
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pio[1] = 0;
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desc = channel->device->device_prep_slave_sg(channel,
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(struct scatterlist *)pio, 2,
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DMA_TRANS_NONE, 1);
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DMA_TRANS_NONE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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pr_err("step 3 error\n");
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return -1;
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