drm/xe: Standardize power gate registers
Standardize power gate registers No functional changes v2: change commit message (Rodrigo) Signed-off-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-2-riana.tauro@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -316,11 +316,9 @@
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#define FORCEWAKE_GT XE_REG(0xa188)
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#define PG_ENABLE XE_REG(0xa210)
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#define VD2_MFXVDENC_POWERGATE_ENABLE REG_BIT(8)
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#define VD2_HCP_POWERGATE_ENABLE REG_BIT(7)
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#define VD0_MFXVDENC_POWERGATE_ENABLE REG_BIT(4)
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#define VD0_HCP_POWERGATE_ENABLE REG_BIT(3)
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#define POWERGATE_ENABLE XE_REG(0xa210)
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#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
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#define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
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#define CTC_MODE XE_REG(0xa26c)
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#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
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@ -202,7 +202,7 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt)
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xe_device_assert_mem_access(gt_to_xe(gt));
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xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);
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xe_mmio_write32(gt, PG_ENABLE, 0);
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xe_mmio_write32(gt, POWERGATE_ENABLE, 0);
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xe_mmio_write32(gt, RC_CONTROL, 0);
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xe_mmio_write32(gt, RC_STATE, 0);
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}
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@ -238,11 +238,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
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},
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{ XE_RTP_NAME("14020316580"),
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XE_RTP_RULES(MEDIA_VERSION(1301)),
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XE_RTP_ACTIONS(CLR(PG_ENABLE,
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VD0_HCP_POWERGATE_ENABLE |
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VD0_MFXVDENC_POWERGATE_ENABLE |
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VD2_HCP_POWERGATE_ENABLE |
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VD2_MFXVDENC_POWERGATE_ENABLE)),
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XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
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VDN_HCP_POWERGATE_ENABLE(0) |
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VDN_MFXVDENC_POWERGATE_ENABLE(0) |
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VDN_HCP_POWERGATE_ENABLE(2) |
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VDN_MFXVDENC_POWERGATE_ENABLE(2))),
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},
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{ XE_RTP_NAME("14019449301"),
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XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
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