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drm/xe/irq: Add helpers to find ISR/IIR/IMR/IER registers

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For cases where IRQ_INIT and IRQ_RESET are used, the relevant interrupt
registers are always consecutive and ordered ISR, IMR, IIR, IER.  Adding
helpers to look these up from a base offset will let us eliminate some
of the CPP pasting and simplify other upcoming patches.

v2:
 - s/_REGS/_OFFSET/ for consistency.  (Lucas)
 - Move IMR/IIR/IER helpers into xe_irq.c; they aren't needed anywhere
   else.  (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230401002106.588656-3-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-03-31 17:21:00 -07:00 committed by Rodrigo Vivi
parent 06d06064f7
commit 9293b67de6
2 changed files with 22 additions and 21 deletions
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11
drivers/gpu/drm/xe/regs/xe_regs.h
View File

@ -72,15 +72,8 @@
#define SOFTWARE_FLAGS_SPR33 _MMIO(0x4f084)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
#define GEN8_PCU_IIR _MMIO(0x444e8)
#define GEN8_PCU_IER _MMIO(0x444ec)
#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
#define GEN11_GU_MISC_IER _MMIO(0x444fc)
#define PCU_IRQ_OFFSET 0x444e0
#define GU_MISC_IRQ_OFFSET 0x444f0
#define GEN11_GU_MISC_GSE (1 << 27)
#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)

32
drivers/gpu/drm/xe/xe_irq.c
View File

@ -18,6 +18,14 @@
#include "xe_hw_engine.h"
#include "xe_mmio.h"
/*
* Interrupt registers for a unit are always consecutive and ordered
* ISR, IMR, IIR, IER.
*/
#define IMR(offset) _MMIO(offset + 0x4)
#define IIR(offset) _MMIO(offset + 0x8)
#define IER(offset) _MMIO(offset + 0xc)
static void assert_iir_is_zero(struct xe_gt *gt, i915_reg_t reg)
{
u32 val = xe_mmio_read32(gt, reg.reg);
@ -47,9 +55,9 @@ static void irq_init(struct xe_gt *gt,
}
#define IRQ_INIT(gt, type, imr_val, ier_val) \
irq_init((gt), \
type##IMR, imr_val, \
type##IER, ier_val, \
type##IIR)
IMR(type), imr_val, \
IER(type), ier_val, \
IIR(type))
static void irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
i915_reg_t ier)
@ -66,7 +74,7 @@ static void irq_reset(struct xe_gt *gt, i915_reg_t imr, i915_reg_t iir,
xe_mmio_read32(gt, iir.reg);
}
#define IRQ_RESET(gt, type) \
irq_reset((gt), type##IMR, type##IIR, type##IER)
irq_reset((gt), IMR(type), IIR(type), IER(type))
static u32 gen11_intr_disable(struct xe_gt *gt)
{
@ -89,9 +97,9 @@ gen11_gu_misc_irq_ack(struct xe_gt *gt, const u32 master_ctl)
if (!(master_ctl & GEN11_GU_MISC_IRQ))
return 0;
iir = xe_mmio_read32(gt, GEN11_GU_MISC_IIR.reg);
iir = xe_mmio_read32(gt, IIR(GU_MISC_IRQ_OFFSET).reg);
if (likely(iir))
xe_mmio_write32(gt, GEN11_GU_MISC_IIR.reg, iir);
xe_mmio_write32(gt, IIR(GU_MISC_IRQ_OFFSET).reg, iir);
return iir;
}
@ -172,7 +180,7 @@ static void gen11_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
gen11_gt_irq_postinstall(xe, gt);
IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
IRQ_INIT(gt, GU_MISC_IRQ_OFFSET, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
gen11_intr_enable(gt, true);
}
@ -331,7 +339,7 @@ static void dg1_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
{
gen11_gt_irq_postinstall(xe, gt);
IRQ_INIT(gt, GEN11_GU_MISC_, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
IRQ_INIT(gt, GU_MISC_IRQ_OFFSET, ~GEN11_GU_MISC_GSE, GEN11_GU_MISC_GSE);
if (gt->info.id == XE_GT0)
dg1_intr_enable(xe, true);
@ -432,8 +440,8 @@ static void gen11_irq_reset(struct xe_gt *gt)
gen11_gt_irq_reset(gt);
IRQ_RESET(gt, GEN11_GU_MISC_);
IRQ_RESET(gt, GEN8_PCU_);
IRQ_RESET(gt, GU_MISC_IRQ_OFFSET);
IRQ_RESET(gt, PCU_IRQ_OFFSET);
}
static void dg1_irq_reset(struct xe_gt *gt)
@ -443,8 +451,8 @@ static void dg1_irq_reset(struct xe_gt *gt)
gen11_gt_irq_reset(gt);
IRQ_RESET(gt, GEN11_GU_MISC_);
IRQ_RESET(gt, GEN8_PCU_);
IRQ_RESET(gt, GU_MISC_IRQ_OFFSET);
IRQ_RESET(gt, PCU_IRQ_OFFSET);
}
static void xe_irq_reset(struct xe_device *xe)