perf/x86/intel: Fix PT PMI handling
Commit:ccbebba4c6
("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") skips the PT/LBR exclusivity check on CPUs where PT and LBRs coexist, but also inadvertently skips the active_events bump for PT in that case, which is a bug. If there aren't any hardware events at the same time as PT, the PMI handler will ignore PT PMIs, as active_events reads zero in that case, resulting in the "Uhhuh" spurious NMI warning and PT data loss. Fix this by always increasing active_events for PT events. Fixes:ccbebba4c6
("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") Reported-by: Vitaly Slobodskoy <vitaly.slobodskoy@intel.com> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Alexey Budankov <alexey.budankov@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Link: https://lkml.kernel.org/r/20191210105101.77210-1-alexander.shishkin@linux.intel.com
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@ -376,7 +376,7 @@ int x86_add_exclusive(unsigned int what)
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* LBR and BTS are still mutually exclusive.
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*/
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if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
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return 0;
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goto out;
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if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
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mutex_lock(&pmc_reserve_mutex);
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@ -388,6 +388,7 @@ int x86_add_exclusive(unsigned int what)
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mutex_unlock(&pmc_reserve_mutex);
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}
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out:
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atomic_inc(&active_events);
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return 0;
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@ -398,11 +399,15 @@ fail_unlock:
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void x86_del_exclusive(unsigned int what)
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{
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atomic_dec(&active_events);
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/*
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* See the comment in x86_add_exclusive().
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*/
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if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
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return;
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atomic_dec(&x86_pmu.lbr_exclusive[what]);
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atomic_dec(&active_events);
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}
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int x86_setup_perfctr(struct perf_event *event)
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