sh fixes for v6.5
- sh: hd64461: Handle virq offset for offchip IRQ base and HD64461 IRQ - sh: mach-dreamcast: Handle virq offset in cascaded IRQ demux - sh: mach-highlander: Handle virq offset in cascaded IRL demux - sh: mach-r2d: Handle virq offset in cascaded IRL demux -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEYv+KdYTgKVaVRgAGdCY7N/W1+RMFAmSvnMUACgkQdCY7N/W1 +RPGFxAAuditVmg2hw2fZ8fcMBxcyB29LH8ker7bVyZemY7xvsVjfs9AcGwZpXV2 xda3C4v65GnUXmLcITyjv2rk2HhUpw4hk5q92wWyslohiNaZ+AHmEv72Ws0/jdlI ds/5sm8+5oPA6/NROU/ywyAUh8EY2SpCs3VEX+4rZQL4wDjlNyWqCyAljILuYum0 p0eAO2b+xRO9kkXP+CYPfFEEZRVW122uTVBXaTDmcNf1gTxpp0R72F7RL/goyubq xroTUQxFEqfTNsDQDVKdBpGFsDVMvoTz6PDWNETee7ZcmC7qu0+mTc80+pzalUMC VAdRhpu11PCG+1V2f4rvOJK9UIpdHPz9EnATUznNFdVrE2g4VmybXkDGTq1wSgZD 2ug3llWTZRmvT1zTNqzfuMudEYY0P4MJXYGSmqNOUJXEBb1PWklfNfHoD6LUVX0l 0E02G8cwPRLKqHOi9UOKfbcltMC4c66yil044y0KeN2ynRSUzIiHbsvfUE/NGasJ qy5L78o/3pNU4Bht1UvUEnMT+j95/0kAkdXuzQdKm2f3AEosygX0cWLDMiJMtJwl Uf5O8oftX1qMjU8F/MnIACNi8dMT41Dr7IEzHjQ33tfzLMJ2iZ6pk1ZMRxxyNfjP rMguwJpuJ91R5mkcC5hlaYxbpjTVqQQ/Sg3pXXOpRH6OeS/3ccg= =9yTF -----END PGP SIGNATURE----- Merge tag 'sh-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux Pull sh fixes from John Paul Adrian Glaubitz: "The sh updates introduced multiple regressions. In particular, the change a8ac2961148e ("sh: Avoid using IRQ0 on SH3 and SH4") causes several boards to hang during boot due to incorrect IRQ numbers. Geert Uytterhoeven has contributed patches that handle the virq offset in the IRQ code for the dreamcast, highlander and r2d boards while Artur Rojek has contributed a patch which handles the virq offset for the hd64461 companion chip" * tag 'sh-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux: sh: hd64461: Handle virq offset for offchip IRQ base and HD64461 IRQ sh: mach-dreamcast: Handle virq offset in cascaded IRQ demux sh: mach-highlander: Handle virq offset in cascaded IRL demux sh: mach-r2d: Handle virq offset in cascaded IRL demux
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commit
9350cd0190
@ -108,13 +108,13 @@ int systemasic_irq_demux(int irq)
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__u32 j, bit;
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switch (irq) {
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case 13:
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case 13 + 16:
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level = 0;
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break;
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case 11:
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case 11 + 16:
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level = 1;
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break;
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case 9:
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case 9 + 16:
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level = 2;
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break;
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default:
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@ -389,10 +389,10 @@ static unsigned char irl2irq[HL_NR_IRL];
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static int highlander_irq_demux(int irq)
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{
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if (irq >= HL_NR_IRL || irq < 0 || !irl2irq[irq])
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if (irq >= HL_NR_IRL + 16 || irq < 16 || !irl2irq[irq - 16])
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return irq;
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return irl2irq[irq];
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return irl2irq[irq - 16];
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}
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static void __init highlander_init_irq(void)
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@ -117,10 +117,10 @@ static unsigned char irl2irq[R2D_NR_IRL];
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int rts7751r2d_irq_demux(int irq)
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{
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if (irq >= R2D_NR_IRL || irq < 0 || !irl2irq[irq])
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if (irq >= R2D_NR_IRL + 16 || irq < 16 || !irl2irq[irq - 16])
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return irq;
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return irl2irq[irq];
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return irl2irq[irq - 16];
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}
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/*
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@ -29,9 +29,9 @@ endchoice
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config HD64461_IRQ
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int "HD64461 IRQ"
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depends on HD64461
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default "36"
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default "52"
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help
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The default setting of the HD64461 IRQ is 36.
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The default setting of the HD64461 IRQ is 52.
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Do not change this unless you know what you are doing.
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@ -229,7 +229,7 @@
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#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
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#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
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#define OFFCHIP_IRQ_BASE 64
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#define OFFCHIP_IRQ_BASE (64 + 16)
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#define HD64461_IRQ_NUM 16
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#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
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