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drm/amd/display: get socBB from VBIOS

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[why]
Some SOC BB paramters may vary per SKU, and it does
not make sense for driver to hardcode these values

[how]
Parse the values from VBIOS if available, and use
them if valid

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jun Lei 2020-02-12 11:29:06 -05:00 committed by Alex Deucher
parent e9462a3279
commit 93669c8e48
4 changed files with 96 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -847,6 +847,73 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
return result;
}
static enum bp_result get_soc_bb_info_v4_4(
struct bios_parser *bp,
struct bp_soc_bb_info *soc_bb_info)
{
enum bp_result result = BP_RESULT_OK;
struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
if (!soc_bb_info)
return BP_RESULT_BADINPUT;
if (!DATA_TABLES(dce_info))
return BP_RESULT_BADBIOSTABLE;
if (!DATA_TABLES(smu_info))
return BP_RESULT_BADBIOSTABLE;
disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
DATA_TABLES(dce_info));
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
return result;
}
static enum bp_result bios_parser_get_soc_bb_info(
struct dc_bios *dcb,
struct bp_soc_bb_info *soc_bb_info)
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
enum bp_result result = BP_RESULT_UNSUPPORTED;
struct atom_common_table_header *header;
struct atom_data_revision tbl_revision;
if (!soc_bb_info) /* check for bad input */
return BP_RESULT_BADINPUT;
if (!DATA_TABLES(dce_info))
return BP_RESULT_UNSUPPORTED;
header = GET_IMAGE(struct atom_common_table_header,
DATA_TABLES(dce_info));
get_atom_data_table_revision(header, &tbl_revision);
switch (tbl_revision.major) {
case 4:
switch (tbl_revision.minor) {
case 1:
case 2:
case 3:
break;
case 4:
result = get_soc_bb_info_v4_4(bp, soc_bb_info);
default:
break;
}
break;
default:
break;
}
return result;
}
static enum bp_result get_embedded_panel_info_v2_1(
struct bios_parser *bp,
struct embedded_panel_info *info)
@ -2222,7 +2289,9 @@ static const struct dc_vbios_funcs vbios_funcs = {
.get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
.enable_lvtma_control = bios_parser_enable_lvtma_control
.enable_lvtma_control = bios_parser_enable_lvtma_control,
.get_soc_bb_info = bios_parser_get_soc_bb_info,
};
static bool bios_parser2_construct(

4
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
View File

@ -140,6 +140,10 @@ struct dc_vbios_funcs {
enum bp_result (*enable_lvtma_control)(
struct dc_bios *bios,
uint8_t uc_pwr_on);
enum bp_result (*get_soc_bb_info)(
struct dc_bios *dcb,
struct bp_soc_bb_info *soc_bb_info);
};
struct bios_registers {

16
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@ -1828,6 +1828,22 @@ static bool init_soc_bounding_box(struct dc *dc,
loaded_ip->max_num_dpp = pool->base.pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
dcn20_patch_bounding_box(dc, loaded_bb);
if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) {
struct bp_soc_bb_info bb_info = {0};
if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
if (bb_info.dram_clock_change_latency_100ns > 0)
dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
if (bb_info.dram_sr_exit_latency_100ns > 0)
dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
}
}
return true;
}

6
drivers/gpu/drm/amd/display/include/bios_parser_types.h
View File

@ -318,4 +318,10 @@ struct bp_encoder_cap_info {
uint32_t RESERVED:27;
};
struct bp_soc_bb_info {
uint32_t dram_clock_change_latency_100ns;
uint32_t dram_sr_exit_latency_100ns;
uint32_t dram_sr_enter_exit_latency_100ns;
};
#endif /*__DAL_BIOS_PARSER_TYPES_H__ */