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Here is the bulk of pin control changes for the v4.2 series:

Browse Source 
- Core functionality:
   - Enable exclusive pin ownership: it is possible to flag a pin
     controller so that GPIO and other functions cannot use a single
     pin simultaneously.
 
 - New drivers:
   - NXP LPC18xx System Control Unit pin controller
   - Imagination Pistachio SoC pin controller
 
 - New subdrivers:
   - Freescale i.MX7d SoC
   - Intel Sunrisepoint-H PCH
   - Renesas PFC R8A7793
   - Renesas PFC R8A7794
   - Mediatek MT6397, MT8127
   - SiRF Atlas 7
   - Allwinner A33
   - Qualcomm MSM8660
   - Marvell Armada 395
   - Rockchip RK3368
 
 - Cleanups:
   - A big cleanup of the Marvell MVEBU driver rectifying it to
     correspond to reality
   - Drop platform device probing from the SH PFC driver, we are now a
     DT only shop for SuperH
   - Drop obsolte multi-platform check for SH PFC
   - Various janitorial: constification, grammar etc
 
 - Improvements:
   - The AT91 GPIO portions now supports the set_multiple() feature
   - Split out SPI pins on the Xilinx Zynq
   - Support DTs without specific function nodes in the i.MX driver
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Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Here is the bulk of pin control changes for the v4.2 series: Quite a
  lot of new SoC subdrivers and two new main drivers this time, apart
  from that business as usual.

  Details:

  Core functionality:
   - Enable exclusive pin ownership: it is possible to flag a pin
     controller so that GPIO and other functions cannot use a single pin
     simultaneously.

  New drivers:
   - NXP LPC18xx System Control Unit pin controller
   - Imagination Pistachio SoC pin controller

  New subdrivers:
   - Freescale i.MX7d SoC
   - Intel Sunrisepoint-H PCH
   - Renesas PFC R8A7793
   - Renesas PFC R8A7794
   - Mediatek MT6397, MT8127
   - SiRF Atlas 7
   - Allwinner A33
   - Qualcomm MSM8660
   - Marvell Armada 395
   - Rockchip RK3368

  Cleanups:
   - A big cleanup of the Marvell MVEBU driver rectifying it to
     correspond to reality
   - Drop platform device probing from the SH PFC driver, we are now a
     DT only shop for SuperH
   - Drop obsolte multi-platform check for SH PFC
   - Various janitorial: constification, grammar etc

  Improvements:
   - The AT91 GPIO portions now supports the set_multiple() feature
   - Split out SPI pins on the Xilinx Zynq
   - Support DTs without specific function nodes in the i.MX driver"

* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: rockchip: add support for the rk3368
  pinctrl: rockchip: generalize perpin driver-strength setting
  pinctrl: sh-pfc: r8a7794: add SDHI pin groups
  pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
  pinctrl: sh-pfc: add R8A7794 PFC support
  pinctrl: make pinctrl_register() return proper error code
  pinctrl: mvebu: armada-39x: add support for Armada 395 variant
  pinctrl: mvebu: armada-39x: add missing SATA functions
  pinctrl: mvebu: armada-39x: add missing PCIe functions
  pinctrl: mvebu: armada-38x: add ptp functions
  pinctrl: mvebu: armada-38x: add ua1 functions
  pinctrl: mvebu: armada-38x: add nand functions
  pinctrl: mvebu: armada-38x: add sata functions
  pinctrl: mvebu: armada-xp: add dram functions
  pinctrl: mvebu: armada-xp: add nand rb function
  pinctrl: mvebu: armada-xp: add spi1 function
  pinctrl: mvebu: armada-39x: normalize ref clock naming
  pinctrl: mvebu: armada-xp: rename spi to spi0
  pinctrl: mvebu: armada-370: align spi1 clock pin naming
  pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
  ...
This commit is contained in:
Linus Torvalds 2015-06-24 19:21:02 -07:00
commit 93a4b1b946
113 changed files with 18261 additions and 843 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
Documentation/devicetree/bindings/gpio/gpio-atlas7.txt Normal file
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@ -0,0 +1,50 @@
CSR SiRFatlas7 GPIO controller bindings
Required properties:
- compatible : "sirf,atlas7-gpio"
- reg : Address range of the pinctrl registers
- interrupts : Interrupts used by every GPIO group
- gpio-banks : How many gpio banks on this controller
- gpio-controller : Indicates this device is a GPIO controller
- interrupt-controller : Marks the device node as an interrupt controller
The GPIO controller also acts as an interrupt controller. It uses the default
two cells specifier as described in Documentation/devicetree/bindings/
interrupt-controller/interrupts.txt.
Example:
gpio_0: gpio_mediam@17040000 {
compatible = "sirf,atlas7-gpio";
reg = <0x17040000 0x1000>;
interrupts = <0 13 0>, <0 14 0>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
gpio-banks = <2>;
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>;
gpio-ranges-group-names = "lvds_gpio_grp",
"uart_nand_gpio_grp";
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&gpio_1 15 0>;
...
};
led2 {
gpios = <&gpio_2 34 0>;
...
};
};
Please refer to gpio.txt in this directory for details of the common
gpio properties used by devices.

2
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
View File

@ -16,6 +16,8 @@ Required properties:
"allwinner,sun7i-a20-pinctrl"
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
"allwinner,sun8i-a33-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.

217
Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt Normal file
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@ -0,0 +1,217 @@
Imagination Technologies Pistachio SoC pin controllers
======================================================
The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
interrupt controller, and pinmux + pinconf device. The system ("east") pin
controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs
each. The GPIO banks are represented as sub-nodes of the pad controller node.
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.
Required properties for pin controller node:
--------------------------------------------
- compatible: "img,pistachio-system-pinctrl".
- reg: Address range of the pinctrl registers.
Required properties for GPIO bank sub-nodes:
--------------------------------------------
- interrupts: Interrupt line for the GPIO bank.
- gpio-controller: Indicates the device is a GPIO controller.
- #gpio-cells: Must be two. The first cell is the GPIO pin number and the
second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for
a list of possible values.
- interrupt-controller: Indicates the device is an interrupt controller.
- #interrupt-cells: Must be two. The first cell is the GPIO pin number and
the second cell encodes the interrupt flags. See
<dt-bindings/interrupt-controller/irq.h> for a list of valid flags.
Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.
Required properties for pin configuration sub-nodes:
----------------------------------------------------
- pins: List of pins to which the configuration applies. See below for a
list of possible pins.
Optional properties for pin configuration sub-nodes:
----------------------------------------------------
- function: Mux function for the specified pins. This is not applicable for
non-MFIO pins. See below for a list of valid functions for each pin.
- bias-high-impedance: Enable high-impedance mode.
- bias-pull-up: Enable weak pull-up.
- bias-pull-down: Enable weak pull-down.
- bias-bus-hold: Enable bus-keeper mode.
- drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.
- input-schmitt-enable: Enable Schmitt trigger.
- input-schmitt-disable: Disable Schmitt trigger.
- slew-rate: Slew rate control. 0 for slow, 1 for fast.
Pin Functions
--- ---------
mfio0 spim1
mfio1 spim1, spim0, uart1
mfio2 spim1, spim0, uart1
mfio3 spim1
mfio4 spim1
mfio5 spim1
mfio6 spim1
mfio7 spim1
mfio8 spim0
mfio9 spim0
mfio10 spim0
mfio11 spis
mfio12 spis
mfio13 spis
mfio14 spis
mfio15 sdhost, mips_trace_clk, mips_trace_data
mfio16 sdhost, mips_trace_dint, mips_trace_data
mfio17 sdhost, mips_trace_trigout, mips_trace_data
mfio18 sdhost, mips_trace_trigin, mips_trace_data
mfio19 sdhost, mips_trace_dm, mips_trace_data
mfio20 sdhost, mips_trace_probe_n, mips_trace_data
mfio21 sdhost, mips_trace_data
mfio22 sdhost, mips_trace_data
mfio23 sdhost
mfio24 sdhost
mfio25 sdhost
mfio26 sdhost
mfio27 sdhost
mfio28 i2c0, spim0
mfio29 i2c0, spim0
mfio30 i2c1, spim0
mfio31 i2c1, spim1
mfio32 i2c2
mfio33 i2c2
mfio34 i2c3
mfio35 i2c3
mfio36 i2s_out, audio_clk_in
mfio37 i2s_out, debug_raw_cca_ind
mfio38 i2s_out, debug_ed_sec20_cca_ind
mfio39 i2s_out, debug_ed_sec40_cca_ind
mfio40 i2s_out, debug_agc_done_0
mfio41 i2s_out, debug_agc_done_1
mfio42 i2s_out, debug_ed_cca_ind
mfio43 i2s_out, debug_s2l_done
mfio44 i2s_out
mfio45 i2s_dac_clk, audio_sync
mfio46 audio_trigger
mfio47 i2s_in
mfio48 i2s_in
mfio49 i2s_in
mfio50 i2s_in
mfio51 i2s_in
mfio52 i2s_in
mfio53 i2s_in
mfio54 i2s_in, spdif_in
mfio55 uart0, spim0, spim1
mfio56 uart0, spim0, spim1
mfio57 uart0, spim0, spim1
mfio58 uart0, spim1
mfio59 uart1
mfio60 uart1
mfio61 spdif_out
mfio62 spdif_in
mfio63 eth, mips_trace_clk, mips_trace_data
mfio64 eth, mips_trace_dint, mips_trace_data
mfio65 eth, mips_trace_trigout, mips_trace_data
mfio66 eth, mips_trace_trigin, mips_trace_data
mfio67 eth, mips_trace_dm, mips_trace_data
mfio68 eth, mips_trace_probe_n, mips_trace_data
mfio69 eth, mips_trace_data
mfio70 eth, mips_trace_data
mfio71 eth
mfio72 ir
mfio73 pwmpdm, mips_trace_clk, sram_debug
mfio74 pwmpdm, mips_trace_dint, sram_debug
mfio75 pwmpdm, mips_trace_trigout, rom_debug
mfio76 pwmpdm, mips_trace_trigin, rom_debug
mfio77 mdc_debug, mips_trace_dm, rpu_debug
mfio78 mdc_debug, mips_trace_probe_n, rpu_debug
mfio79 ddr_debug, mips_trace_data, mips_debug
mfio80 ddr_debug, mips_trace_data, mips_debug
mfio81 dreq0, mips_trace_data, eth_debug
mfio82 dreq1, mips_trace_data, eth_debug
mfio83 mips_pll_lock, mips_trace_data, usb_debug
mfio84 sys_pll_lock, mips_trace_data, usb_debug
mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug
mfio86 bt_pll_lock, mips_trace_data, sdhost_debug
mfio87 rpu_v_pll_lock, dreq2, socif_debug
mfio88 rpu_l_pll_lock, dreq3, socif_debug
mfio89 audio_pll_lock, dreq4, dreq5
tck
trstn
tdi
tms
tdo
jtag_comply
safe_mode
por_disable
resetn
Example:
--------
pinctrl@18101C00 {
compatible = "img,pistachio-system-pinctrl";
reg = <0x18101C00 0x400>;
gpio0: gpio0 {
interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
gpio5: gpio5 {
interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
uart0_xfer: uart0-xfer {
uart0-rxd {
pins = "mfio55";
function = "uart0";
};
uart0-txd {
pins = "mfio56";
function = "uart0";
};
};
uart0_rts_cts: uart0-rts-cts {
uart0-rts {
pins = "mfio57";
function = "uart0";
};
uart0-cts {
pins = "mfio58";
function = "uart0";
};
};
};
uart@... {
...
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;
...
};
usb_vbus: fixed-regulator {
...
gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
...
};

18
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
View File

@ -17,10 +17,10 @@ mpp0 0 gpio, uart0(rxd)
mpp1 1 gpo, uart0(txd)
mpp2 2 gpio, i2c0(sck), uart0(txd)
mpp3 3 gpio, i2c0(sda), uart0(rxd)
mpp4 4 gpio, cpu_pd(vdd)
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
mpp4 4 gpio, vdd(cpu-pd)
mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
mpp31 31 gpio, tclk, ge0(txerr)
mpp32 32 gpio, spi0(cs0)
mpp33 33 gpio, dev(bootcs), spi0(cs0)
mpp34 34 gpo, dev(wen0), spi0(mosi)
mpp35 35 gpo, dev(oen), spi0(sck)
mpp34 34 gpo, dev(we0), spi0(mosi)
mpp35 35 gpo, dev(oe), spi0(sck)
mpp36 36 gpo, dev(a1), spi0(miso)
mpp37 37 gpo, dev(a0), sata0(prsnt)
mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
@ -86,11 +86,11 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
uart0(rts)
mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
audio(sdi)
mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
audio(mclk), uart0(cts)
mpp63 63 gpo, spi0(sck), tclk
mpp64 64 gpio, spi0(miso), spi0-1(cs1)
mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
mpp64 64 gpio, spi0(miso), spi0(cs1)
mpp65 65 gpio, spi0(mosi), spi0(cs2)

34
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
View File

@ -15,24 +15,24 @@ name pins functions
================================================================================
mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk)
mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
mpp10 10 gpio, dram(vttctrl), led(c1), nand(re)
mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
mpp12 12 gpio, dev(a1), audio(bclk)
mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout)
mpp14 14 gpio, i2c0(sda), uart1(txd)
mpp15 15 gpio, i2c0(sck), uart1(rxd)
mpp16 16 gpio, uart0(txd)
mpp17 17 gpio, uart0(rxd)
mpp18 18 gpio, tdm(intn)
mpp19 19 gpio, tdm(rstn)
mpp18 18 gpio, tdm(int)
mpp19 19 gpio, tdm(rst)
mpp20 20 gpio, tdm(pclk)
mpp21 21 gpio, tdm(fsync)
mpp22 22 gpio, tdm(drx)
@ -45,12 +45,12 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
mpp30 30 gpio, ge1(txd0), spi1(cs0)
mpp31 31 gpio, ge1(txd1), spi1(mosi)
mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig)
mpp33 33 gpio, ge1(txd3), spi1(miso)
mpp34 34 gpio, ge1(txclkout), spi1(sck)
mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
mpp36 36 gpio, pcie0(clkreq)
mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc)
mpp38 38 gpio, pcie1(clkreq), ge(mdio)
mpp39 39 gpio, ref(clkout)
mpp40 40 gpio, uart1(txd)
@ -58,25 +58,25 @@ mpp41 41 gpio, uart1(rxd)
mpp42 42 gpio, spi1(cs2), led(c0)
mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
mpp44 44 gpio, sata0(prsnt)
mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
mpp45 45 gpio, spi0(cs2), pcie0(rstout)
mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1)
mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3)
mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl)
mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
mpp57 57 gpio, ge0(txctl), ge1(txctl)
mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0)
mpp58 58 gpio, led(c0)
mpp59 59 gpio, led(c1)
mpp60 60 gpio, uart1(txd), led(c2)
mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
mpp62 62 gpio, i2c1(sck), led(p1)
mpp63 63 gpio, ptp(triggen), led(p2)
mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last)
mpp64 64 gpio, dram(vttctrl), led(p3)
mpp65 65 gpio, sata1(prsnt)
mpp66 66 gpio, ptp(eventreq), spi1(cs3)
mpp66 66 gpio, ptp(evreq), spi1(cs3)

66
Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
View File

@ -27,16 +27,16 @@ mpp8 8 gpio, ge0(txd1), dev(ad10)
mpp9 9 gpio, ge0(txd2), dev(ad11)
mpp10 10 gpio, ge0(txd3), dev(ad12)
mpp11 11 gpio, ge0(txctl), dev(ad13)
mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq)
mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1]
mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt)
mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0)
mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts)
mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts)
mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt)
mpp22 22 gpio, spi0(mosi), dev(ad0)
mpp23 23 gpio, spi0(sck), dev(ad2)
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
@ -45,36 +45,36 @@ mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
mpp29 29 gpio, ge1(txd1), dev(ale0)
mpp30 30 gpio, ge1(txd2), dev(oen)
mpp30 30 gpio, ge1(txd2), dev(oe)
mpp31 31 gpio, ge1(txd3), dev(ale1)
mpp32 32 gpio, ge1(txctl), dev(wen0)
mpp33 33 gpio, m(decc_err), dev(ad3)
mpp32 32 gpio, ge1(txctl), dev(we0)
mpp33 33 gpio, dram(deccerr), dev(ad3)
mpp34 34 gpio, dev(ad1)
mpp35 35 gpio, ref(clk_out1), dev(a1)
mpp36 36 gpio, ptp(trig_gen), dev(a0)
mpp36 36 gpio, ptp(trig), dev(a0)
mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0)
mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
mpp57 57 gpio, spi1(sck), sd0(clk)
mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3]
mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd)
mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd)
mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2]
mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq)
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq)
mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd)
mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig)
mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk)
mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq)
mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3)
mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd)
mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
[1]: only available on 88F6820 and 88F6828
[2]: only available on 88F6828

84
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
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@ -4,8 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl"
depending on the specific variant of the SoC being used.
- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
"marvell,88f6928-pinctrl" depending on the specific variant of the
SoC being used.
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
@ -24,55 +25,60 @@ mpp6 6 gpio, dev(cs3), xsmi(mdio)
mpp7 7 gpio, dev(ad9), xsmi(mdc)
mpp8 8 gpio, dev(ad10), ptp(trig)
mpp9 9 gpio, dev(ad11), ptp(clk)
mpp10 10 gpio, dev(ad12), ptp(event)
mpp10 10 gpio, dev(ad12), ptp(evreq)
mpp11 11 gpio, dev(ad13), led(clk)
mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb)
mpp13 13 gpio, dev(ad15), led(data)
mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd)
mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data)
mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd)
mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda)
mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio)
mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck)
mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda)
mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc)
mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0)
mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda)
mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs),
sata1(prsnt) [1], ge(rxd0)
mpp22 22 gpio, spi0(mosi), dev(ad0)
mpp23 23 gpio, spi0(sck), dev(ad2)
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn)
mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0)
mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1)
mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout)
mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0)
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout)
mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0)
mpp29 29 gpio, dev(ale0), ge(txd1)
mpp30 30 gpio, dev(oen), ge(txd2)
mpp30 30 gpio, dev(oe), ge(txd2)
mpp31 31 gpio, dev(ale1), ge(txd3)
mpp32 32 gpio, dev(wen0), ge(txctl)
mpp33 33 gpio, m(decc), dev(ad3)
mpp32 32 gpio, dev(we0), ge(txctl)
mpp33 33 gpio, dram(deccerr), dev(ad3)
mpp34 34 gpio, dev(ad1)
mpp35 35 gpio, ref(clk), dev(a1)
mpp36 36 gpio, dev(a0)
mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk)
mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1)
mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2)
mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3)
mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl)
mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk)
mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1)
mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2)
mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3)
mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl)
mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1)
mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk)
mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2],
sata3(prsnt) [2], led(clk)
mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd)
mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)
mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data)
mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd)
mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd)
mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd)
mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd)
mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck)
mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda)
mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd)
mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd)
mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd)
mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd)
mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd)
mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2)
mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2],
sata3(prsnt) [2], led(data)
mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd)
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2],
audio(lrclk) [2], sd0(d5), ua2(rxd)
mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd)
mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd)
mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck)
mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda)
mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd)
mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd)
mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd)
mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
[1]: only available on 88F6928
[1]: only available on 88F6925/88F6928
[2]: only available on 88F6928

80
Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
View File

@ -18,7 +18,7 @@ only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, ge0(txclko), lcd(d0)
mpp0 0 gpio, ge0(txclkout), lcd(d0)
mpp1 1 gpio, ge0(txd0), lcd(d1)
mpp2 2 gpio, ge0(txd1), lcd(d2)
mpp3 3 gpio, ge0(txd2), lcd(d3)
@ -30,49 +30,50 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8)
mpp9 9 gpio, ge0(rxd3), lcd(d9)
mpp10 10 gpio, ge0(rxctl), lcd(d10)
mpp11 11 gpio, ge0(rxclk), lcd(d11)
mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12)
mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13)
mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15)
mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16)
mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16)
mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat)
mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst)
mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk)
mpp26 26 gpio, lcd(clk), tdm(fsync)
mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
mpp30 30 gpio, tdm(int1), sd0(clk)
mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
mpp31 31 gpio, tdm(int2), sd0(cmd)
mpp32 32 gpio, tdm(int3), sd0(d0)
mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl)
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr)
mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
mpp36 36 gpio, spi(mosi)
mpp37 37 gpio, spi(miso)
mpp38 38 gpio, spi(sck)
mpp39 39 gpio, spi(cs0)
mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
pcie(clkreq0)
mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
pcie(clkreq1)
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
vdd(cpu0-pd)
mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
vdd(cpu2-3-pd){1}
mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
mem(bat)
mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
ref(clkout)
mpp48 48 gpio, tclk, dev(burst/last)
mpp36 36 gpio, spi0(mosi)
mpp37 37 gpio, spi0(miso)
mpp38 38 gpio, spi0(sck)
mpp39 39 gpio, spi0(cs0)
mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
spi1(cs1)
mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
pcie(clkreq1), spi1(cs2)
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer)
mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout),
spi1(cs3)
mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2),
dram(bat), spi1(cs4)
mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt),
spi1(cs5), dram(vttctrl)
mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt),
spi1(cs6)
mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3),
ref(clkout), spi1(cs7)
mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb)
* Marvell Armada XP (mv78260 and mv78460 only)
@ -84,9 +85,9 @@ mpp51 51 gpio, dev(ad16)
mpp52 52 gpio, dev(ad17)
mpp53 53 gpio, dev(ad18)
mpp54 54 gpio, dev(ad19)
mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
mpp55 55 gpio, dev(ad20)
mpp56 56 gpio, dev(ad21)
mpp57 57 gpio, dev(ad22)
mpp58 58 gpio, dev(ad23)
mpp59 59 gpio, dev(ad24)
mpp60 60 gpio, dev(ad25)
@ -96,6 +97,3 @@ mpp63 63 gpio, dev(ad28)
mpp64 64 gpio, dev(ad29)
mpp65 65 gpio, dev(ad30)
mpp66 66 gpio, dev(ad31)
Notes:
* {1} vdd(cpu2-3-pd) only available on mv78460.

57
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt Normal file
View File

@ -0,0 +1,57 @@
NXP LPC18xx/43xx SCU pin controller Device Tree Bindings
--------------------------------------------------------
Required properties:
- compatible : Should be "nxp,lpc1850-scu"
- reg : Address and length of the register set for the device
- clocks : Clock specifier (see clock bindings for details)
The lpc1850-scu driver uses the generic pin multiplexing and generic pin
configuration documented in pinctrl-bindings.txt.
The following generic nodes are supported:
- function
- pins
- bias-disable
- bias-pull-up
- bias-pull-down
- drive-strength
- input-enable
- input-disable
- input-schmitt-enable
- input-schmitt-disable
- slew-rate
Not all pins support all properties so either refer to the NXP 1850/4350
user manual or the pin table in the pinctrl-lpc18xx driver for supported
pin properties.
Example:
pinctrl: pinctrl@40086000 {
compatible = "nxp,lpc1850-scu";
reg = <0x40086000 0x1000>;
clocks = <&ccu1 CLK_CPU_SCU>;
i2c0_pins: i2c0-pins {
i2c0_pins_cfg {
pins = "i2c0_scl", "i2c0_sda";
function = "i2c0";
input-enable;
};
};
uart0_pins: uart0-pins {
uart0_rx_cfg {
pins = "pf_11";
function = "uart0";
bias-disable;
input-enable;
};
uart0_tx_cfg {
pins = "pf_10";
function = "uart0";
bias-disable;
};
};
};

109
Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt Normal file
View File

@ -0,0 +1,109 @@
CSR SiRFatlas7 pinmux controller
Required properties:
- compatible : "sirf,atlas7-ioc"
- reg : Address range of the pinctrl registers
For example, pinctrl might have properties like the following:
pinctrl: ioc@18880000 {
compatible = "sirf,atlas7-ioc";
reg = <0x18880000 0x1000>;
a_ac97_pmx: ac97@0 {
ac97 {
groups = "audio_ac97_grp";
function = "audio_ac97";
};
};
...
sd2_pmx: sd2@0 {
sd2 {
groups = "sd2_grp0";
function = "sd2";
};
};
...
sample0_cfg: sample0@0 {
sample0 {
pins = "ldd_0", "ldd_1";
bias-pull-up;
};
};
sample1_cfg: sample1@0 {
sample1 {
pins = "ldd_2", "ldd_3";
input-schmitt-enable;
};
};
sample2_cfg: sample2@0 {
sample2 {
groups = "uart4_nopause_grp";
bias-pull-down;
};
};
sample3_cfg: sample3@0 {
sample3 {
pins = "ldd_4", "ldd_5";
drive-strength = <2>;
};
};
};
Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.
SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes.
Each of these subnodes represents some desired configuration for a group of pins.
Required subnode-properties:
- groups : An array of strings. Each string contains the name of a group.
- function: A string containing the name of the function to mux to the
group.
Valid values for group and function names can be found from looking at the
group and function arrays in driver files:
drivers/pinctrl/pinctrl-sirf.c
For example, pinctrl might have subnodes like the following:
sd0_pmx: sd0@0 {
sd0 {
groups = "sd0_grp";
function = "sd0";
};
};
sd1_pmx0: sd1@0 {
sd1 {
groups = "sd1_grp0";
function = "sd1_m0";
};
};
sd1_pmx1: sd1@1 {
sd1 {
groups = "sd1_grp1";
function = "sd1_m1";
};
};
For a specific board, if it wants to use sd1,
it can add the following to its board-specific .dts file.
sd1: sd@0x12340000 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_pmx0>;
}
or
sd1: sd@0x12340000 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_pmx1>;
}

9
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
View File

@ -3,9 +3,11 @@
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be either of the following.
- compatible: value should be one of the following.
(a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
(b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
(c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
(d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.
@ -24,6 +26,9 @@ Required properties:
Only the following flags are supported:
0 - GPIO_ACTIVE_HIGH
1 - GPIO_ACTIVE_LOW
Optional properties:
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
- reg: physicall address base for EINT registers
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.

90
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt Normal file
View File

@ -0,0 +1,90 @@
Qualcomm MSM8660 TLMM block
Required properties:
- compatible: "qcom,msm8660-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for pins are:
gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data
Valid values for function are:
gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b,
gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n,
gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm,
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8660-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi12_uart>;
gsbi12_uart: gsbi12-uart {
mux {
pins = "gpio117", "gpio118";
function = "gsbi12";
};
tx {
pins = "gpio118";
drive-strength = <8>;
bias-disable;
};
rx {
pins = "gpio117";
drive-strength = <2>;
bias-pull-up;
};
};
};

4
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
View File

@ -16,7 +16,9 @@ Required Properties:
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin

5
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@ -21,14 +21,15 @@ defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3288-pinctrl"
"rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"
Optional properties for iomux controller:
- rockchip,pmu: phandle referencing a syscon providing the pmu registers
as some SoCs carry parts of the iomux controller registers there.
Required for at least rk3188 and rk3288.
Required for at least rk3188 and rk3288. On the rk3368 this should
point to the PMUGRF syscon.
Deprecated properties for iomux controller:
- reg: first element is the general register space of the iomux controller

7
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
View File

@ -45,8 +45,9 @@ to specify in a pinconf subnode:
Valid values for groups are:
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp,
spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
@ -59,7 +60,7 @@ to specify in a pinconf subnode:
Valid values for function are:
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1

11
Documentation/pinctrl.txt
View File

@ -714,6 +714,7 @@ static struct pinmux_ops foo_pmxops = {
.get_function_name = foo_get_fname,
.get_function_groups = foo_get_groups,
.set_mux = foo_set_mux,
.strict = true,
};
/* Pinmux operations are handled by some pin controller */
@ -830,6 +831,11 @@ separate memory range only intended for GPIO driving, and the register
range dealing with pin config and pin multiplexing get placed into a
different memory range and a separate section of the data sheet.
A flag "strict" in struct pinctrl_desc is available to check and deny
simultaneous access to the same pin from GPIO and pin multiplexing
consumers on hardware of this type. The pinctrl driver should set this flag
accordingly.
(B)
pin config
@ -850,6 +856,11 @@ possible that the GPIO, pin config and pin multiplex registers are placed into
the same memory range and the same section of the data sheet, although that
need not be the case.
In some pin controllers, although the physical pins are designed in the same
way as (B), the GPIO function still can't be enabled at the same time as the
peripheral functions. So again the "strict" flag should be set, denying
simultaneous activation by GPIO and other muxed in devices.
From a kernel point of view, however, these are different aspects of the
hardware and shall be put into different subsystems:

2
drivers/gpio/gpio-bcm-kona.c
View File

@ -540,7 +540,7 @@ static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
irq_set_chip_data(irq, NULL);
}
static struct irq_domain_ops bcm_kona_irq_ops = {
static const struct irq_domain_ops bcm_kona_irq_ops = {
.map = bcm_kona_gpio_irq_map,
.unmap = bcm_kona_gpio_irq_unmap,
.xlate = irq_domain_xlate_twocell,

2
drivers/gpio/gpio-em.c
View File

@ -266,7 +266,7 @@ static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
return 0;
}
static struct irq_domain_ops em_gio_irq_domain_ops = {
static const struct irq_domain_ops em_gio_irq_domain_ops = {
.map = em_gio_irq_domain_map,
.xlate = irq_domain_xlate_twocell,
};

2
drivers/gpio/gpio-grgpio.c
View File

@ -332,7 +332,7 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
spin_unlock_irqrestore(&priv->bgc.lock, flags);
}
static struct irq_domain_ops grgpio_irq_domain_ops = {
static const struct irq_domain_ops grgpio_irq_domain_ops = {
.map = grgpio_irq_map,
.unmap = grgpio_irq_unmap,
};

2
drivers/gpio/gpio-mpc8xxx.c
View File

@ -329,7 +329,7 @@ static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
return 0;
}
static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
.map = mpc8xxx_gpio_irq_map,
.xlate = irq_domain_xlate_twocell,
};

2
drivers/gpio/gpio-sa1100.c
View File

@ -160,7 +160,7 @@ static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
return 0;
}
static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
.map = sa1100_gpio_irqdomain_map,
.xlate = irq_domain_xlate_onetwocell,
};

2
drivers/gpio/gpio-sodaville.c
View File

@ -125,7 +125,7 @@ static int sdv_xlate(struct irq_domain *h, struct device_node *node,
return 0;
}
static struct irq_domain_ops irq_domain_sdv_ops = {
static const struct irq_domain_ops irq_domain_sdv_ops = {
.xlate = sdv_xlate,
};

19
drivers/pinctrl/Kconfig
View File

@ -88,6 +88,15 @@ config PINCTRL_LANTIQ
select PINMUX
select PINCONF
config PINCTRL_LPC18XX
bool "NXP LPC18XX/43XX SCU pinctrl driver"
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
default ARCH_LPC18XX
select PINMUX
select GENERIC_PINCONF
help
Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
config PINCTRL_FALCON
bool
depends on SOC_FALCON
@ -123,8 +132,18 @@ config PINCTRL_SIRF
bool "CSR SiRFprimaII pin controller driver"
depends on ARCH_SIRF
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
config PINCTRL_PISTACHIO
def_bool y if MACH_PISTACHIO
depends on GPIOLIB
select PINMUX
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
select OF_GPIO
config PINCTRL_ST
bool
depends on OF

2
drivers/pinctrl/Makefile
View File

@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
@ -34,6 +35,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o

4
drivers/pinctrl/bcm/pinctrl-bcm281xx.c
View File

@ -1425,9 +1425,9 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
pctl = pinctrl_register(&bcm281xx_pinctrl_desc,
&pdev->dev,
pdata);
if (!pctl) {
if (IS_ERR(pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return -ENODEV;
return PTR_ERR(pctl);
}
platform_set_drvdata(pdev, pdata);

4
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -1036,9 +1036,9 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
}
pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
if (!pc->pctl_dev) {
if (IS_ERR(pc->pctl_dev)) {
gpiochip_remove(&pc->gpio_chip);
return -EINVAL;
return PTR_ERR(pc->pctl_dev);
}
pc->gpio_range = bcm2835_pinctrl_gpio_range;

8
drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
View File

@ -38,7 +38,7 @@
#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00
#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04
#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08
#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c
#define CYGNUS_GPIO_INT_TYPE_OFFSET 0x0c
#define CYGNUS_GPIO_INT_DE_OFFSET 0x10
#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14
#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18
@ -264,7 +264,7 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type)
}
spin_lock_irqsave(&chip->lock, flags);
cygnus_set_bit(chip, CYGNUS_GPIO_IN_TYPE_OFFSET, gpio,
cygnus_set_bit(chip, CYGNUS_GPIO_INT_TYPE_OFFSET, gpio,
level_triggered);
cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge);
cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio,
@ -750,9 +750,9 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip)
pctldesc->confops = &cygnus_pconf_ops;
chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
if (!chip->pctl) {
if (IS_ERR(chip->pctl)) {
dev_err(chip->dev, "unable to register pinctrl device\n");
return -EINVAL;
return PTR_ERR(chip->pctl);
}
return 0;

4
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
View File

@ -989,9 +989,9 @@ static int cygnus_pinmux_probe(struct platform_device *pdev)
pinctrl->pctl = pinctrl_register(&cygnus_pinctrl_desc, &pdev->dev,
pinctrl);
if (!pinctrl->pctl) {
if (IS_ERR(pinctrl->pctl)) {
dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");
return -EINVAL;
return PTR_ERR(pinctrl->pctl);
}
return 0;

18
drivers/pinctrl/berlin/berlin-bg2.c
View File

@ -20,24 +20,24 @@
static const struct berlin_desc_group berlin2_soc_pinctrl_groups[] = {
/* G */
BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "usb1")),
BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s0")),
BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s1")),
BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK/SDI/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "pwm")),
BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08,
@ -163,15 +163,15 @@ static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = {
/* GSM */
BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "twsi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2")),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS2n/SS3n */
BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */
@ -187,7 +187,7 @@ static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = {
BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")),
BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* CLK/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "clki")),
BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),

8
drivers/pinctrl/berlin/berlin-bg2cd.c
View File

@ -68,17 +68,17 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10,
BERLIN_PINCTRL_FUNCTION(0x0, "ss0"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */
BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")),
BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a,
BERLIN_PINCTRL_FUNCTION(0x0, "usb1"),

16
drivers/pinctrl/berlin/berlin-bg2q.c
View File

@ -59,21 +59,21 @@ static const struct berlin_desc_group berlin2q_soc_pinctrl_groups[] = {
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "eddc")),
BERLIN_PINCTRL_GROUP("G8", 0x18, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK/SDI/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G9", 0x18, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n/SS1n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
BERLIN_PINCTRL_GROUP("G10", 0x1c, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
BERLIN_PINCTRL_GROUP("G11", 0x1c, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s1"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
@ -301,19 +301,19 @@ static const struct berlin_desc_group berlin2q_sysmgr_pinctrl_groups[] = {
/* GSM */
BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n/SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* CLK/SDO */
BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x1, 0x08,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),

4
drivers/pinctrl/berlin/berlin.c
View File

@ -320,9 +320,9 @@ int berlin_pinctrl_probe(struct platform_device *pdev,
}
pctrl->pctrl_dev = pinctrl_register(&berlin_pctrl_desc, dev, pctrl);
if (!pctrl->pctrl_dev) {
if (IS_ERR(pctrl->pctrl_dev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(pctrl->pctrl_dev);
}
return 0;

21
drivers/pinctrl/core.c
View File

@ -558,7 +558,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
}
/**
* pinctrl_request_gpio() - request a single pin to be used in as GPIO
* pinctrl_request_gpio() - request a single pin to be used as GPIO
* @gpio: the GPIO pin number from the GPIO subsystem number space
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
@ -1115,7 +1115,7 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
int i, ret;
struct pinctrl_maps *maps_node;
pr_debug("add %d pinmux maps\n", num_maps);
pr_debug("add %u pinctrl maps\n", num_maps);
/* First sanity check the new mapping */
for (i = 0; i < num_maps; i++) {
@ -1704,14 +1704,14 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
int ret;
if (!pctldesc)
return NULL;
return ERR_PTR(-EINVAL);
if (!pctldesc->name)
return NULL;
return ERR_PTR(-EINVAL);
pctldev = kzalloc(sizeof(*pctldev), GFP_KERNEL);
if (pctldev == NULL) {
dev_err(dev, "failed to alloc struct pinctrl_dev\n");
return NULL;
return ERR_PTR(-ENOMEM);
}
/* Initialize pin control device struct */
@ -1724,20 +1724,23 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
mutex_init(&pctldev->mutex);
/* check core ops for sanity */
if (pinctrl_check_ops(pctldev)) {
ret = pinctrl_check_ops(pctldev);
if (ret) {
dev_err(dev, "pinctrl ops lacks necessary functions\n");
goto out_err;
}
/* If we're implementing pinmuxing, check the ops for sanity */
if (pctldesc->pmxops) {
if (pinmux_check_ops(pctldev))
ret = pinmux_check_ops(pctldev);
if (ret)
goto out_err;
}
/* If we're implementing pinconfig, check the ops for sanity */
if (pctldesc->confops) {
if (pinconf_check_ops(pctldev))
ret = pinconf_check_ops(pctldev);
if (ret)
goto out_err;
}
@ -1783,7 +1786,7 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
out_err:
mutex_destroy(&pctldev->mutex);
kfree(pctldev);
return NULL;
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(pinctrl_register);

7
drivers/pinctrl/freescale/Kconfig
View File

@ -87,6 +87,13 @@ config PINCTRL_IMX6SX
help
Say Y here to enable the imx6sx pinctrl driver
config PINCTRL_IMX7D
bool "IMX7D pinctrl driver"
depends on SOC_IMX7D
select PINCTRL_IMX
help
Say Y here to enable the imx7d pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610

1
drivers/pinctrl/freescale/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o

59
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -606,6 +606,29 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
return 0;
}
/*
* Check if the DT contains pins in the direct child nodes. This indicates the
* newer DT format to store pins. This function returns true if the first found
* fsl,pins property is in a child of np. Otherwise false is returned.
*/
static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
{
struct device_node *function_np;
struct device_node *pinctrl_np;
for_each_child_of_node(np, function_np) {
if (of_property_read_bool(function_np, "fsl,pins"))
return true;
for_each_child_of_node(function_np, pinctrl_np) {
if (of_property_read_bool(pinctrl_np, "fsl,pins"))
return false;
}
}
return true;
}
static int imx_pinctrl_probe_dt(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
@ -613,14 +636,20 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
struct device_node *child;
u32 nfuncs = 0;
u32 i = 0;
bool flat_funcs;
if (!np)
return -ENODEV;
nfuncs = of_get_child_count(np);
if (nfuncs <= 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
if (flat_funcs) {
nfuncs = 1;
} else {
nfuncs = of_get_child_count(np);
if (nfuncs <= 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
}
}
info->nfunctions = nfuncs;
@ -629,16 +658,24 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
if (!info->functions)
return -ENOMEM;
info->ngroups = 0;
for_each_child_of_node(np, child)
info->ngroups += of_get_child_count(child);
if (flat_funcs) {
info->ngroups = of_get_child_count(np);
} else {
info->ngroups = 0;
for_each_child_of_node(np, child)
info->ngroups += of_get_child_count(child);
}
info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
GFP_KERNEL);
if (!info->groups)
return -ENOMEM;
for_each_child_of_node(np, child)
imx_pinctrl_parse_functions(child, info, i++);
if (flat_funcs) {
imx_pinctrl_parse_functions(np, info, 0);
} else {
for_each_child_of_node(np, child)
imx_pinctrl_parse_functions(child, info, i++);
}
return 0;
}
@ -690,9 +727,9 @@ int imx_pinctrl_probe(struct platform_device *pdev,
ipctl->dev = info->dev;
platform_set_drvdata(pdev, ipctl);
ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
if (!ipctl->pctl) {
if (IS_ERR(ipctl->pctl)) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return -EINVAL;
return PTR_ERR(ipctl->pctl);
}
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");

4
drivers/pinctrl/freescale/pinctrl-imx1-core.c
View File

@ -633,9 +633,9 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev,
ipctl->dev = info->dev;
platform_set_drvdata(pdev, ipctl);
ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
if (!ipctl->pctl) {
if (IS_ERR(ipctl->pctl)) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return -EINVAL;
return PTR_ERR(ipctl->pctl);
}
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

384
drivers/pinctrl/freescale/pinctrl-imx7d.c Normal file
View File

@ -0,0 +1,384 @@
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx7d_pads {
MX7D_PAD_RESERVE0 = 0,
MX7D_PAD_RESERVE1 = 1,
MX7D_PAD_RESERVE2 = 2,
MX7D_PAD_RESERVE3 = 3,
MX7D_PAD_RESERVE4 = 4,
MX7D_PAD_GPIO1_IO08 = 5,
MX7D_PAD_GPIO1_IO09 = 6,
MX7D_PAD_GPIO1_IO10 = 7,
MX7D_PAD_GPIO1_IO11 = 8,
MX7D_PAD_GPIO1_IO12 = 9,
MX7D_PAD_GPIO1_IO13 = 10,
MX7D_PAD_GPIO1_IO14 = 11,
MX7D_PAD_GPIO1_IO15 = 12,
MX7D_PAD_EPDC_DATA00 = 13,
MX7D_PAD_EPDC_DATA01 = 14,
MX7D_PAD_EPDC_DATA02 = 15,
MX7D_PAD_EPDC_DATA03 = 16,
MX7D_PAD_EPDC_DATA04 = 17,
MX7D_PAD_EPDC_DATA05 = 18,
MX7D_PAD_EPDC_DATA06 = 19,
MX7D_PAD_EPDC_DATA07 = 20,
MX7D_PAD_EPDC_DATA08 = 21,
MX7D_PAD_EPDC_DATA09 = 22,
MX7D_PAD_EPDC_DATA10 = 23,
MX7D_PAD_EPDC_DATA11 = 24,
MX7D_PAD_EPDC_DATA12 = 25,
MX7D_PAD_EPDC_DATA13 = 26,
MX7D_PAD_EPDC_DATA14 = 27,
MX7D_PAD_EPDC_DATA15 = 28,
MX7D_PAD_EPDC_SDCLK = 29,
MX7D_PAD_EPDC_SDLE = 30,
MX7D_PAD_EPDC_SDOE = 31,
MX7D_PAD_EPDC_SDSHR = 32,
MX7D_PAD_EPDC_SDCE0 = 33,
MX7D_PAD_EPDC_SDCE1 = 34,
MX7D_PAD_EPDC_SDCE2 = 35,
MX7D_PAD_EPDC_SDCE3 = 36,
MX7D_PAD_EPDC_GDCLK = 37,
MX7D_PAD_EPDC_GDOE = 38,
MX7D_PAD_EPDC_GDRL = 39,
MX7D_PAD_EPDC_GDSP = 40,
MX7D_PAD_EPDC_BDR0 = 41,
MX7D_PAD_EPDC_BDR1 = 42,
MX7D_PAD_EPDC_PWR_COM = 43,
MX7D_PAD_EPDC_PWR_STAT = 44,
MX7D_PAD_LCD_CLK = 45,
MX7D_PAD_LCD_ENABLE = 46,
MX7D_PAD_LCD_HSYNC = 47,
MX7D_PAD_LCD_VSYNC = 48,
MX7D_PAD_LCD_RESET = 49,
MX7D_PAD_LCD_DATA00 = 50,
MX7D_PAD_LCD_DATA01 = 51,
MX7D_PAD_LCD_DATA02 = 52,
MX7D_PAD_LCD_DATA03 = 53,
MX7D_PAD_LCD_DATA04 = 54,
MX7D_PAD_LCD_DATA05 = 55,
MX7D_PAD_LCD_DATA06 = 56,
MX7D_PAD_LCD_DATA07 = 57,
MX7D_PAD_LCD_DATA08 = 58,
MX7D_PAD_LCD_DATA09 = 59,
MX7D_PAD_LCD_DATA10 = 60,
MX7D_PAD_LCD_DATA11 = 61,
MX7D_PAD_LCD_DATA12 = 62,
MX7D_PAD_LCD_DATA13 = 63,
MX7D_PAD_LCD_DATA14 = 64,
MX7D_PAD_LCD_DATA15 = 65,
MX7D_PAD_LCD_DATA16 = 66,
MX7D_PAD_LCD_DATA17 = 67,
MX7D_PAD_LCD_DATA18 = 68,
MX7D_PAD_LCD_DATA19 = 69,
MX7D_PAD_LCD_DATA20 = 70,
MX7D_PAD_LCD_DATA21 = 71,
MX7D_PAD_LCD_DATA22 = 72,
MX7D_PAD_LCD_DATA23 = 73,
MX7D_PAD_UART1_RX_DATA = 74,
MX7D_PAD_UART1_TX_DATA = 75,
MX7D_PAD_UART2_RX_DATA = 76,
MX7D_PAD_UART2_TX_DATA = 77,
MX7D_PAD_UART3_RX_DATA = 78,
MX7D_PAD_UART3_TX_DATA = 79,
MX7D_PAD_UART3_RTS_B = 80,
MX7D_PAD_UART3_CTS_B = 81,
MX7D_PAD_I2C1_SCL = 82,
MX7D_PAD_I2C1_SDA = 83,
MX7D_PAD_I2C2_SCL = 84,
MX7D_PAD_I2C2_SDA = 85,
MX7D_PAD_I2C3_SCL = 86,
MX7D_PAD_I2C3_SDA = 87,
MX7D_PAD_I2C4_SCL = 88,
MX7D_PAD_I2C4_SDA = 89,
MX7D_PAD_ECSPI1_SCLK = 90,
MX7D_PAD_ECSPI1_MOSI = 91,
MX7D_PAD_ECSPI1_MISO = 92,
MX7D_PAD_ECSPI1_SS0 = 93,
MX7D_PAD_ECSPI2_SCLK = 94,
MX7D_PAD_ECSPI2_MOSI = 95,
MX7D_PAD_ECSPI2_MISO = 96,
MX7D_PAD_ECSPI2_SS0 = 97,
MX7D_PAD_SD1_CD_B = 98,
MX7D_PAD_SD1_WP = 99,
MX7D_PAD_SD1_RESET_B = 100,
MX7D_PAD_SD1_CLK = 101,
MX7D_PAD_SD1_CMD = 102,
MX7D_PAD_SD1_DATA0 = 103,
MX7D_PAD_SD1_DATA1 = 104,
MX7D_PAD_SD1_DATA2 = 105,
MX7D_PAD_SD1_DATA3 = 106,
MX7D_PAD_SD2_CD_B = 107,
MX7D_PAD_SD2_WP = 108,
MX7D_PAD_SD2_RESET_B = 109,
MX7D_PAD_SD2_CLK = 110,
MX7D_PAD_SD2_CMD = 111,
MX7D_PAD_SD2_DATA0 = 112,
MX7D_PAD_SD2_DATA1 = 113,
MX7D_PAD_SD2_DATA2 = 114,
MX7D_PAD_SD2_DATA3 = 115,
MX7D_PAD_SD3_CLK = 116,
MX7D_PAD_SD3_CMD = 117,
MX7D_PAD_SD3_DATA0 = 118,
MX7D_PAD_SD3_DATA1 = 119,
MX7D_PAD_SD3_DATA2 = 120,
MX7D_PAD_SD3_DATA3 = 121,
MX7D_PAD_SD3_DATA4 = 122,
MX7D_PAD_SD3_DATA5 = 123,
MX7D_PAD_SD3_DATA6 = 124,
MX7D_PAD_SD3_DATA7 = 125,
MX7D_PAD_SD3_STROBE = 126,
MX7D_PAD_SD3_RESET_B = 127,
MX7D_PAD_SAI1_RX_DATA = 128,
MX7D_PAD_SAI1_TX_BCLK = 129,
MX7D_PAD_SAI1_TX_SYNC = 130,
MX7D_PAD_SAI1_TX_DATA = 131,
MX7D_PAD_SAI1_RX_SYNC = 132,
MX7D_PAD_SAI1_RX_BCLK = 133,
MX7D_PAD_SAI1_MCLK = 134,
MX7D_PAD_SAI2_TX_SYNC = 135,
MX7D_PAD_SAI2_TX_BCLK = 136,
MX7D_PAD_SAI2_RX_DATA = 137,
MX7D_PAD_SAI2_TX_DATA = 138,
MX7D_PAD_ENET1_RGMII_RD0 = 139,
MX7D_PAD_ENET1_RGMII_RD1 = 140,
MX7D_PAD_ENET1_RGMII_RD2 = 141,
MX7D_PAD_ENET1_RGMII_RD3 = 142,
MX7D_PAD_ENET1_RGMII_RX_CTL = 143,
MX7D_PAD_ENET1_RGMII_RXC = 144,
MX7D_PAD_ENET1_RGMII_TD0 = 145,
MX7D_PAD_ENET1_RGMII_TD1 = 146,
MX7D_PAD_ENET1_RGMII_TD2 = 147,
MX7D_PAD_ENET1_RGMII_TD3 = 148,
MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
MX7D_PAD_ENET1_RGMII_TXC = 150,
MX7D_PAD_ENET1_TX_CLK = 151,
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23),
IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B),
IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
};
static struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
{ /* sentinel */ }
};
static int imx7d_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct imx_pinctrl_soc_info *pinctrl_info;
match = of_match_device(imx7d_pinctrl_of_match, &pdev->dev);
if (!match)
return -ENODEV;
pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
return imx_pinctrl_probe(pdev, pinctrl_info);
}
static struct platform_driver imx7d_pinctrl_driver = {
.driver = {
.name = "imx7d-pinctrl",
.of_match_table = of_match_ptr(imx7d_pinctrl_of_match),
},
.probe = imx7d_pinctrl_probe,
.remove = imx_pinctrl_remove,
};
static int __init imx7d_pinctrl_init(void)
{
return platform_driver_register(&imx7d_pinctrl_driver);
}
arch_initcall(imx7d_pinctrl_init);
static void __exit imx7d_pinctrl_exit(void)
{
platform_driver_unregister(&imx7d_pinctrl_driver);
}
module_exit(imx7d_pinctrl_exit);
MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
MODULE_DESCRIPTION("Freescale imx7d pinctrl driver");
MODULE_LICENSE("GPL v2");

4
drivers/pinctrl/freescale/pinctrl-mxs.c
View File

@ -540,9 +540,9 @@ int mxs_pinctrl_probe(struct platform_device *pdev,
}
d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
if (!d->pctl) {
if (IS_ERR(d->pctl)) {
dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
ret = -EINVAL;
ret = PTR_ERR(d->pctl);
goto err;
}

4
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1533,9 +1533,9 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
pctrl->pctldesc.npins = pctrl->community->npins;
pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
if (!pctrl->pctldev) {
if (IS_ERR(pctrl->pctldev)) {
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pctrl->pctldev);
}
ret = chv_gpio_probe(pctrl, irq);

4
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -1021,9 +1021,9 @@ int intel_pinctrl_probe(struct platform_device *pdev,
pctrl->pctldesc.npins = pctrl->soc->npins;
pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
if (!pctrl->pctldev) {
if (IS_ERR(pctrl->pctldev)) {
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pctrl->pctldev);
}
ret = intel_gpio_probe(pctrl, irq);

263
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -284,8 +284,271 @@ static const struct intel_pinctrl_soc_data sptlp_soc_data = {
.ncommunities = ARRAY_SIZE(sptlp_communities),
};
/* Sunrisepoint-H */
static const struct pinctrl_pin_desc spth_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "RCINB"),
PINCTRL_PIN(1, "LAD_0"),
PINCTRL_PIN(2, "LAD_1"),
PINCTRL_PIN(3, "LAD_2"),
PINCTRL_PIN(4, "LAD_3"),
PINCTRL_PIN(5, "LFRAMEB"),
PINCTRL_PIN(6, "SERIQ"),
PINCTRL_PIN(7, "PIRQAB"),
PINCTRL_PIN(8, "CLKRUNB"),
PINCTRL_PIN(9, "CLKOUT_LPC_0"),
PINCTRL_PIN(10, "CLKOUT_LPC_1"),
PINCTRL_PIN(11, "PMEB"),
PINCTRL_PIN(12, "BM_BUSYB"),
PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
PINCTRL_PIN(14, "SUS_STATB"),
PINCTRL_PIN(15, "SUSACKB"),
PINCTRL_PIN(16, "CLKOUT_48"),
PINCTRL_PIN(17, "ISH_GP_7"),
PINCTRL_PIN(18, "ISH_GP_0"),
PINCTRL_PIN(19, "ISH_GP_1"),
PINCTRL_PIN(20, "ISH_GP_2"),
PINCTRL_PIN(21, "ISH_GP_3"),
PINCTRL_PIN(22, "ISH_GP_4"),
PINCTRL_PIN(23, "ISH_GP_5"),
/* GPP_B */
PINCTRL_PIN(24, "CORE_VID_0"),
PINCTRL_PIN(25, "CORE_VID_1"),
PINCTRL_PIN(26, "VRALERTB"),
PINCTRL_PIN(27, "CPU_GP_2"),
PINCTRL_PIN(28, "CPU_GP_3"),
PINCTRL_PIN(29, "SRCCLKREQB_0"),
PINCTRL_PIN(30, "SRCCLKREQB_1"),
PINCTRL_PIN(31, "SRCCLKREQB_2"),
PINCTRL_PIN(32, "SRCCLKREQB_3"),
PINCTRL_PIN(33, "SRCCLKREQB_4"),
PINCTRL_PIN(34, "SRCCLKREQB_5"),
PINCTRL_PIN(35, "EXT_PWR_GATEB"),
PINCTRL_PIN(36, "SLP_S0B"),
PINCTRL_PIN(37, "PLTRSTB"),
PINCTRL_PIN(38, "SPKR"),
PINCTRL_PIN(39, "GSPI0_CSB"),
PINCTRL_PIN(40, "GSPI0_CLK"),
PINCTRL_PIN(41, "GSPI0_MISO"),
PINCTRL_PIN(42, "GSPI0_MOSI"),
PINCTRL_PIN(43, "GSPI1_CSB"),
PINCTRL_PIN(44, "GSPI1_CLK"),
PINCTRL_PIN(45, "GSPI1_MISO"),
PINCTRL_PIN(46, "GSPI1_MOSI"),
PINCTRL_PIN(47, "SML1ALERTB"),
/* GPP_C */
PINCTRL_PIN(48, "SMBCLK"),
PINCTRL_PIN(49, "SMBDATA"),
PINCTRL_PIN(50, "SMBALERTB"),
PINCTRL_PIN(51, "SML0CLK"),
PINCTRL_PIN(52, "SML0DATA"),
PINCTRL_PIN(53, "SML0ALERTB"),
PINCTRL_PIN(54, "SML1CLK"),
PINCTRL_PIN(55, "SML1DATA"),
PINCTRL_PIN(56, "UART0_RXD"),
PINCTRL_PIN(57, "UART0_TXD"),
PINCTRL_PIN(58, "UART0_RTSB"),
PINCTRL_PIN(59, "UART0_CTSB"),
PINCTRL_PIN(60, "UART1_RXD"),
PINCTRL_PIN(61, "UART1_TXD"),
PINCTRL_PIN(62, "UART1_RTSB"),
PINCTRL_PIN(63, "UART1_CTSB"),
PINCTRL_PIN(64, "I2C0_SDA"),
PINCTRL_PIN(65, "I2C0_SCL"),
PINCTRL_PIN(66, "I2C1_SDA"),
PINCTRL_PIN(67, "I2C1_SCL"),
PINCTRL_PIN(68, "UART2_RXD"),
PINCTRL_PIN(69, "UART2_TXD"),
PINCTRL_PIN(70, "UART2_RTSB"),
PINCTRL_PIN(71, "UART2_CTSB"),
/* GPP_D */
PINCTRL_PIN(72, "SPI1_CSB"),
PINCTRL_PIN(73, "SPI1_CLK"),
PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(76, "ISH_I2C2_SDA"),
PINCTRL_PIN(77, "SSP0_SFRM"),
PINCTRL_PIN(78, "SSP0_TXD"),
PINCTRL_PIN(79, "SSP0_RXD"),
PINCTRL_PIN(80, "SSP0_SCLK"),
PINCTRL_PIN(81, "ISH_SPI_CSB"),
PINCTRL_PIN(82, "ISH_SPI_CLK"),
PINCTRL_PIN(83, "ISH_SPI_MISO"),
PINCTRL_PIN(84, "ISH_SPI_MOSI"),
PINCTRL_PIN(85, "ISH_UART0_RXD"),
PINCTRL_PIN(86, "ISH_UART0_TXD"),
PINCTRL_PIN(87, "ISH_UART0_RTSB"),
PINCTRL_PIN(88, "ISH_UART0_CTSB"),
PINCTRL_PIN(89, "DMIC_CLK_1"),
PINCTRL_PIN(90, "DMIC_DATA_1"),
PINCTRL_PIN(91, "DMIC_CLK_0"),
PINCTRL_PIN(92, "DMIC_DATA_0"),
PINCTRL_PIN(93, "SPI1_IO_2"),
PINCTRL_PIN(94, "SPI1_IO_3"),
PINCTRL_PIN(95, "ISH_I2C2_SCL"),
/* GPP_E */
PINCTRL_PIN(96, "SATAXPCIE_0"),
PINCTRL_PIN(97, "SATAXPCIE_1"),
PINCTRL_PIN(98, "SATAXPCIE_2"),
PINCTRL_PIN(99, "CPU_GP_0"),
PINCTRL_PIN(100, "SATA_DEVSLP_0"),
PINCTRL_PIN(101, "SATA_DEVSLP_1"),
PINCTRL_PIN(102, "SATA_DEVSLP_2"),
PINCTRL_PIN(103, "CPU_GP_1"),
PINCTRL_PIN(104, "SATA_LEDB"),
PINCTRL_PIN(105, "USB2_OCB_0"),
PINCTRL_PIN(106, "USB2_OCB_1"),
PINCTRL_PIN(107, "USB2_OCB_2"),
PINCTRL_PIN(108, "USB2_OCB_3"),
/* GPP_F */
PINCTRL_PIN(109, "SATAXPCIE_3"),
PINCTRL_PIN(110, "SATAXPCIE_4"),
PINCTRL_PIN(111, "SATAXPCIE_5"),
PINCTRL_PIN(112, "SATAXPCIE_6"),
PINCTRL_PIN(113, "SATAXPCIE_7"),
PINCTRL_PIN(114, "SATA_DEVSLP_3"),
PINCTRL_PIN(115, "SATA_DEVSLP_4"),
PINCTRL_PIN(116, "SATA_DEVSLP_5"),
PINCTRL_PIN(117, "SATA_DEVSLP_6"),
PINCTRL_PIN(118, "SATA_DEVSLP_7"),
PINCTRL_PIN(119, "SATA_SCLOCK"),
PINCTRL_PIN(120, "SATA_SLOAD"),
PINCTRL_PIN(121, "SATA_SDATAOUT1"),
PINCTRL_PIN(122, "SATA_SDATAOUT0"),
PINCTRL_PIN(123, "GPP_F_14"),
PINCTRL_PIN(124, "USB_OCB_4"),
PINCTRL_PIN(125, "USB_OCB_5"),
PINCTRL_PIN(126, "USB_OCB_6"),
PINCTRL_PIN(127, "USB_OCB_7"),
PINCTRL_PIN(128, "L_VDDEN"),
PINCTRL_PIN(129, "L_BKLTEN"),
PINCTRL_PIN(130, "L_BKLTCTL"),
PINCTRL_PIN(131, "GPP_F_22"),
PINCTRL_PIN(132, "GPP_F_23"),
/* GPP_G */
PINCTRL_PIN(133, "FAN_TACH_0"),
PINCTRL_PIN(134, "FAN_TACH_1"),
PINCTRL_PIN(135, "FAN_TACH_2"),
PINCTRL_PIN(136, "FAN_TACH_3"),
PINCTRL_PIN(137, "FAN_TACH_4"),
PINCTRL_PIN(138, "FAN_TACH_5"),
PINCTRL_PIN(139, "FAN_TACH_6"),
PINCTRL_PIN(140, "FAN_TACH_7"),
PINCTRL_PIN(141, "FAN_PWM_0"),
PINCTRL_PIN(142, "FAN_PWM_1"),
PINCTRL_PIN(143, "FAN_PWM_2"),
PINCTRL_PIN(144, "FAN_PWM_3"),
PINCTRL_PIN(145, "GSXDOUT"),
PINCTRL_PIN(146, "GSXSLOAD"),
PINCTRL_PIN(147, "GSXDIN"),
PINCTRL_PIN(148, "GSXRESETB"),
PINCTRL_PIN(149, "GSXCLK"),
PINCTRL_PIN(150, "ADR_COMPLETE"),
PINCTRL_PIN(151, "NMIB"),
PINCTRL_PIN(152, "SMIB"),
PINCTRL_PIN(153, "GPP_G_20"),
PINCTRL_PIN(154, "GPP_G_21"),
PINCTRL_PIN(155, "GPP_G_22"),
PINCTRL_PIN(156, "GPP_G_23"),
/* GPP_H */
PINCTRL_PIN(157, "SRCCLKREQB_6"),
PINCTRL_PIN(158, "SRCCLKREQB_7"),
PINCTRL_PIN(159, "SRCCLKREQB_8"),
PINCTRL_PIN(160, "SRCCLKREQB_9"),
PINCTRL_PIN(161, "SRCCLKREQB_10"),
PINCTRL_PIN(162, "SRCCLKREQB_11"),
PINCTRL_PIN(163, "SRCCLKREQB_12"),
PINCTRL_PIN(164, "SRCCLKREQB_13"),
PINCTRL_PIN(165, "SRCCLKREQB_14"),
PINCTRL_PIN(166, "SRCCLKREQB_15"),
PINCTRL_PIN(167, "SML2CLK"),
PINCTRL_PIN(168, "SML2DATA"),
PINCTRL_PIN(169, "SML2ALERTB"),
PINCTRL_PIN(170, "SML3CLK"),
PINCTRL_PIN(171, "SML3DATA"),
PINCTRL_PIN(172, "SML3ALERTB"),
PINCTRL_PIN(173, "SML4CLK"),
PINCTRL_PIN(174, "SML4DATA"),
PINCTRL_PIN(175, "SML4ALERTB"),
PINCTRL_PIN(176, "ISH_I2C0_SDA"),
PINCTRL_PIN(177, "ISH_I2C0_SCL"),
PINCTRL_PIN(178, "ISH_I2C1_SDA"),
PINCTRL_PIN(179, "ISH_I2C1_SCL"),
PINCTRL_PIN(180, "GPP_H_23"),
/* GPP_I */
PINCTRL_PIN(181, "DDSP_HDP_0"),
PINCTRL_PIN(182, "DDSP_HDP_1"),
PINCTRL_PIN(183, "DDSP_HDP_2"),
PINCTRL_PIN(184, "DDSP_HDP_3"),
PINCTRL_PIN(185, "EDP_HPD"),
PINCTRL_PIN(186, "DDPB_CTRLCLK"),
PINCTRL_PIN(187, "DDPB_CTRLDATA"),
PINCTRL_PIN(188, "DDPC_CTRLCLK"),
PINCTRL_PIN(189, "DDPC_CTRLDATA"),
PINCTRL_PIN(190, "DDPD_CTRLCLK"),
PINCTRL_PIN(191, "DDPD_CTRLDATA"),
};
static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
static const unsigned spth_i2c0_pins[] = { 64, 65 };
static const unsigned spth_i2c1_pins[] = { 66, 67 };
static const unsigned spth_i2c2_pins[] = { 76, 95 };
static const struct intel_pingroup spth_groups[] = {
PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
};
static const char * const spth_spi0_groups[] = { "spi0_grp" };
static const char * const spth_spi1_groups[] = { "spi0_grp" };
static const char * const spth_uart0_groups[] = { "uart0_grp" };
static const char * const spth_uart1_groups[] = { "uart1_grp" };
static const char * const spth_uart2_groups[] = { "uart2_grp" };
static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
static const struct intel_function spth_functions[] = {
FUNCTION("spi0", spth_spi0_groups),
FUNCTION("spi1", spth_spi1_groups),
FUNCTION("uart0", spth_uart0_groups),
FUNCTION("uart1", spth_uart1_groups),
FUNCTION("uart2", spth_uart2_groups),
FUNCTION("i2c0", spth_i2c0_groups),
FUNCTION("i2c1", spth_i2c1_groups),
FUNCTION("i2c2", spth_i2c2_groups),
};
static const struct intel_community spth_communities[] = {
SPT_COMMUNITY(0, 0, 47),
SPT_COMMUNITY(1, 48, 180),
SPT_COMMUNITY(2, 181, 191),
};
static const struct intel_pinctrl_soc_data spth_soc_data = {
.pins = spth_pins,
.npins = ARRAY_SIZE(spth_pins),
.groups = spth_groups,
.ngroups = ARRAY_SIZE(spth_groups),
.functions = spth_functions,
.nfunctions = ARRAY_SIZE(spth_functions),
.communities = spth_communities,
.ncommunities = ARRAY_SIZE(spth_communities),
};
static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
{ "INT344B", (kernel_ulong_t)&sptlp_soc_data },
{ "INT345D", (kernel_ulong_t)&spth_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);

13
drivers/pinctrl/mediatek/Kconfig
View File

@ -15,6 +15,12 @@ config PINCTRL_MT8135
default MACH_MT8135
select PINCTRL_MTK_COMMON
config PINCTRL_MT8127
bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127
depends on OF
default MACH_MT8127
select PINCTRL_MTK_COMMON
# For ARMv8 SoCs
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
@ -23,4 +29,11 @@ config PINCTRL_MT8173
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_COMMON
# For PMIC
config PINCTRL_MT6397
bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397
depends on OF
default MFD_MT6397
select PINCTRL_MTK_COMMON
endif

2
drivers/pinctrl/mediatek/Makefile
View File

@ -3,4 +3,6 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

77
drivers/pinctrl/mediatek/pinctrl-mt6397.c Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/mfd/mt6397/core.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt6397.h"
#define MT6397_PIN_REG_BASE 0xc000
static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = {
.pins = mtk_pins_mt6397,
.npins = ARRAY_SIZE(mtk_pins_mt6397),
.dir_offset = (MT6397_PIN_REG_BASE + 0x000),
.ies_offset = MTK_PINCTRL_NOT_SUPPORT,
.smt_offset = MTK_PINCTRL_NOT_SUPPORT,
.pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
.pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
.dout_offset = (MT6397_PIN_REG_BASE + 0x080),
.din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
.pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
.type1_start = 41,
.type1_end = 41,
.port_shf = 3,
.port_mask = 0x3,
.port_align = 2,
};
static int mt6397_pinctrl_probe(struct platform_device *pdev)
{
struct mt6397_chip *mt6397;
mt6397 = dev_get_drvdata(pdev->dev.parent);
return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap);
}
static const struct of_device_id mt6397_pctrl_match[] = {
{ .compatible = "mediatek,mt6397-pinctrl", },
{ }
};
MODULE_DEVICE_TABLE(of, mt6397_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt6397_pinctrl_probe,
.driver = {
.name = "mediatek-mt6397-pinctrl",
.of_match_table = mt6397_pctrl_match,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
module_init(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver");
MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");

358
drivers/pinctrl/mediatek/pinctrl-mt8127.c Normal file
View File

@ -0,0 +1,358 @@
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
* Yingjoe Chen <yingjoe.chen@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8127.h"
static const struct mtk_drv_group_desc mt8127_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
MTK_PIN_DRV_GRP(10, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(11, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(12, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(13, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(14, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(15, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(16, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(17, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(18, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(19, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(20, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(21, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(22, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(23, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(24, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(25, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(26, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(27, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(28, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(29, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(30, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(31, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(32, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(33, 0xb30, 4, 1),
MTK_PIN_DRV_GRP(34, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(35, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(36, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(37, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(38, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(39, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(40, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(41, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(42, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(43, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(44, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(45, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(46, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(47, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(48, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(49, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(50, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(51, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(52, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(53, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(54, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(55, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(56, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(59, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(60, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(61, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(62, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(63, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(64, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(65, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(66, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(67, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(68, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(69, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(70, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(71, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(72, 0xb50, 4, 1),
MTK_PIN_DRV_GRP(73, 0xb50, 4, 1),
MTK_PIN_DRV_GRP(74, 0xb50, 4, 1),
MTK_PIN_DRV_GRP(79, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(80, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(81, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(82, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(83, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(84, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(85, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2),
MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(121, 0xc80, 0, 2),
MTK_PIN_DRV_GRP(122, 0xc70, 0, 2),
MTK_PIN_DRV_GRP(123, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(124, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(125, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(126, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(127, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(128, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(129, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(130, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(131, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
MTK_PIN_DRV_GRP(133, 0xc00, 0, 2),
MTK_PIN_DRV_GRP(134, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(135, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(136, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(137, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(142, 0xb50, 0, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */
MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */
MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */
MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */
MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */
MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */
MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */
MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */
MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */
MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */
MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */
MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */
MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */
MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */
MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */
MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */
MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */
MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */
MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */
MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */
MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */
MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */
MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */
MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */
MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */
MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */
MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */
MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */
MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */
MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */
MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */
MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */
MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
};
static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
};
static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
};
static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
ARRAY_SIZE(mt8127_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
ARRAY_SIZE(mt8127_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
.pins = mtk_pins_mt8127,
.npins = ARRAY_SIZE(mtk_pins_mt8127),
.grp_desc = mt8127_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
.pin_drv_grp = mt8127_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
.spec_pull_set = mt8127_spec_pull_set,
.spec_ies_smt_set = mt8127_ies_smt_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
.dout_offset = 0x0400,
.din_offset = 0x0500,
.pinmux_offset = 0x0600,
.type1_start = 143,
.type1_end = 143,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.eint_offsets = {
.name = "mt8127_eint",
.stat = 0x000,
.ack = 0x040,
.mask = 0x080,
.mask_set = 0x0c0,
.mask_clr = 0x100,
.sens = 0x140,
.sens_set = 0x180,
.sens_clr = 0x1c0,
.soft = 0x200,
.soft_set = 0x240,
.soft_clr = 0x280,
.pol = 0x300,
.pol_set = 0x340,
.pol_clr = 0x380,
.dom_en = 0x400,
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
.port_mask = 7,
.ports = 6,
},
.ap_num = 143,
.db_cnt = 16,
};
static int mt8127_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
}
static const struct of_device_id mt8127_pctrl_match[] = {
{ .compatible = "mediatek,mt8127-pinctrl", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8127_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8127_pinctrl_probe,
.driver = {
.name = "mediatek-mt8127-pinctrl",
.of_match_table = mt8127_pctrl_match,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
module_init(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");
MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>");

13
drivers/pinctrl/mediatek/pinctrl-mt8135.c
View File

@ -32,12 +32,12 @@
#define R1_BASE2 0x250
struct mtk_spec_pull_set {
unsigned int pin;
unsigned int pupd_offset;
unsigned char pin;
unsigned char pupd_bit;
unsigned int r0_offset;
unsigned short pupd_offset;
unsigned short r0_offset;
unsigned short r1_offset;
unsigned char r0_bit;
unsigned int r1_offset;
unsigned char r1_bit;
};
@ -305,7 +305,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
.pullen_offset = 0x0200,
.smt_offset = 0x0300,
.pullsel_offset = 0x0400,
.invser_offset = 0x0600,
.dout_offset = 0x0800,
.din_offset = 0x0A00,
.pinmux_offset = 0x0C00,
@ -314,7 +313,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.chip_type = MTK_CHIP_TYPE_BASE,
.eint_offsets = {
.name = "mt8135_eint",
.stat = 0x000,
@ -344,7 +342,7 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
static int mt8135_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8135_pinctrl_data);
return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
}
static const struct of_device_id mt8135_pctrl_match[] = {
@ -359,7 +357,6 @@ static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8135_pinctrl_probe,
.driver = {
.name = "mediatek-mt8135-pinctrl",
.owner = THIS_MODULE,
.of_match_table = mt8135_pctrl_match,
},
};

377
drivers/pinctrl/mediatek/pinctrl-mt8173.c
View File

@ -18,6 +18,7 @@
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
@ -25,228 +26,172 @@
#define DRV_BASE 0xb00
/**
* struct mtk_pin_ies_smt_set - For special pins' ies and smt setting.
* @start: The start pin number of those special pins.
* @end: The end pin number of those special pins.
* @offset: The offset of special setting register.
* @bit: The bit of special setting register.
*/
struct mtk_pin_ies_smt_set {
unsigned int start;
unsigned int end;
unsigned int offset;
unsigned char bit;
static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */
MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */
MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */
MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */
MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */
MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */
MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */
MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */
MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */
MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */
MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */
MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */
MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */
MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */
MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
};
#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \
{ \
.start = _start, \
.end = _end, \
.bit = _bit, \
.offset = _offset, \
}
/**
* struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting.
* @pin: The pin number.
* @offset: The offset of special pull up/down setting register.
* @pupd_bit: The pull up/down bit in this register.
* @r0_bit: The r0 bit of pull resistor.
* @r1_bit: The r1 bit of pull resistor.
*/
struct mtk_pin_spec_pupd_set {
unsigned int pin;
unsigned int offset;
unsigned char pupd_bit;
unsigned char r1_bit;
unsigned char r0_bit;
};
#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \
{ \
.pin = _pin, \
.offset = _offset, \
.pupd_bit = _pupd, \
.r1_bit = _r1, \
.r0_bit = _r0, \
}
static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = {
MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */
MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */
MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */
MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */
MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */
MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */
MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */
MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */
MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */
MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */
MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */
MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */
MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */
MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */
MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */
MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */
MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */
MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */
MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */
MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */
MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */
MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */
MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */
MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
};
static int spec_pull_set(struct regmap *regmap, unsigned int pin,
static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
unsigned int i;
unsigned int reg_pupd, reg_set, reg_rst;
unsigned int bit_pupd, bit_r0, bit_r1;
const struct mtk_pin_spec_pupd_set *spec_pupd_pin;
bool find = false;
for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) {
if (pin == mt8173_spec_pupd[i].pin) {
find = true;
break;
}
}
if (!find)
return -EINVAL;
spec_pupd_pin = mt8173_spec_pupd + i;
reg_set = spec_pupd_pin->offset + align;
reg_rst = spec_pupd_pin->offset + (align << 1);
if (isup)
reg_pupd = reg_rst;
else
reg_pupd = reg_set;
bit_pupd = BIT(spec_pupd_pin->pupd_bit);
regmap_write(regmap, reg_pupd, bit_pupd);
bit_r0 = BIT(spec_pupd_pin->r0_bit);
bit_r1 = BIT(spec_pupd_pin->r1_bit);
switch (r1r0) {
case MTK_PUPD_SET_R1R0_00:
regmap_write(regmap, reg_rst, bit_r0);
regmap_write(regmap, reg_rst, bit_r1);
break;
case MTK_PUPD_SET_R1R0_01:
regmap_write(regmap, reg_set, bit_r0);
regmap_write(regmap, reg_rst, bit_r1);
break;
case MTK_PUPD_SET_R1R0_10:
regmap_write(regmap, reg_rst, bit_r0);
regmap_write(regmap, reg_set, bit_r1);
break;
case MTK_PUPD_SET_R1R0_11:
regmap_write(regmap, reg_set, bit_r0);
regmap_write(regmap, reg_set, bit_r1);
break;
default:
return -EINVAL;
}
return 0;
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = {
MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1),
MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2),
MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10),
MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10),
MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0),
MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2),
MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3),
MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3),
MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4),
MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5),
MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6),
MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7),
MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9),
MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0),
MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11),
MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12),
MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13),
MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13),
MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13),
MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13),
MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13),
MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14),
MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13),
MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13),
MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13),
MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15),
MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0),
MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1),
MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2),
MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13),
MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14),
MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15),
MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13),
MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13),
MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13),
MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4),
MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1),
MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2),
MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5),
MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6),
MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7),
MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0),
MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8),
MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9),
MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8),
MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8)
static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
};
static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value)
static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
};
static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
unsigned int i, reg_addr, bit;
bool find = false;
for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) {
if (pin >= mt8173_ies_smt_set[i].start &&
pin <= mt8173_ies_smt_set[i].end) {
find = true;
break;
}
}
if (!find)
return -EINVAL;
if (value)
reg_addr = mt8173_ies_smt_set[i].offset + align;
else
reg_addr = mt8173_ies_smt_set[i].offset + (align << 1);
bit = BIT(mt8173_ies_smt_set[i].bit);
regmap_write(regmap, reg_addr, bit);
return 0;
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
ARRAY_SIZE(mt8173_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
ARRAY_SIZE(mt8173_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
@ -382,8 +327,8 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
.pin_drv_grp = mt8173_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
.spec_pull_set = spec_pull_set,
.spec_ies_smt_set = spec_ies_smt_set,
.spec_pull_set = mt8173_spec_pull_set,
.spec_ies_smt_set = mt8173_ies_smt_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
@ -424,7 +369,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
static int mt8173_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8173_pinctrl_data);
return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
}
static const struct of_device_id mt8173_pctrl_match[] = {

161
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View File

@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
}
static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
int value, enum pin_config_param param)
static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
int value, enum pin_config_param arg)
{
unsigned int reg_addr, offset;
unsigned int bit;
int ret;
/**
* Due to some soc are not support ies/smt config, add this special
* control to handle it.
*/
if (!pctl->devdata->spec_ies_smt_set &&
pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
arg == PIN_CONFIG_INPUT_ENABLE)
return -EINVAL;
if (!pctl->devdata->spec_ies_smt_set &&
pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return -EINVAL;
/*
* Due to some pins are irregular, their input enable and smt
* control register are discontinuous, but they are mapping together.
* So we need this special handle.
* control register are discontinuous, so we need this special handle.
*/
if (pctl->devdata->spec_ies_smt_set) {
ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
pin, pctl->devdata->port_align, value);
if (!ret)
return;
return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
pin, pctl->devdata->port_align, value, arg);
}
bit = BIT(pin & 0xf);
if (param == PIN_CONFIG_INPUT_ENABLE)
if (arg == PIN_CONFIG_INPUT_ENABLE)
offset = pctl->devdata->ies_offset;
else
offset = pctl->devdata->smt_offset;
@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
return 0;
}
int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
unsigned int pin, unsigned char align, int value)
{
unsigned int i, reg_addr, bit;
for (i = 0; i < info_num; i++) {
if (pin >= ies_smt_infos[i].start &&
pin <= ies_smt_infos[i].end) {
break;
}
}
if (i == info_num)
return -EINVAL;
if (value)
reg_addr = ies_smt_infos[i].offset + align;
else
reg_addr = ies_smt_infos[i].offset + (align << 1);
bit = BIT(ies_smt_infos[i].bit);
regmap_write(regmap, reg_addr, bit);
return 0;
}
static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
@ -186,6 +223,66 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
return -EINVAL;
}
int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
unsigned int info_num, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
unsigned int i;
unsigned int reg_pupd, reg_set, reg_rst;
unsigned int bit_pupd, bit_r0, bit_r1;
const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
bool find = false;
for (i = 0; i < info_num; i++) {
if (pin == pupd_infos[i].pin) {
find = true;
break;
}
}
if (!find)
return -EINVAL;
spec_pupd_pin = pupd_infos + i;
reg_set = spec_pupd_pin->offset + align;
reg_rst = spec_pupd_pin->offset + (align << 1);
if (isup)
reg_pupd = reg_rst;
else
reg_pupd = reg_set;
bit_pupd = BIT(spec_pupd_pin->pupd_bit);
regmap_write(regmap, reg_pupd, bit_pupd);
bit_r0 = BIT(spec_pupd_pin->r0_bit);
bit_r1 = BIT(spec_pupd_pin->r1_bit);
switch (r1r0) {
case MTK_PUPD_SET_R1R0_00:
regmap_write(regmap, reg_rst, bit_r0);
regmap_write(regmap, reg_rst, bit_r1);
break;
case MTK_PUPD_SET_R1R0_01:
regmap_write(regmap, reg_set, bit_r0);
regmap_write(regmap, reg_rst, bit_r1);
break;
case MTK_PUPD_SET_R1R0_10:
regmap_write(regmap, reg_rst, bit_r0);
regmap_write(regmap, reg_set, bit_r1);
break;
case MTK_PUPD_SET_R1R0_11:
regmap_write(regmap, reg_set, bit_r0);
regmap_write(regmap, reg_set, bit_r1);
break;
default:
return -EINVAL;
}
return 0;
}
static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
@ -235,36 +332,37 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
unsigned int pin, enum pin_config_param param,
enum pin_config_param arg)
{
int ret = 0;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
break;
case PIN_CONFIG_INPUT_ENABLE:
mtk_pconf_set_ies_smt(pctl, pin, arg, param);
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
break;
case PIN_CONFIG_OUTPUT:
mtk_gpio_set(pctl->chip, pin, arg);
mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
mtk_pconf_set_ies_smt(pctl, pin, arg, param);
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
mtk_pconf_set_driving(pctl, pin, arg);
ret = mtk_pconf_set_driving(pctl, pin, arg);
break;
default:
return -EINVAL;
ret = -EINVAL;
}
return 0;
return ret;
}
static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
@ -283,12 +381,14 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *g = &pctl->groups[group];
int i;
int i, ret;
for (i = 0; i < num_configs; i++) {
mtk_pconf_parse_conf(pctldev, g->pin,
ret = mtk_pconf_parse_conf(pctldev, g->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
g->config = configs[i];
}
@ -1109,7 +1209,8 @@ static struct pinctrl_desc mtk_pctrl_desc = {
};
int mtk_pctrl_init(struct platform_device *pdev,
const struct mtk_pinctrl_devdata *data)
const struct mtk_pinctrl_devdata *data,
struct regmap *regmap)
{
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *pctl;
@ -1135,6 +1236,11 @@ int mtk_pctrl_init(struct platform_device *pdev,
pctl->regmap1 = syscon_node_to_regmap(node);
if (IS_ERR(pctl->regmap1))
return PTR_ERR(pctl->regmap1);
} else if (regmap) {
pctl->regmap1 = regmap;
} else {
dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
return -EINVAL;
}
/* Only 8135 has two base addr, other SoCs have only one. */
@ -1165,9 +1271,9 @@ int mtk_pctrl_init(struct platform_device *pdev,
mtk_pctrl_desc.npins = pctl->devdata->npins;
pctl->dev = &pdev->dev;
pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
if (!pctl->pctl_dev) {
if (IS_ERR(pctl->pctl_dev)) {
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(pctl->pctl_dev);
}
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
@ -1176,11 +1282,11 @@ int mtk_pctrl_init(struct platform_device *pdev,
goto pctrl_error;
}
pctl->chip = &mtk_gpio_chip;
*pctl->chip = mtk_gpio_chip;
pctl->chip->ngpio = pctl->devdata->npins;
pctl->chip->label = dev_name(&pdev->dev);
pctl->chip->dev = &pdev->dev;
pctl->chip->base = 0;
pctl->chip->base = -1;
ret = gpiochip_add(pctl->chip);
if (ret) {
@ -1196,6 +1302,9 @@ int mtk_pctrl_init(struct platform_device *pdev,
goto chip_error;
}
if (!of_property_read_bool(np, "interrupt-controller"))
return 0;
/* Get EINT register base from dts. */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {

75
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
View File

@ -17,16 +17,17 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf-generic.h>
#define NO_EINT_SUPPORT 255
#define MTK_CHIP_TYPE_BASE 0
#define MTK_CHIP_TYPE_PMIC 1
#define MT_EDGE_SENSITIVE 0
#define MT_LEVEL_SENSITIVE 1
#define EINT_DBNC_SET_DBNC_BITS 4
#define EINT_DBNC_RST_BIT (0x1 << 1)
#define EINT_DBNC_SET_EN (0x1 << 0)
#define MTK_PINCTRL_NOT_SUPPORT (0xffff)
struct mtk_desc_function {
const char *name;
unsigned char muxval;
@ -39,7 +40,6 @@ struct mtk_desc_eint {
struct mtk_desc_pin {
struct pinctrl_pin_desc pin;
const char *chip;
const struct mtk_desc_eint eint;
const struct mtk_desc_function *functions;
};
@ -47,7 +47,6 @@ struct mtk_desc_pin {
#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \
{ \
.pin = _pin, \
.chip = _chip, \
.eint = _eint, \
.functions = (struct mtk_desc_function[]){ \
__VA_ARGS__, { } }, \
@ -107,8 +106,8 @@ struct mtk_drv_group_desc {
* @grp: The group for this pin belongs to.
*/
struct mtk_pin_drv_grp {
unsigned int pin;
unsigned int offset;
unsigned short pin;
unsigned short offset;
unsigned char bit;
unsigned char grp;
};
@ -121,6 +120,54 @@ struct mtk_pin_drv_grp {
.grp = _grp, \
}
/**
* struct mtk_pin_spec_pupd_set_samereg
* - For special pins' pull up/down setting which resides in same register
* @pin: The pin number.
* @offset: The offset of special pull up/down setting register.
* @pupd_bit: The pull up/down bit in this register.
* @r0_bit: The r0 bit of pull resistor.
* @r1_bit: The r1 bit of pull resistor.
*/
struct mtk_pin_spec_pupd_set_samereg {
unsigned short pin;
unsigned short offset;
unsigned char pupd_bit;
unsigned char r1_bit;
unsigned char r0_bit;
};
#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \
{ \
.pin = _pin, \
.offset = _offset, \
.pupd_bit = _pupd, \
.r1_bit = _r1, \
.r0_bit = _r0, \
}
/**
* struct mtk_pin_ies_set - For special pins' ies and smt setting.
* @start: The start pin number of those special pins.
* @end: The end pin number of those special pins.
* @offset: The offset of special setting register.
* @bit: The bit of special setting register.
*/
struct mtk_pin_ies_smt_set {
unsigned short start;
unsigned short end;
unsigned short offset;
unsigned char bit;
};
#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \
{ \
.start = _start, \
.end = _end, \
.bit = _bit, \
.offset = _offset, \
}
struct mtk_eint_offsets {
const char *name;
unsigned int stat;
@ -186,14 +233,13 @@ struct mtk_pinctrl_devdata {
int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
unsigned char align, bool isup, unsigned int arg);
int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
unsigned char align, int value);
unsigned char align, int value, enum pin_config_param arg);
unsigned int dir_offset;
unsigned int ies_offset;
unsigned int smt_offset;
unsigned int pullen_offset;
unsigned int pullsel_offset;
unsigned int drv_offset;
unsigned int invser_offset;
unsigned int dout_offset;
unsigned int din_offset;
unsigned int pinmux_offset;
@ -202,7 +248,6 @@ struct mtk_pinctrl_devdata {
unsigned char port_shf;
unsigned char port_mask;
unsigned char port_align;
unsigned char chip_type;
struct mtk_eint_offsets eint_offsets;
unsigned int ap_num;
unsigned int db_cnt;
@ -224,6 +269,16 @@ struct mtk_pinctrl {
};
int mtk_pctrl_init(struct platform_device *pdev,
const struct mtk_pinctrl_devdata *data);
const struct mtk_pinctrl_devdata *data,
struct regmap *regmap);
int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
unsigned int info_num, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0);
int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
unsigned int pin, unsigned char align, int value);
#endif /* __PINCTRL_MTK_COMMON_H */

424
drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h Normal file
View File

@ -0,0 +1,424 @@
#ifndef __PINCTRL_MTK_MT6397_H
#define __PINCTRL_MTK_MT6397_H
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_PIN(
PINCTRL_PIN(0, "INT"),
"N2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "INT")
),
MTK_PIN(
PINCTRL_PIN(1, "SRCVOLTEN"),
"M4", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "SRCVOLTEN"),
MTK_FUNCTION(6, "TEST_CK1")
),
MTK_PIN(
PINCTRL_PIN(2, "SRCLKEN_PERI"),
"M2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "SRCLKEN_PERI"),
MTK_FUNCTION(6, "TEST_CK2")
),
MTK_PIN(
PINCTRL_PIN(3, "RTC_32K1V8"),
"K3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "RTC_32K1V8"),
MTK_FUNCTION(6, "TEST_CK3")
),
MTK_PIN(
PINCTRL_PIN(4, "WRAP_EVENT"),
"J2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "WRAP_EVENT")
),
MTK_PIN(
PINCTRL_PIN(5, "SPI_CLK"),
"L4", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "SPI_CLK")
),
MTK_PIN(
PINCTRL_PIN(6, "SPI_CSN"),
"J3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "SPI_CSN")
),
MTK_PIN(
PINCTRL_PIN(7, "SPI_MOSI"),
"J1", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SPI_MOSI")
),
MTK_PIN(
PINCTRL_PIN(8, "SPI_MISO"),
"L3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SPI_MISO")
),
MTK_PIN(
PINCTRL_PIN(9, "AUD_CLK_MOSI"),
"H2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO9"),
MTK_FUNCTION(1, "AUD_CLK"),
MTK_FUNCTION(6, "TEST_IN0"),
MTK_FUNCTION(7, "TEST_OUT0")
),
MTK_PIN(
PINCTRL_PIN(10, "AUD_DAT_MISO"),
"H3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "AUD_MISO"),
MTK_FUNCTION(6, "TEST_IN1"),
MTK_FUNCTION(7, "TEST_OUT1")
),
MTK_PIN(
PINCTRL_PIN(11, "AUD_DAT_MOSI"),
"H1", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "AUD_MOSI"),
MTK_FUNCTION(6, "TEST_IN2"),
MTK_FUNCTION(7, "TEST_OUT2")
),
MTK_PIN(
PINCTRL_PIN(12, "COL0"),
"F3", "mt6397",
MTK_EINT_FUNCTION(2, 10),
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "COL0_USBDL"),
MTK_FUNCTION(2, "EINT10_1X"),
MTK_FUNCTION(3, "PWM1_3X"),
MTK_FUNCTION(6, "TEST_IN3"),
MTK_FUNCTION(7, "TEST_OUT3")
),
MTK_PIN(
PINCTRL_PIN(13, "COL1"),
"G8", "mt6397",
MTK_EINT_FUNCTION(2, 11),
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(1, "COL1"),
MTK_FUNCTION(2, "EINT11_1X"),
MTK_FUNCTION(3, "SCL0_2X"),
MTK_FUNCTION(6, "TEST_IN4"),
MTK_FUNCTION(7, "TEST_OUT4")
),
MTK_PIN(
PINCTRL_PIN(14, "COL2"),
"H4", "mt6397",
MTK_EINT_FUNCTION(2, 12),
MTK_FUNCTION(0, "GPIO14"),
MTK_FUNCTION(1, "COL2"),
MTK_FUNCTION(2, "EINT12_1X"),
MTK_FUNCTION(3, "SDA0_2X"),
MTK_FUNCTION(6, "TEST_IN5"),
MTK_FUNCTION(7, "TEST_OUT5")
),
MTK_PIN(
PINCTRL_PIN(15, "COL3"),
"G2", "mt6397",
MTK_EINT_FUNCTION(2, 13),
MTK_FUNCTION(0, "GPIO15"),
MTK_FUNCTION(1, "COL3"),
MTK_FUNCTION(2, "EINT13_1X"),
MTK_FUNCTION(3, "SCL1_2X"),
MTK_FUNCTION(6, "TEST_IN6"),
MTK_FUNCTION(7, "TEST_OUT6")
),
MTK_PIN(
PINCTRL_PIN(16, "COL4"),
"F2", "mt6397",
MTK_EINT_FUNCTION(2, 14),
MTK_FUNCTION(0, "GPIO16"),
MTK_FUNCTION(1, "COL4"),
MTK_FUNCTION(2, "EINT14_1X"),
MTK_FUNCTION(3, "SDA1_2X"),
MTK_FUNCTION(6, "TEST_IN7"),
MTK_FUNCTION(7, "TEST_OUT7")
),
MTK_PIN(
PINCTRL_PIN(17, "COL5"),
"G7", "mt6397",
MTK_EINT_FUNCTION(2, 15),
MTK_FUNCTION(0, "GPIO17"),
MTK_FUNCTION(1, "COL5"),
MTK_FUNCTION(2, "EINT15_1X"),
MTK_FUNCTION(3, "SCL2_2X"),
MTK_FUNCTION(6, "TEST_IN8"),
MTK_FUNCTION(7, "TEST_OUT8")
),
MTK_PIN(
PINCTRL_PIN(18, "COL6"),
"J6", "mt6397",
MTK_EINT_FUNCTION(2, 16),
MTK_FUNCTION(0, "GPIO18"),
MTK_FUNCTION(1, "COL6"),
MTK_FUNCTION(2, "EINT16_1X"),
MTK_FUNCTION(3, "SDA2_2X"),
MTK_FUNCTION(4, "GPIO32K_0"),
MTK_FUNCTION(5, "GPIO26M_0"),
MTK_FUNCTION(6, "TEST_IN9"),
MTK_FUNCTION(7, "TEST_OUT9")
),
MTK_PIN(
PINCTRL_PIN(19, "COL7"),
"J5", "mt6397",
MTK_EINT_FUNCTION(2, 17),
MTK_FUNCTION(0, "GPIO19"),
MTK_FUNCTION(1, "COL7"),
MTK_FUNCTION(2, "EINT17_1X"),
MTK_FUNCTION(3, "PWM2_3X"),
MTK_FUNCTION(4, "GPIO32K_1"),
MTK_FUNCTION(5, "GPIO26M_1"),
MTK_FUNCTION(6, "TEST_IN10"),
MTK_FUNCTION(7, "TEST_OUT10")
),
MTK_PIN(
PINCTRL_PIN(20, "ROW0"),
"L7", "mt6397",
MTK_EINT_FUNCTION(2, 18),
MTK_FUNCTION(0, "GPIO20"),
MTK_FUNCTION(1, "ROW0"),
MTK_FUNCTION(2, "EINT18_1X"),
MTK_FUNCTION(3, "SCL0_3X"),
MTK_FUNCTION(6, "TEST_IN11"),
MTK_FUNCTION(7, "TEST_OUT11")
),
MTK_PIN(
PINCTRL_PIN(21, "ROW1"),
"P1", "mt6397",
MTK_EINT_FUNCTION(2, 19),
MTK_FUNCTION(0, "GPIO21"),
MTK_FUNCTION(1, "ROW1"),
MTK_FUNCTION(2, "EINT19_1X"),
MTK_FUNCTION(3, "SDA0_3X"),
MTK_FUNCTION(4, "AUD_TSTCK"),
MTK_FUNCTION(6, "TEST_IN12"),
MTK_FUNCTION(7, "TEST_OUT12")
),
MTK_PIN(
PINCTRL_PIN(22, "ROW2"),
"J8", "mt6397",
MTK_EINT_FUNCTION(2, 20),
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(1, "ROW2"),
MTK_FUNCTION(2, "EINT20_1X"),
MTK_FUNCTION(3, "SCL1_3X"),
MTK_FUNCTION(6, "TEST_IN13"),
MTK_FUNCTION(7, "TEST_OUT13")
),
MTK_PIN(
PINCTRL_PIN(23, "ROW3"),
"J7", "mt6397",
MTK_EINT_FUNCTION(2, 21),
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(1, "ROW3"),
MTK_FUNCTION(2, "EINT21_1X"),
MTK_FUNCTION(3, "SDA1_3X"),
MTK_FUNCTION(6, "TEST_IN14"),
MTK_FUNCTION(7, "TEST_OUT14")
),
MTK_PIN(
PINCTRL_PIN(24, "ROW4"),
"L5", "mt6397",
MTK_EINT_FUNCTION(2, 22),
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(1, "ROW4"),
MTK_FUNCTION(2, "EINT22_1X"),
MTK_FUNCTION(3, "SCL2_3X"),
MTK_FUNCTION(6, "TEST_IN15"),
MTK_FUNCTION(7, "TEST_OUT15")
),
MTK_PIN(
PINCTRL_PIN(25, "ROW5"),
"N6", "mt6397",
MTK_EINT_FUNCTION(2, 23),
MTK_FUNCTION(0, "GPIO25"),
MTK_FUNCTION(1, "ROW5"),
MTK_FUNCTION(2, "EINT23_1X"),
MTK_FUNCTION(3, "SDA2_3X"),
MTK_FUNCTION(6, "TEST_IN16"),
MTK_FUNCTION(7, "TEST_OUT16")
),
MTK_PIN(
PINCTRL_PIN(26, "ROW6"),
"L6", "mt6397",
MTK_EINT_FUNCTION(2, 24),
MTK_FUNCTION(0, "GPIO26"),
MTK_FUNCTION(1, "ROW6"),
MTK_FUNCTION(2, "EINT24_1X"),
MTK_FUNCTION(3, "PWM3_3X"),
MTK_FUNCTION(4, "GPIO32K_2"),
MTK_FUNCTION(5, "GPIO26M_2"),
MTK_FUNCTION(6, "TEST_IN17"),
MTK_FUNCTION(7, "TEST_OUT17")
),
MTK_PIN(
PINCTRL_PIN(27, "ROW7"),
"P2", "mt6397",
MTK_EINT_FUNCTION(2, 3),
MTK_FUNCTION(0, "GPIO27"),
MTK_FUNCTION(1, "ROW7"),
MTK_FUNCTION(2, "EINT3_1X"),
MTK_FUNCTION(3, "CBUS"),
MTK_FUNCTION(4, "GPIO32K_3"),
MTK_FUNCTION(5, "GPIO26M_3"),
MTK_FUNCTION(6, "TEST_IN18"),
MTK_FUNCTION(7, "TEST_OUT18")
),
MTK_PIN(
PINCTRL_PIN(28, "PWM1(VMSEL1)"),
"J4", "mt6397",
MTK_EINT_FUNCTION(2, 4),
MTK_FUNCTION(0, "GPIO28"),
MTK_FUNCTION(1, "PWM1"),
MTK_FUNCTION(2, "EINT4_1X"),
MTK_FUNCTION(4, "GPIO32K_4"),
MTK_FUNCTION(5, "GPIO26M_4"),
MTK_FUNCTION(6, "TEST_IN19"),
MTK_FUNCTION(7, "TEST_OUT19")
),
MTK_PIN(
PINCTRL_PIN(29, "PWM2(VMSEL2)"),
"N5", "mt6397",
MTK_EINT_FUNCTION(2, 5),
MTK_FUNCTION(0, "GPIO29"),
MTK_FUNCTION(1, "PWM2"),
MTK_FUNCTION(2, "EINT5_1X"),
MTK_FUNCTION(4, "GPIO32K_5"),
MTK_FUNCTION(5, "GPIO26M_5"),
MTK_FUNCTION(6, "TEST_IN20"),
MTK_FUNCTION(7, "TEST_OUT20")
),
MTK_PIN(
PINCTRL_PIN(30, "PWM3(PWM)"),
"R3", "mt6397",
MTK_EINT_FUNCTION(2, 6),
MTK_FUNCTION(0, "GPIO30"),
MTK_FUNCTION(1, "PWM3"),
MTK_FUNCTION(2, "EINT6_1X"),
MTK_FUNCTION(3, "COL0"),
MTK_FUNCTION(4, "GPIO32K_6"),
MTK_FUNCTION(5, "GPIO26M_6"),
MTK_FUNCTION(6, "TEST_IN21"),
MTK_FUNCTION(7, "TEST_OUT21")
),
MTK_PIN(
PINCTRL_PIN(31, "SCL0"),
"N1", "mt6397",
MTK_EINT_FUNCTION(2, 7),
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "SCL0"),
MTK_FUNCTION(2, "EINT7_1X"),
MTK_FUNCTION(3, "PWM1_2X"),
MTK_FUNCTION(6, "TEST_IN22"),
MTK_FUNCTION(7, "TEST_OUT22")
),
MTK_PIN(
PINCTRL_PIN(32, "SDA0"),
"N3", "mt6397",
MTK_EINT_FUNCTION(2, 8),
MTK_FUNCTION(0, "GPIO32"),
MTK_FUNCTION(1, "SDA0"),
MTK_FUNCTION(2, "EINT8_1X"),
MTK_FUNCTION(6, "TEST_IN23"),
MTK_FUNCTION(7, "TEST_OUT23")
),
MTK_PIN(
PINCTRL_PIN(33, "SCL1"),
"T1", "mt6397",
MTK_EINT_FUNCTION(2, 9),
MTK_FUNCTION(0, "GPIO33"),
MTK_FUNCTION(1, "SCL1"),
MTK_FUNCTION(2, "EINT9_1X"),
MTK_FUNCTION(3, "PWM2_2X"),
MTK_FUNCTION(6, "TEST_IN24"),
MTK_FUNCTION(7, "TEST_OUT24")
),
MTK_PIN(
PINCTRL_PIN(34, "SDA1"),
"T2", "mt6397",
MTK_EINT_FUNCTION(2, 0),
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, "SDA1"),
MTK_FUNCTION(2, "EINT0_1X"),
MTK_FUNCTION(6, "TEST_IN25"),
MTK_FUNCTION(7, "TEST_OUT25")
),
MTK_PIN(
PINCTRL_PIN(35, "SCL2"),
"T3", "mt6397",
MTK_EINT_FUNCTION(2, 1),
MTK_FUNCTION(0, "GPIO35"),
MTK_FUNCTION(1, "SCL2"),
MTK_FUNCTION(2, "EINT1_1X"),
MTK_FUNCTION(3, "PWM3_2X"),
MTK_FUNCTION(6, "TEST_IN26"),
MTK_FUNCTION(7, "TEST_OUT26")
),
MTK_PIN(
PINCTRL_PIN(36, "SDA2"),
"U2", "mt6397",
MTK_EINT_FUNCTION(2, 2),
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "SDA2"),
MTK_FUNCTION(2, "EINT2_1X"),
MTK_FUNCTION(6, "TEST_IN27"),
MTK_FUNCTION(7, "TEST_OUT27")
),
MTK_PIN(
PINCTRL_PIN(37, "HDMISD"),
"H6", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO37"),
MTK_FUNCTION(1, "HDMISD"),
MTK_FUNCTION(6, "TEST_IN28"),
MTK_FUNCTION(7, "TEST_OUT28")
),
MTK_PIN(
PINCTRL_PIN(38, "HDMISCK"),
"H5", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO38"),
MTK_FUNCTION(1, "HDMISCK"),
MTK_FUNCTION(6, "TEST_IN29"),
MTK_FUNCTION(7, "TEST_OUT29")
),
MTK_PIN(
PINCTRL_PIN(39, "HTPLG"),
"H7", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO39"),
MTK_FUNCTION(1, "HTPLG"),
MTK_FUNCTION(6, "TEST_IN30"),
MTK_FUNCTION(7, "TEST_OUT30")
),
MTK_PIN(
PINCTRL_PIN(40, "CEC"),
"J9", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO40"),
MTK_FUNCTION(1, "CEC"),
MTK_FUNCTION(6, "TEST_IN31"),
MTK_FUNCTION(7, "TEST_OUT31")
),
};
#endif /* __PINCTRL_MTK_MT6397_H */

1318
drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/pinctrl/meson/pinctrl-meson.c
View File

@ -738,9 +738,9 @@ static int meson_pinctrl_probe(struct platform_device *pdev)
pc->desc.npins = pc->data->num_pins;
pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
if (!pc->pcdev) {
if (IS_ERR(pc->pcdev)) {
dev_err(pc->dev, "can't register pinctrl device");
return -EINVAL;
return PTR_ERR(pc->pcdev);
}
ret = meson_gpiolib_register(pc);

22
drivers/pinctrl/mvebu/pinctrl-armada-370.c
View File

@ -52,12 +52,12 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_FUNCTION(0x2, "uart0", "rxd")),
MPP_MODE(4,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
MPP_FUNCTION(0x1, "vdd", "cpu-pd")),
MPP_MODE(5,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txclko"),
MPP_FUNCTION(0x1, "ge0", "txclkout"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x4, "spi1", "clk"),
MPP_FUNCTION(0x4, "spi1", "sck"),
MPP_FUNCTION(0x5, "audio", "mclk")),
MPP_MODE(6,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -68,7 +68,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_MODE(7,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd1"),
MPP_FUNCTION(0x4, "tdm", "tdx"),
MPP_FUNCTION(0x4, "tdm", "dtx"),
MPP_FUNCTION(0x5, "audio", "lrclk")),
MPP_MODE(8,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -207,11 +207,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_FUNCTION(0x2, "spi0", "cs0")),
MPP_MODE(34,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "wen0"),
MPP_FUNCTION(0x1, "dev", "we0"),
MPP_FUNCTION(0x2, "spi0", "mosi")),
MPP_MODE(35,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "oen"),
MPP_FUNCTION(0x1, "dev", "oe"),
MPP_FUNCTION(0x2, "spi0", "sck")),
MPP_MODE(36,
MPP_FUNCTION(0x0, "gpo", NULL),
@ -348,13 +348,13 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_FUNCTION(0x1, "dev", "ale1"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "sata0", "prsnt"),
MPP_FUNCTION(0x4, "pcie", "rst-out"),
MPP_FUNCTION(0x4, "pcie", "rstout"),
MPP_FUNCTION(0x5, "audio", "sdi")),
MPP_MODE(61,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "wen1"),
MPP_FUNCTION(0x1, "dev", "we1"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x5, "audio", "rclk")),
MPP_FUNCTION(0x5, "audio", "lrclk")),
MPP_MODE(62,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "a2"),
@ -370,11 +370,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_MODE(64,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "miso"),
MPP_FUNCTION(0x2, "spi0-1", "cs1")),
MPP_FUNCTION(0x2, "spi0", "cs1")),
MPP_MODE(65,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "mosi"),
MPP_FUNCTION(0x2, "spi0-1", "cs2")),
MPP_FUNCTION(0x2, "spi0", "cs2")),
};
static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;

50
drivers/pinctrl/mvebu/pinctrl-armada-375.c
View File

@ -51,7 +51,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_MODE(2,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad4"),
MPP_FUNCTION(0x2, "ptp", "eventreq"),
MPP_FUNCTION(0x2, "ptp", "evreq"),
MPP_FUNCTION(0x3, "led", "c0"),
MPP_FUNCTION(0x4, "audio", "sdi"),
MPP_FUNCTION(0x5, "nand", "io4"),
@ -59,7 +59,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_MODE(3,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad5"),
MPP_FUNCTION(0x2, "ptp", "triggen"),
MPP_FUNCTION(0x2, "ptp", "trig"),
MPP_FUNCTION(0x3, "led", "p3"),
MPP_FUNCTION(0x4, "audio", "mclk"),
MPP_FUNCTION(0x5, "nand", "io5"),
@ -81,7 +81,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad0"),
MPP_FUNCTION(0x3, "led", "p1"),
MPP_FUNCTION(0x4, "audio", "rclk"),
MPP_FUNCTION(0x4, "audio", "lrclk"),
MPP_FUNCTION(0x5, "nand", "io0")),
MPP_MODE(7,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -92,19 +92,17 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x5, "nand", "io1")),
MPP_MODE(8,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev ", "bootcs"),
MPP_FUNCTION(0x1, "dev", "bootcs"),
MPP_FUNCTION(0x2, "spi0", "cs0"),
MPP_FUNCTION(0x3, "spi1", "cs0"),
MPP_FUNCTION(0x5, "nand", "ce")),
MPP_MODE(9,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "nf", "wen"),
MPP_FUNCTION(0x2, "spi0", "sck"),
MPP_FUNCTION(0x3, "spi1", "sck"),
MPP_FUNCTION(0x5, "nand", "we")),
MPP_MODE(10,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "nf", "ren"),
MPP_FUNCTION(0x2, "dram", "vttctrl"),
MPP_FUNCTION(0x3, "led", "c1"),
MPP_FUNCTION(0x5, "nand", "re"),
@ -122,9 +120,9 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x5, "nand", "ale")),
MPP_MODE(13,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "readyn"),
MPP_FUNCTION(0x2, "pcie0", "rstoutn"),
MPP_FUNCTION(0x3, "pcie1", "rstoutn"),
MPP_FUNCTION(0x1, "dev", "ready"),
MPP_FUNCTION(0x2, "pcie0", "rstout"),
MPP_FUNCTION(0x3, "pcie1", "rstout"),
MPP_FUNCTION(0x5, "nand", "rb"),
MPP_FUNCTION(0x6, "spi1", "mosi")),
MPP_MODE(14,
@ -143,10 +141,10 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x2, "uart0", "rxd")),
MPP_MODE(18,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "intn")),
MPP_FUNCTION(0x2, "tdm", "int")),
MPP_MODE(19,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "rstn")),
MPP_FUNCTION(0x2, "tdm", "rst")),
MPP_MODE(20,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "pclk")),
@ -203,13 +201,13 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x2, "ge1", "rxclk"),
MPP_FUNCTION(0x3, "sd", "d3"),
MPP_FUNCTION(0x5, "spi0", "sck"),
MPP_FUNCTION(0x6, "pcie0", "rstoutn")),
MPP_FUNCTION(0x6, "pcie0", "rstout")),
MPP_MODE(30,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd0"),
MPP_FUNCTION(0x3, "spi1", "cs0"),
MPP_FUNCTION(0x5, "led", "p3"),
MPP_FUNCTION(0x6, "ptp", "eventreq")),
MPP_FUNCTION(0x6, "ptp", "evreq")),
MPP_MODE(31,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd1"),
@ -219,7 +217,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd2"),
MPP_FUNCTION(0x3, "spi1", "sck"),
MPP_FUNCTION(0x4, "ptp", "triggen"),
MPP_FUNCTION(0x4, "ptp", "trig"),
MPP_FUNCTION(0x5, "led", "c0")),
MPP_MODE(33,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -244,7 +242,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_MODE(37,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie0", "clkreq"),
MPP_FUNCTION(0x2, "tdm", "intn"),
MPP_FUNCTION(0x2, "tdm", "int"),
MPP_FUNCTION(0x4, "ge", "mdc")),
MPP_MODE(38,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -278,7 +276,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_MODE(45,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "spi0", "cs2"),
MPP_FUNCTION(0x4, "pcie0", "rstoutn"),
MPP_FUNCTION(0x4, "pcie0", "rstout"),
MPP_FUNCTION(0x5, "led", "c2"),
MPP_FUNCTION(0x6, "spi1", "cs2")),
MPP_MODE(46,
@ -286,13 +284,13 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x1, "led", "p0"),
MPP_FUNCTION(0x2, "ge0", "txd0"),
MPP_FUNCTION(0x3, "ge1", "txd0"),
MPP_FUNCTION(0x6, "dev", "wen1")),
MPP_FUNCTION(0x6, "dev", "we1")),
MPP_MODE(47,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p1"),
MPP_FUNCTION(0x2, "ge0", "txd1"),
MPP_FUNCTION(0x3, "ge1", "txd1"),
MPP_FUNCTION(0x5, "ptp", "triggen"),
MPP_FUNCTION(0x5, "ptp", "trig"),
MPP_FUNCTION(0x6, "dev", "ale0")),
MPP_MODE(48,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -311,7 +309,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x1, "led", "c0"),
MPP_FUNCTION(0x2, "ge0", "rxd0"),
MPP_FUNCTION(0x3, "ge1", "rxd0"),
MPP_FUNCTION(0x5, "ptp", "eventreq"),
MPP_FUNCTION(0x5, "ptp", "evreq"),
MPP_FUNCTION(0x6, "dev", "ad12")),
MPP_MODE(51,
MPP_FUNCTION(0x0, "gpio", NULL),
@ -328,14 +326,14 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x6, "dev", "ad9")),
MPP_MODE(53,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie1", "rstoutn"),
MPP_FUNCTION(0x1, "pcie1", "rstout"),
MPP_FUNCTION(0x2, "ge0", "rxd3"),
MPP_FUNCTION(0x3, "ge1", "rxd3"),
MPP_FUNCTION(0x5, "i2c0", "sck"),
MPP_FUNCTION(0x6, "dev", "ad10")),
MPP_MODE(54,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie0", "rstoutn"),
MPP_FUNCTION(0x1, "pcie0", "rstout"),
MPP_FUNCTION(0x2, "ge0", "rxctl"),
MPP_FUNCTION(0x3, "ge1", "rxctl"),
MPP_FUNCTION(0x6, "dev", "ad11")),
@ -353,7 +351,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge0", "txctl"),
MPP_FUNCTION(0x3, "ge1", "txctl"),
MPP_FUNCTION(0x6, "dev", "wen0")),
MPP_FUNCTION(0x6, "dev", "we0")),
MPP_MODE(58,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "led", "c0")),
@ -379,9 +377,9 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x6, "dev", "ad15")),
MPP_MODE(63,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ptp", "triggen"),
MPP_FUNCTION(0x2, "ptp", "trig"),
MPP_FUNCTION(0x4, "led", "p2"),
MPP_FUNCTION(0x6, "dev", "burst")),
MPP_FUNCTION(0x6, "dev", "burst/last")),
MPP_MODE(64,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "dram", "vttctrl"),
@ -391,9 +389,9 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_FUNCTION(0x1, "sata1", "prsnt")),
MPP_MODE(66,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ptp", "eventreq"),
MPP_FUNCTION(0x2, "ptp", "evreq"),
MPP_FUNCTION(0x4, "spi1", "cs3"),
MPP_FUNCTION(0x5, "pcie0", "rstoutn"),
MPP_FUNCTION(0x5, "pcie0", "rstout"),
MPP_FUNCTION(0x6, "dev", "cs3")),
};

120
drivers/pinctrl/mvebu/pinctrl-armada-38x.c
View File

@ -94,56 +94,58 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6810_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)),
MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6810_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "trig", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)),
MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "evreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
@ -151,7 +153,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
@ -161,7 +162,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6810_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS),
@ -209,7 +211,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_MODE(30,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6810_PLUS)),
MPP_MODE(31,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS),
@ -217,10 +219,10 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_MODE(32,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6810_PLUS)),
MPP_MODE(33,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "m", "decc_err", V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
@ -231,7 +233,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "trig_gen", V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "trig", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
@ -241,7 +243,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "evreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS),
@ -266,7 +268,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6810_PLUS)),
MPP_MODE(42,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS),
@ -275,84 +278,82 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_MODE(43,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6810_PLUS)),
MPP_MODE(44,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828)),
MPP_MODE(45,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(46,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(47,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)),
MPP_MODE(49,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
MPP_MODE(50,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)),
MPP_MODE(51,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "trig", V_88F6810_PLUS)),
MPP_MODE(52,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "clk", V_88F6810_PLUS)),
MPP_MODE(53,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm2c", "rstn", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "evreq", V_88F6810_PLUS)),
MPP_MODE(54,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
@ -360,29 +361,32 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(56,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(57,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(58,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(59,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)),
};
@ -411,7 +415,7 @@ static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = {
static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 27),
MPP_GPIO_RANGE(1, 32, 32, 28),
};
static int armada_38x_pinctrl_probe(struct platform_device *pdev)

131
drivers/pinctrl/mvebu/pinctrl-armada-39x.c
View File

@ -36,8 +36,10 @@ static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config)
enum {
V_88F6920 = BIT(0),
V_88F6928 = BIT(1),
V_88F6920_PLUS = (V_88F6920 | V_88F6928),
V_88F6925 = BIT(1),
V_88F6928 = BIT(2),
V_88F6920_PLUS = (V_88F6920 | V_88F6925 | V_88F6928),
V_88F6925_PLUS = (V_88F6925 | V_88F6928),
};
static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
@ -82,7 +84,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_MODE(10,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ptp", "event", V_88F6920_PLUS)),
MPP_VAR_FUNCTION(7, "ptp", "evreq", V_88F6920_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS),
@ -95,11 +97,12 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_MODE(13,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "m", "vtt", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@ -108,13 +111,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@ -123,22 +129,23 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sata1", "present", V_88F6928),
MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)),
MPP_MODE(20,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
MPP_MODE(21,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@ -153,31 +160,31 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)),
MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6920_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6920_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6920_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d7", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txclkout", V_88F6920_PLUS)),
MPP_MODE(28,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txd0", V_88F6920_PLUS)),
MPP_MODE(29,
@ -186,7 +193,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txd2", V_88F6920_PLUS)),
MPP_MODE(31,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@ -194,45 +201,45 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)),
MPP_MODE(33,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "m", "decc", V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6920_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6920_PLUS)),
MPP_MODE(35,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6920_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ref", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)),
MPP_MODE(39,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd2", V_88F6920_PLUS)),
MPP_MODE(40,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd", "d2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd3", V_88F6920_PLUS)),
MPP_MODE(41,
@ -240,8 +247,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "burstn", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)),
MPP_MODE(42,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
@ -251,113 +258,119 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_MODE(43,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)),
MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)),
MPP_MODE(44,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),
MPP_MODE(45,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)),
MPP_MODE(46,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),
MPP_MODE(47,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(49,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd", "d5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)),
MPP_MODE(50,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd", "cmd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)),
MPP_MODE(51,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928),
MPP_VAR_FUNCTION(5, "m", "decc", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)),
MPP_MODE(52,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928),
MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928),
MPP_VAR_FUNCTION(5, "sd", "d6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)),
MPP_MODE(53,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata1", "present", V_88F6928),
MPP_VAR_FUNCTION(2, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928),
MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)),
MPP_MODE(54,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd", "d0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua3", "rxd", V_88F6920_PLUS)),
MPP_MODE(56,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(57,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(58,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd", "d1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)),
MPP_MODE(59,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd", "d2", V_88F6920_PLUS)),
MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6920_PLUS)),
};
static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info;
@ -367,6 +380,10 @@ static const struct of_device_id armada_39x_pinctrl_of_match[] = {
.compatible = "marvell,mv88f6920-pinctrl",
.data = (void *) V_88F6920,
},
{
.compatible = "marvell,mv88f6925-pinctrl",
.data = (void *) V_88F6925,
},
{
.compatible = "marvell,mv88f6928-pinctrl",
.data = (void *) V_88F6928,
@ -380,7 +397,7 @@ static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = {
static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 27),
MPP_GPIO_RANGE(1, 32, 32, 28),
};
static int armada_39x_pinctrl_probe(struct platform_device *pdev)

98
drivers/pinctrl/mvebu/pinctrl-armada-xp.c
View File

@ -14,10 +14,7 @@
* available: mv78230, mv78260 and mv78460. From a pin muxing
* perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
* both have 67 MPP pins (more GPIOs and address lines for the memory
* bus mainly). The only difference between the mv78260 and the
* mv78460 in terms of pin muxing is the addition of two functions on
* pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
* cores, mv78460 has four cores).
* bus mainly).
*/
#include <linux/err.h>
@ -57,7 +54,7 @@ enum armada_xp_variant {
static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@ -106,17 +103,19 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(12,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@ -127,11 +126,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@ -155,7 +156,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
@ -172,20 +173,17 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(24,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
@ -200,8 +198,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
@ -209,23 +206,23 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(31,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)),
MPP_MODE(33,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "dram", "deccerr", V_MV78230_PLUS)),
MPP_MODE(35,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
@ -233,74 +230,80 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)),
MPP_MODE(39,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)),
MPP_MODE(40,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)),
MPP_MODE(41,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)),
MPP_MODE(42,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)),
MPP_MODE(43,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)),
MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)),
MPP_MODE(44,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)),
MPP_MODE(45,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)),
MPP_MODE(46,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)),
MPP_MODE(47,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "nand", "rb", V_MV78230_PLUS)),
MPP_MODE(49,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
@ -321,16 +324,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)),
MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)),
MPP_MODE(56,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)),
MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)),
MPP_MODE(57,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)),
MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)),
MPP_MODE(58,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),

4
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View File

@ -706,9 +706,9 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
}
pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
if (!pctl->pctldev) {
if (IS_ERR(pctl->pctldev)) {
dev_err(&pdev->dev, "unable to register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(pctl->pctldev);
}
dev_info(&pdev->dev, "registered pinctrl driver\n");

2
drivers/pinctrl/nomadik/pinctrl-ab8505.c
View File

@ -286,7 +286,7 @@ alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = {
ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */
ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */
ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reserved */
ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */

5
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -787,6 +787,7 @@ static const struct pinmux_ops abx500_pinmux_ops = {
.set_mux = abx500_pmx_set,
.gpio_request_enable = abx500_gpio_request_enable,
.gpio_disable_free = abx500_gpio_disable_free,
.strict = true,
};
static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
@ -1234,10 +1235,10 @@ static int abx500_gpio_probe(struct platform_device *pdev)
abx500_pinctrl_desc.pins = pct->soc->pins;
abx500_pinctrl_desc.npins = pct->soc->npins;
pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
if (!pct->pctldev) {
if (IS_ERR(pct->pctldev)) {
dev_err(&pdev->dev,
"could not register abx500 pinctrl driver\n");
ret = -EINVAL;
ret = PTR_ERR(pct->pctldev);
goto out_rem_chip;
}
dev_info(&pdev->dev, "registered pin controller\n");

66
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -246,6 +246,7 @@ enum nmk_gpio_slpm {
struct nmk_gpio_chip {
struct gpio_chip chip;
struct irq_chip irqchip;
void __iomem *addr;
struct clk *clk;
unsigned int bank;
@ -842,18 +843,6 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d)
clk_disable(nmk_chip->clk);
}
static struct irq_chip nmk_gpio_irq_chip = {
.name = "Nomadik-GPIO",
.irq_ack = nmk_gpio_irq_ack,
.irq_mask = nmk_gpio_irq_mask,
.irq_unmask = nmk_gpio_irq_unmask,
.irq_set_type = nmk_gpio_irq_set_type,
.irq_set_wake = nmk_gpio_irq_set_wake,
.irq_startup = nmk_gpio_irq_startup,
.irq_shutdown = nmk_gpio_irq_shutdown,
.flags = IRQCHIP_MASK_ON_SUSPEND,
};
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
u32 status)
{
@ -1077,18 +1066,6 @@ static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
#define nmk_gpio_dbg_show NULL
#endif
/* This structure is replicated for each GPIO block allocated at probe time */
static struct gpio_chip nmk_gpio_template = {
.request = nmk_gpio_request,
.free = nmk_gpio_free,
.direction_input = nmk_gpio_make_input,
.get = nmk_gpio_get_input,
.direction_output = nmk_gpio_make_output,
.set = nmk_gpio_set_output,
.dbg_show = nmk_gpio_dbg_show,
.can_sleep = false,
};
void nmk_gpio_clocks_enable(void)
{
int i;
@ -1190,6 +1167,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
struct device_node *np = dev->dev.of_node;
struct nmk_gpio_chip *nmk_chip;
struct gpio_chip *chip;
struct irq_chip *irqchip;
struct resource *res;
struct clk *clk;
int latent_irq;
@ -1236,19 +1214,40 @@ static int nmk_gpio_probe(struct platform_device *dev)
nmk_chip->bank = dev->id;
nmk_chip->clk = clk;
nmk_chip->addr = base;
nmk_chip->chip = nmk_gpio_template;
nmk_chip->parent_irq = irq;
nmk_chip->latent_parent_irq = latent_irq;
nmk_chip->sleepmode = supports_sleepmode;
spin_lock_init(&nmk_chip->lock);
chip = &nmk_chip->chip;
chip->request = nmk_gpio_request;
chip->free = nmk_gpio_free;
chip->direction_input = nmk_gpio_make_input;
chip->get = nmk_gpio_get_input;
chip->direction_output = nmk_gpio_make_output;
chip->set = nmk_gpio_set_output;
chip->dbg_show = nmk_gpio_dbg_show;
chip->can_sleep = false;
chip->base = dev->id * NMK_GPIO_PER_CHIP;
chip->ngpio = NMK_GPIO_PER_CHIP;
chip->label = dev_name(&dev->dev);
chip->dev = &dev->dev;
chip->owner = THIS_MODULE;
irqchip = &nmk_chip->irqchip;
irqchip->irq_ack = nmk_gpio_irq_ack;
irqchip->irq_mask = nmk_gpio_irq_mask;
irqchip->irq_unmask = nmk_gpio_irq_unmask;
irqchip->irq_set_type = nmk_gpio_irq_set_type;
irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
irqchip->irq_startup = nmk_gpio_irq_startup;
irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
dev->id,
chip->base,
chip->base + chip->ngpio - 1);
clk_enable(nmk_chip->clk);
nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
clk_disable(nmk_chip->clk);
@ -1269,8 +1268,8 @@ static int nmk_gpio_probe(struct platform_device *dev)
* handler will perform the actual work of handling the parent
* interrupt.
*/
ret = gpiochip_irqchip_add(&nmk_chip->chip,
&nmk_gpio_irq_chip,
ret = gpiochip_irqchip_add(chip,
irqchip,
0,
handle_edge_irq,
IRQ_TYPE_EDGE_FALLING);
@ -1280,13 +1279,13 @@ static int nmk_gpio_probe(struct platform_device *dev)
return -ENODEV;
}
/* Then register the chain on the parent IRQ */
gpiochip_set_chained_irqchip(&nmk_chip->chip,
&nmk_gpio_irq_chip,
gpiochip_set_chained_irqchip(chip,
irqchip,
nmk_chip->parent_irq,
nmk_gpio_irq_handler);
if (nmk_chip->latent_parent_irq > 0)
gpiochip_set_chained_irqchip(&nmk_chip->chip,
&nmk_gpio_irq_chip,
gpiochip_set_chained_irqchip(chip,
irqchip,
nmk_chip->latent_parent_irq,
nmk_gpio_latent_irq_handler);
@ -1803,6 +1802,7 @@ static const struct pinmux_ops nmk_pinmux_ops = {
.set_mux = nmk_pmx_set,
.gpio_request_enable = nmk_gpio_request_enable,
.gpio_disable_free = nmk_gpio_disable_free,
.strict = true,
};
static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
@ -2029,9 +2029,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
npct->dev = &pdev->dev;
npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
if (!npct->pctl) {
if (IS_ERR(npct->pctl)) {
dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
return -EINVAL;
return PTR_ERR(npct->pctl);
}
/* We will handle a range of GPIO pins */

5
drivers/pinctrl/pinctrl-adi2.c
View File

@ -703,6 +703,7 @@ static struct pinmux_ops adi_pinmux_ops = {
.get_function_name = adi_pinmux_get_func_name,
.get_function_groups = adi_pinmux_get_groups,
.gpio_request_enable = adi_pinmux_request_gpio,
.strict = true,
};
@ -1069,9 +1070,9 @@ static int adi_pinctrl_probe(struct platform_device *pdev)
/* Now register the pin controller and all pins it handles */
pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
if (!pinctrl->pctl) {
if (IS_ERR(pinctrl->pctl)) {
dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
return -EINVAL;
return PTR_ERR(pinctrl->pctl);
}
platform_set_drvdata(pdev, pinctrl);

5
drivers/pinctrl/pinctrl-amd.c
View File

@ -789,9 +789,9 @@ static int amd_gpio_probe(struct platform_device *pdev)
amd_pinctrl_desc.name = dev_name(&pdev->dev);
gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc,
&pdev->dev, gpio_dev);
if (!gpio_dev->pctrl) {
if (IS_ERR(gpio_dev->pctrl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(gpio_dev->pctrl);
}
ret = gpiochip_add(&gpio_dev->gc);
@ -855,7 +855,6 @@ MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
static struct platform_driver amd_gpio_driver = {
.driver = {
.name = "amd_gpio",
.owner = THIS_MODULE,
.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
},
.probe = amd_gpio_probe,

4
drivers/pinctrl/pinctrl-as3722.c
View File

@ -586,9 +586,9 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc,
&pdev->dev, as_pci);
if (!as_pci->pctl) {
if (IS_ERR(as_pci->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(as_pci->pctl);
}
as_pci->gpio_chip = as3722_gpio_chip;

20
drivers/pinctrl/pinctrl-at91.c
View File

@ -1238,9 +1238,9 @@ static int at91_pinctrl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info);
info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
if (!info->pctl) {
if (IS_ERR(info->pctl)) {
dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
return -EINVAL;
return PTR_ERR(info->pctl);
}
/* We will handle a range of GPIO pins */
@ -1326,6 +1326,21 @@ static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
}
static void at91_gpio_set_multiple(struct gpio_chip *chip,
unsigned long *mask, unsigned long *bits)
{
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
void __iomem *pio = at91_gpio->regbase;
#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
/* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
writel_relaxed(set_mask, pio + PIO_SODR);
writel_relaxed(clear_mask, pio + PIO_CODR);
}
static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int val)
{
@ -1685,6 +1700,7 @@ static struct gpio_chip at91_gpio_template = {
.get = at91_gpio_get,
.direction_output = at91_gpio_direction_output,
.set = at91_gpio_set,
.set_multiple = at91_gpio_set_multiple,
.dbg_show = at91_gpio_dbg_show,
.can_sleep = false,
.ngpio = MAX_NB_GPIO_PER_BANK,

4
drivers/pinctrl/pinctrl-lantiq.c
View File

@ -337,9 +337,9 @@ int ltq_pinctrl_register(struct platform_device *pdev,
info->dev = &pdev->dev;
info->pctrl = pinctrl_register(desc, &pdev->dev, info);
if (!info->pctrl) {
if (IS_ERR(info->pctrl)) {
dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n");
return -EINVAL;
return PTR_ERR(info->pctrl);
}
platform_set_drvdata(pdev, info);
return 0;

1220
drivers/pinctrl/pinctrl-lpc18xx.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/pinctrl/pinctrl-palmas.c
View File

@ -1044,9 +1044,9 @@ static int palmas_pinctrl_probe(struct platform_device *pdev)
palmas_pinctrl_desc.pins = palmas_pins_desc;
palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci);
if (!pci->pctl) {
if (IS_ERR(pci->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pci->pctl);
}
return 0;
}

1504
drivers/pinctrl/pinctrl-pistachio.c Normal file
View File

File diff suppressed because it is too large Load Diff

131
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -63,6 +63,7 @@ enum rockchip_pinctrl_type {
RK3066B,
RK3188,
RK3288,
RK3368,
};
/**
@ -163,6 +164,9 @@ struct rockchip_pin_ctrl {
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
};
struct rockchip_pin_config {
@ -581,7 +585,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3288_DRV_BITS_PER_PIN 2
#define RK3288_DRV_PINS_PER_REG 8
#define RK3288_DRV_BANK_STRIDE 16
static int rk3288_drv_list[] = { 2, 4, 8, 12 };
static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@ -611,14 +614,81 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
}
static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3188_PULL_PINS_PER_REG;
*bit *= RK3188_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
}
#define RK3368_DRV_PMU_OFFSET 0x20
#define RK3368_DRV_GRF_OFFSET 0x200
static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3288_DRV_PINS_PER_REG;
*bit *= RK3288_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
}
}
static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u32 data;
u8 bit;
rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = regmap_read(regmap, reg, &data);
if (ret)
@ -627,24 +697,25 @@ static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
data >>= bit;
data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
return rk3288_drv_list[data];
return rockchip_perpin_drv_list[data];
}
static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
int strength)
static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
unsigned long flags;
int reg, ret, i;
u32 data, rmask;
u8 bit;
rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
if (rk3288_drv_list[i] == strength) {
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
if (rockchip_perpin_drv_list[i] == strength) {
ret = i;
break;
}
@ -695,6 +766,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
: PIN_CONFIG_BIAS_DISABLE;
case RK3188:
case RK3288:
case RK3368:
data >>= bit;
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
@ -750,6 +822,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case RK3188:
case RK3288:
case RK3368:
spin_lock_irqsave(&bank->slock, flags);
/* enable the write to the equivalent lower bits */
@ -927,6 +1000,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case RK3188:
case RK3288:
case RK3368:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
@ -983,10 +1057,11 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* rk3288 is the first with per-pin drive-strength */
if (info->ctrl->type != RK3288)
if (!info->ctrl->drv_calc_reg)
return -ENOTSUPP;
rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
rc = rockchip_set_drive_perpin(bank,
pin - bank->pin_base, arg);
if (rc < 0)
return rc;
break;
@ -1041,10 +1116,10 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* rk3288 is the first with per-pin drive-strength */
if (info->ctrl->type != RK3288)
if (!info->ctrl->drv_calc_reg)
return -ENOTSUPP;
rc = rk3288_get_drive(bank, pin - bank->pin_base);
rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
if (rc < 0)
return rc;
@ -1274,9 +1349,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
return ret;
info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
if (!info->pctl_dev) {
if (IS_ERR(info->pctl_dev)) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(info->pctl_dev);
}
for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
@ -2056,8 +2131,32 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x84,
.pull_calc_reg = rk3288_calc_pull_reg_and_bit,
.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3368_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU
),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.label = "RK3368-GPIO",
.type = RK3368,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.pull_calc_reg = rk3368_calc_pull_reg_and_bit,
.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)&rk2928_pin_ctrl },
@ -2069,6 +2168,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = (void *)&rk3188_pin_ctrl },
{ .compatible = "rockchip,rk3288-pinctrl",
.data = (void *)&rk3288_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",
.data = (void *)&rk3368_pin_ctrl },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);

6
drivers/pinctrl/pinctrl-single.c
View File

@ -1726,7 +1726,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
return 0;
}
static struct irq_domain_ops pcs_irqdomain_ops = {
static const struct irq_domain_ops pcs_irqdomain_ops = {
.map = pcs_irqdomain_map,
.xlate = irq_domain_xlate_onecell,
};
@ -1921,9 +1921,9 @@ static int pcs_probe(struct platform_device *pdev)
goto free;
pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
if (!pcs->pctl) {
if (IS_ERR(pcs->pctl)) {
dev_err(pcs->dev, "could not register single pinctrl driver\n");
ret = -EINVAL;
ret = PTR_ERR(pcs->pctl);
goto free;
}

4
drivers/pinctrl/pinctrl-st.c
View File

@ -1737,9 +1737,9 @@ static int st_pctl_probe(struct platform_device *pdev)
pctl_desc->name = dev_name(&pdev->dev);
info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info);
if (!info->pctl) {
if (IS_ERR(info->pctl)) {
dev_err(&pdev->dev, "Failed pinctrl registration\n");
return -EINVAL;
return PTR_ERR(info->pctl);
}
for (i = 0; i < info->nbanks; i++)

4
drivers/pinctrl/pinctrl-tb10x.c
View File

@ -807,9 +807,9 @@ static int tb10x_pinctrl_probe(struct platform_device *pdev)
}
state->pctl = pinctrl_register(&tb10x_pindesc, dev, state);
if (!state->pctl) {
if (IS_ERR(state->pctl)) {
dev_err(dev, "could not register TB10x pin driver\n");
ret = -EINVAL;
ret = PTR_ERR(state->pctl);
goto fail;
}

27
drivers/pinctrl/pinctrl-tegra-xusb.c
View File

@ -59,11 +59,6 @@ struct tegra_xusb_padctl_function {
unsigned int num_groups;
};
struct tegra_xusb_padctl_group {
const unsigned int *funcs;
unsigned int num_funcs;
};
struct tegra_xusb_padctl_soc {
const struct pinctrl_pin_desc *pins;
unsigned int num_pins;
@ -130,6 +125,21 @@ static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
return padctl->soc->pins[group].name;
}
static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
/*
* For the tegra-xusb pad controller groups are synonomous
* with lanes/pins and there is always one lane/pin per group.
*/
*pins = &pinctrl->desc->pins[group].number;
*num_pins = 1;
return 0;
}
enum tegra_xusb_padctl_param {
TEGRA_XUSB_PADCTL_IDDQ,
};
@ -253,6 +263,7 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
.get_groups_count = tegra_xusb_padctl_get_groups_count,
.get_group_name = tegra_xusb_padctl_get_group_name,
.get_group_pins = tegra_xusb_padctl_get_group_pins,
.dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
.dt_free_map = pinctrl_utils_dt_free_map,
};
@ -903,15 +914,17 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev)
memset(&padctl->desc, 0, sizeof(padctl->desc));
padctl->desc.name = dev_name(padctl->dev);
padctl->desc.pins = tegra124_pins;
padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
padctl->desc.owner = THIS_MODULE;
padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
if (!padctl->pinctrl) {
if (IS_ERR(padctl->pinctrl)) {
dev_err(&pdev->dev, "failed to register pincontrol\n");
err = -ENODEV;
err = PTR_ERR(padctl->pinctrl);
goto reset;
}

4
drivers/pinctrl/pinctrl-tegra.c
View File

@ -703,9 +703,9 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
}
pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
if (!pmx->pctl) {
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pmx->pctl);
}
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);

4
drivers/pinctrl/pinctrl-tz1090-pdc.c
View File

@ -948,9 +948,9 @@ static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
return PTR_ERR(pmx->regs);
pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx);
if (!pmx->pctl) {
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pmx->pctl);
}
platform_set_drvdata(pdev, pmx);

4
drivers/pinctrl/pinctrl-tz1090.c
View File

@ -1963,9 +1963,9 @@ static int tz1090_pinctrl_probe(struct platform_device *pdev)
return PTR_ERR(pmx->regs);
pmx->pctl = pinctrl_register(&tz1090_pinctrl_desc, &pdev->dev, pmx);
if (!pmx->pctl) {
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pmx->pctl);
}
platform_set_drvdata(pdev, pmx);

4
drivers/pinctrl/pinctrl-u300.c
View File

@ -1068,9 +1068,9 @@ static int u300_pmx_probe(struct platform_device *pdev)
return PTR_ERR(upmx->virtbase);
upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx);
if (!upmx->pctl) {
if (IS_ERR(upmx->pctl)) {
dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
return -EINVAL;
return PTR_ERR(upmx->pctl);
}
platform_set_drvdata(pdev, upmx);

91
drivers/pinctrl/pinctrl-zynq.c
View File

@ -101,6 +101,8 @@ enum zynq_pinmux_functions {
ZYNQ_PMUX_qspi_cs1,
ZYNQ_PMUX_spi0,
ZYNQ_PMUX_spi1,
ZYNQ_PMUX_spi0_ss,
ZYNQ_PMUX_spi1_ss,
ZYNQ_PMUX_sdio0,
ZYNQ_PMUX_sdio0_pc,
ZYNQ_PMUX_sdio0_cd,
@ -123,7 +125,7 @@ enum zynq_pinmux_functions {
ZYNQ_PMUX_MAX_FUNC
};
const struct pinctrl_pin_desc zynq_pins[] = {
static const struct pinctrl_pin_desc zynq_pins[] = {
PINCTRL_PIN(0, "MIO0"),
PINCTRL_PIN(1, "MIO1"),
PINCTRL_PIN(2, "MIO2"),
@ -196,13 +198,35 @@ static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
static const unsigned int qspi_cs1_pins[] = {0};
static const unsigned int qspi_fbclk_pins[] = {8};
static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21};
static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33};
static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45};
static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15};
static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27};
static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39};
static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51};
static const unsigned int spi0_0_pins[] = {16, 17, 21};
static const unsigned int spi0_0_ss0_pins[] = {18};
static const unsigned int spi0_0_ss1_pins[] = {19};
static const unsigned int spi0_0_ss2_pins[] = {20,};
static const unsigned int spi0_1_pins[] = {28, 29, 33};
static const unsigned int spi0_1_ss0_pins[] = {30};
static const unsigned int spi0_1_ss1_pins[] = {31};
static const unsigned int spi0_1_ss2_pins[] = {32};
static const unsigned int spi0_2_pins[] = {40, 41, 45};
static const unsigned int spi0_2_ss0_pins[] = {42};
static const unsigned int spi0_2_ss1_pins[] = {43};
static const unsigned int spi0_2_ss2_pins[] = {44};
static const unsigned int spi1_0_pins[] = {10, 11, 12};
static const unsigned int spi1_0_ss0_pins[] = {13};
static const unsigned int spi1_0_ss1_pins[] = {14};
static const unsigned int spi1_0_ss2_pins[] = {15};
static const unsigned int spi1_1_pins[] = {22, 23, 24};
static const unsigned int spi1_1_ss0_pins[] = {25};
static const unsigned int spi1_1_ss1_pins[] = {26};
static const unsigned int spi1_1_ss2_pins[] = {27};
static const unsigned int spi1_2_pins[] = {34, 35, 36};
static const unsigned int spi1_2_ss0_pins[] = {37};
static const unsigned int spi1_2_ss1_pins[] = {38};
static const unsigned int spi1_2_ss2_pins[] = {39};
static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
static const unsigned int spi1_3_ss0_pins[] = {49};
static const unsigned int spi1_3_ss1_pins[] = {50};
static const unsigned int spi1_3_ss2_pins[] = {51};
static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
@ -369,7 +393,7 @@ static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
.npins = ARRAY_SIZE(nm ## _pins), \
}
struct zynq_pctrl_group zynq_pctrl_groups[] = {
static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
@ -379,12 +403,33 @@ struct zynq_pctrl_group zynq_pctrl_groups[] = {
DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
@ -552,6 +597,15 @@ static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
"spi0_2_grp"};
static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
"spi1_2_grp", "spi1_3_grp"};
static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
"spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
"spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
"spi0_2_ss1_grp", "spi0_2_ss2_grp"};
static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
"spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
"spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
"spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
"spi1_3_ss1_grp", "spi1_3_ss2_grp"};
static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
"sdio0_2_grp"};
static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
@ -714,12 +768,13 @@ static const char * const gpio0_groups[] = {"gpio0_0_grp",
.mux_val = mval, \
}
#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \
#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
[ZYNQ_PMUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
.mux_val = mval, \
.mux = offset, \
.mux_mask = mask, \
.mux_shift = shift, \
}
@ -742,17 +797,19 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = {
DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK,
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK,
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK,
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
@ -1139,8 +1196,8 @@ static int zynq_pinctrl_probe(struct platform_device *pdev)
pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
pctrl->pctrl = pinctrl_register(&zynq_desc, &pdev->dev, pctrl);
if (!pctrl->pctrl)
return -ENOMEM;
if (IS_ERR(pctrl->pctrl))
return PTR_ERR(pctrl->pctrl);
platform_set_drvdata(pdev, pctrl);
@ -1149,7 +1206,7 @@ static int zynq_pinctrl_probe(struct platform_device *pdev)
return 0;
}
int zynq_pinctrl_remove(struct platform_device *pdev)
static int zynq_pinctrl_remove(struct platform_device *pdev)
{
struct zynq_pinctrl *pctrl = platform_get_drvdata(pdev);

59
drivers/pinctrl/pinmux.c
View File

@ -107,6 +107,13 @@ static int pin_request(struct pinctrl_dev *pctldev,
desc->name, desc->gpio_owner, owner);
goto out;
}
if (ops->strict && desc->mux_usecount &&
strcmp(desc->mux_owner, owner)) {
dev_err(pctldev->dev,
"pin %s already requested by %s; cannot claim for %s\n",
desc->name, desc->mux_owner, owner);
goto out;
}
desc->gpio_owner = owner;
} else {
@ -116,6 +123,12 @@ static int pin_request(struct pinctrl_dev *pctldev,
desc->name, desc->mux_owner, owner);
goto out;
}
if (ops->strict && desc->gpio_owner) {
dev_err(pctldev->dev,
"pin %s already requested by %s; cannot claim for %s\n",
desc->name, desc->gpio_owner, owner);
goto out;
}
desc->mux_usecount++;
if (desc->mux_usecount > 1)
@ -544,9 +557,12 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
ret = pmxops->get_function_groups(pctldev, func_selector,
&groups, &num_groups);
if (ret)
if (ret) {
seq_printf(s, "function %s: COULD NOT GET GROUPS\n",
func);
func_selector++;
continue;
}
seq_printf(s, "function: %s, groups = [ ", func);
for (i = 0; i < num_groups; i++)
@ -572,7 +588,12 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
return 0;
seq_puts(s, "Pinmux settings per pin\n");
seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
if (pmxops->strict)
seq_puts(s,
"Format: pin (name): mux_owner|gpio_owner (strict) hog?\n");
else
seq_puts(s,
"Format: pin (name): mux_owner gpio_owner hog?\n");
mutex_lock(&pctldev->mutex);
@ -591,14 +612,34 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
!strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev)))
is_hog = true;
seq_printf(s, "pin %d (%s): %s %s%s", pin,
desc->name ? desc->name : "unnamed",
desc->mux_owner ? desc->mux_owner
: "(MUX UNCLAIMED)",
desc->gpio_owner ? desc->gpio_owner
: "(GPIO UNCLAIMED)",
is_hog ? " (HOG)" : "");
if (pmxops->strict) {
if (desc->mux_owner)
seq_printf(s, "pin %d (%s): device %s%s",
pin,
desc->name ? desc->name : "unnamed",
desc->mux_owner,
is_hog ? " (HOG)" : "");
else if (desc->gpio_owner)
seq_printf(s, "pin %d (%s): GPIO %s",
pin,
desc->name ? desc->name : "unnamed",
desc->gpio_owner);
else
seq_printf(s, "pin %d (%s): UNCLAIMED",
pin,
desc->name ? desc->name : "unnamed");
} else {
/* For non-strict controllers */
seq_printf(s, "pin %d (%s): %s %s%s", pin,
desc->name ? desc->name : "unnamed",
desc->mux_owner ? desc->mux_owner
: "(MUX UNCLAIMED)",
desc->gpio_owner ? desc->gpio_owner
: "(GPIO UNCLAIMED)",
is_hog ? " (HOG)" : "");
}
/* If mux: print function+group claiming the pin */
if (desc->mux_setting)
seq_printf(s, " function %s group %s\n",
pmxops->get_function_name(pctldev,

8
drivers/pinctrl/qcom/Kconfig
View File

@ -31,6 +31,14 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8660 platform.
config PINCTRL_MSM8960
tristate "Qualcomm 8960 pin controller driver"
depends on GPIOLIB && OF

1
drivers/pinctrl/qcom/Makefile
View File

@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o

4
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -906,9 +906,9 @@ int msm_pinctrl_probe(struct platform_device *pdev,
msm_pinctrl_desc.pins = pctrl->soc->pins;
msm_pinctrl_desc.npins = pctrl->soc->npins;
pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
if (!pctrl->pctrl) {
if (IS_ERR(pctrl->pctrl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return -ENODEV;
return PTR_ERR(pctrl->pctrl);
}
ret = msm_gpio_init(pctrl);

984
drivers/pinctrl/qcom/pinctrl-msm8660.c Normal file
View File

@ -0,0 +1,984 @@
/*
* Copyright (c) 2015, Sony Mobile Communications AB.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
static const struct pinctrl_pin_desc msm8660_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
PINCTRL_PIN(110, "GPIO_110"),
PINCTRL_PIN(111, "GPIO_111"),
PINCTRL_PIN(112, "GPIO_112"),
PINCTRL_PIN(113, "GPIO_113"),
PINCTRL_PIN(114, "GPIO_114"),
PINCTRL_PIN(115, "GPIO_115"),
PINCTRL_PIN(116, "GPIO_116"),
PINCTRL_PIN(117, "GPIO_117"),
PINCTRL_PIN(118, "GPIO_118"),
PINCTRL_PIN(119, "GPIO_119"),
PINCTRL_PIN(120, "GPIO_120"),
PINCTRL_PIN(121, "GPIO_121"),
PINCTRL_PIN(122, "GPIO_122"),
PINCTRL_PIN(123, "GPIO_123"),
PINCTRL_PIN(124, "GPIO_124"),
PINCTRL_PIN(125, "GPIO_125"),
PINCTRL_PIN(126, "GPIO_126"),
PINCTRL_PIN(127, "GPIO_127"),
PINCTRL_PIN(128, "GPIO_128"),
PINCTRL_PIN(129, "GPIO_129"),
PINCTRL_PIN(130, "GPIO_130"),
PINCTRL_PIN(131, "GPIO_131"),
PINCTRL_PIN(132, "GPIO_132"),
PINCTRL_PIN(133, "GPIO_133"),
PINCTRL_PIN(134, "GPIO_134"),
PINCTRL_PIN(135, "GPIO_135"),
PINCTRL_PIN(136, "GPIO_136"),
PINCTRL_PIN(137, "GPIO_137"),
PINCTRL_PIN(138, "GPIO_138"),
PINCTRL_PIN(139, "GPIO_139"),
PINCTRL_PIN(140, "GPIO_140"),
PINCTRL_PIN(141, "GPIO_141"),
PINCTRL_PIN(142, "GPIO_142"),
PINCTRL_PIN(143, "GPIO_143"),
PINCTRL_PIN(144, "GPIO_144"),
PINCTRL_PIN(145, "GPIO_145"),
PINCTRL_PIN(146, "GPIO_146"),
PINCTRL_PIN(147, "GPIO_147"),
PINCTRL_PIN(148, "GPIO_148"),
PINCTRL_PIN(149, "GPIO_149"),
PINCTRL_PIN(150, "GPIO_150"),
PINCTRL_PIN(151, "GPIO_151"),
PINCTRL_PIN(152, "GPIO_152"),
PINCTRL_PIN(153, "GPIO_153"),
PINCTRL_PIN(154, "GPIO_154"),
PINCTRL_PIN(155, "GPIO_155"),
PINCTRL_PIN(156, "GPIO_156"),
PINCTRL_PIN(157, "GPIO_157"),
PINCTRL_PIN(158, "GPIO_158"),
PINCTRL_PIN(159, "GPIO_159"),
PINCTRL_PIN(160, "GPIO_160"),
PINCTRL_PIN(161, "GPIO_161"),
PINCTRL_PIN(162, "GPIO_162"),
PINCTRL_PIN(163, "GPIO_163"),
PINCTRL_PIN(164, "GPIO_164"),
PINCTRL_PIN(165, "GPIO_165"),
PINCTRL_PIN(166, "GPIO_166"),
PINCTRL_PIN(167, "GPIO_167"),
PINCTRL_PIN(168, "GPIO_168"),
PINCTRL_PIN(169, "GPIO_169"),
PINCTRL_PIN(170, "GPIO_170"),
PINCTRL_PIN(171, "GPIO_171"),
PINCTRL_PIN(172, "GPIO_172"),
PINCTRL_PIN(173, "SDC1_CLK"),
PINCTRL_PIN(174, "SDC1_CMD"),
PINCTRL_PIN(175, "SDC1_DATA"),
PINCTRL_PIN(176, "SDC3_CLK"),
PINCTRL_PIN(177, "SDC3_CMD"),
PINCTRL_PIN(178, "SDC3_DATA"),
};
#define DECLARE_MSM_GPIO_PIN(pin) static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PIN(0);
DECLARE_MSM_GPIO_PIN(1);
DECLARE_MSM_GPIO_PIN(2);
DECLARE_MSM_GPIO_PIN(3);
DECLARE_MSM_GPIO_PIN(4);
DECLARE_MSM_GPIO_PIN(5);
DECLARE_MSM_GPIO_PIN(6);
DECLARE_MSM_GPIO_PIN(7);
DECLARE_MSM_GPIO_PIN(8);
DECLARE_MSM_GPIO_PIN(9);
DECLARE_MSM_GPIO_PIN(10);
DECLARE_MSM_GPIO_PIN(11);
DECLARE_MSM_GPIO_PIN(12);
DECLARE_MSM_GPIO_PIN(13);
DECLARE_MSM_GPIO_PIN(14);
DECLARE_MSM_GPIO_PIN(15);
DECLARE_MSM_GPIO_PIN(16);
DECLARE_MSM_GPIO_PIN(17);
DECLARE_MSM_GPIO_PIN(18);
DECLARE_MSM_GPIO_PIN(19);
DECLARE_MSM_GPIO_PIN(20);
DECLARE_MSM_GPIO_PIN(21);
DECLARE_MSM_GPIO_PIN(22);
DECLARE_MSM_GPIO_PIN(23);
DECLARE_MSM_GPIO_PIN(24);
DECLARE_MSM_GPIO_PIN(25);
DECLARE_MSM_GPIO_PIN(26);
DECLARE_MSM_GPIO_PIN(27);
DECLARE_MSM_GPIO_PIN(28);
DECLARE_MSM_GPIO_PIN(29);
DECLARE_MSM_GPIO_PIN(30);
DECLARE_MSM_GPIO_PIN(31);
DECLARE_MSM_GPIO_PIN(32);
DECLARE_MSM_GPIO_PIN(33);
DECLARE_MSM_GPIO_PIN(34);
DECLARE_MSM_GPIO_PIN(35);
DECLARE_MSM_GPIO_PIN(36);
DECLARE_MSM_GPIO_PIN(37);
DECLARE_MSM_GPIO_PIN(38);
DECLARE_MSM_GPIO_PIN(39);
DECLARE_MSM_GPIO_PIN(40);
DECLARE_MSM_GPIO_PIN(41);
DECLARE_MSM_GPIO_PIN(42);
DECLARE_MSM_GPIO_PIN(43);
DECLARE_MSM_GPIO_PIN(44);
DECLARE_MSM_GPIO_PIN(45);
DECLARE_MSM_GPIO_PIN(46);
DECLARE_MSM_GPIO_PIN(47);
DECLARE_MSM_GPIO_PIN(48);
DECLARE_MSM_GPIO_PIN(49);
DECLARE_MSM_GPIO_PIN(50);
DECLARE_MSM_GPIO_PIN(51);
DECLARE_MSM_GPIO_PIN(52);
DECLARE_MSM_GPIO_PIN(53);
DECLARE_MSM_GPIO_PIN(54);
DECLARE_MSM_GPIO_PIN(55);
DECLARE_MSM_GPIO_PIN(56);
DECLARE_MSM_GPIO_PIN(57);
DECLARE_MSM_GPIO_PIN(58);
DECLARE_MSM_GPIO_PIN(59);
DECLARE_MSM_GPIO_PIN(60);
DECLARE_MSM_GPIO_PIN(61);
DECLARE_MSM_GPIO_PIN(62);
DECLARE_MSM_GPIO_PIN(63);
DECLARE_MSM_GPIO_PIN(64);
DECLARE_MSM_GPIO_PIN(65);
DECLARE_MSM_GPIO_PIN(66);
DECLARE_MSM_GPIO_PIN(67);
DECLARE_MSM_GPIO_PIN(68);
DECLARE_MSM_GPIO_PIN(69);
DECLARE_MSM_GPIO_PIN(70);
DECLARE_MSM_GPIO_PIN(71);
DECLARE_MSM_GPIO_PIN(72);
DECLARE_MSM_GPIO_PIN(73);
DECLARE_MSM_GPIO_PIN(74);
DECLARE_MSM_GPIO_PIN(75);
DECLARE_MSM_GPIO_PIN(76);
DECLARE_MSM_GPIO_PIN(77);
DECLARE_MSM_GPIO_PIN(78);
DECLARE_MSM_GPIO_PIN(79);
DECLARE_MSM_GPIO_PIN(80);
DECLARE_MSM_GPIO_PIN(81);
DECLARE_MSM_GPIO_PIN(82);
DECLARE_MSM_GPIO_PIN(83);
DECLARE_MSM_GPIO_PIN(84);
DECLARE_MSM_GPIO_PIN(85);
DECLARE_MSM_GPIO_PIN(86);
DECLARE_MSM_GPIO_PIN(87);
DECLARE_MSM_GPIO_PIN(88);
DECLARE_MSM_GPIO_PIN(89);
DECLARE_MSM_GPIO_PIN(90);
DECLARE_MSM_GPIO_PIN(91);
DECLARE_MSM_GPIO_PIN(92);
DECLARE_MSM_GPIO_PIN(93);
DECLARE_MSM_GPIO_PIN(94);
DECLARE_MSM_GPIO_PIN(95);
DECLARE_MSM_GPIO_PIN(96);
DECLARE_MSM_GPIO_PIN(97);
DECLARE_MSM_GPIO_PIN(98);
DECLARE_MSM_GPIO_PIN(99);
DECLARE_MSM_GPIO_PIN(100);
DECLARE_MSM_GPIO_PIN(101);
DECLARE_MSM_GPIO_PIN(102);
DECLARE_MSM_GPIO_PIN(103);
DECLARE_MSM_GPIO_PIN(104);
DECLARE_MSM_GPIO_PIN(105);
DECLARE_MSM_GPIO_PIN(106);
DECLARE_MSM_GPIO_PIN(107);
DECLARE_MSM_GPIO_PIN(108);
DECLARE_MSM_GPIO_PIN(109);
DECLARE_MSM_GPIO_PIN(110);
DECLARE_MSM_GPIO_PIN(111);
DECLARE_MSM_GPIO_PIN(112);
DECLARE_MSM_GPIO_PIN(113);
DECLARE_MSM_GPIO_PIN(114);
DECLARE_MSM_GPIO_PIN(115);
DECLARE_MSM_GPIO_PIN(116);
DECLARE_MSM_GPIO_PIN(117);
DECLARE_MSM_GPIO_PIN(118);
DECLARE_MSM_GPIO_PIN(119);
DECLARE_MSM_GPIO_PIN(120);
DECLARE_MSM_GPIO_PIN(121);
DECLARE_MSM_GPIO_PIN(122);
DECLARE_MSM_GPIO_PIN(123);
DECLARE_MSM_GPIO_PIN(124);
DECLARE_MSM_GPIO_PIN(125);
DECLARE_MSM_GPIO_PIN(126);
DECLARE_MSM_GPIO_PIN(127);
DECLARE_MSM_GPIO_PIN(128);
DECLARE_MSM_GPIO_PIN(129);
DECLARE_MSM_GPIO_PIN(130);
DECLARE_MSM_GPIO_PIN(131);
DECLARE_MSM_GPIO_PIN(132);
DECLARE_MSM_GPIO_PIN(133);
DECLARE_MSM_GPIO_PIN(134);
DECLARE_MSM_GPIO_PIN(135);
DECLARE_MSM_GPIO_PIN(136);
DECLARE_MSM_GPIO_PIN(137);
DECLARE_MSM_GPIO_PIN(138);
DECLARE_MSM_GPIO_PIN(139);
DECLARE_MSM_GPIO_PIN(140);
DECLARE_MSM_GPIO_PIN(141);
DECLARE_MSM_GPIO_PIN(142);
DECLARE_MSM_GPIO_PIN(143);
DECLARE_MSM_GPIO_PIN(144);
DECLARE_MSM_GPIO_PIN(145);
DECLARE_MSM_GPIO_PIN(146);
DECLARE_MSM_GPIO_PIN(147);
DECLARE_MSM_GPIO_PIN(148);
DECLARE_MSM_GPIO_PIN(149);
DECLARE_MSM_GPIO_PIN(150);
DECLARE_MSM_GPIO_PIN(151);
DECLARE_MSM_GPIO_PIN(152);
DECLARE_MSM_GPIO_PIN(153);
DECLARE_MSM_GPIO_PIN(154);
DECLARE_MSM_GPIO_PIN(155);
DECLARE_MSM_GPIO_PIN(156);
DECLARE_MSM_GPIO_PIN(157);
DECLARE_MSM_GPIO_PIN(158);
DECLARE_MSM_GPIO_PIN(159);
DECLARE_MSM_GPIO_PIN(160);
DECLARE_MSM_GPIO_PIN(161);
DECLARE_MSM_GPIO_PIN(162);
DECLARE_MSM_GPIO_PIN(163);
DECLARE_MSM_GPIO_PIN(164);
DECLARE_MSM_GPIO_PIN(165);
DECLARE_MSM_GPIO_PIN(166);
DECLARE_MSM_GPIO_PIN(167);
DECLARE_MSM_GPIO_PIN(168);
DECLARE_MSM_GPIO_PIN(169);
DECLARE_MSM_GPIO_PIN(170);
DECLARE_MSM_GPIO_PIN(171);
DECLARE_MSM_GPIO_PIN(172);
static const unsigned int sdc4_clk_pins[] = { 173 };
static const unsigned int sdc4_cmd_pins[] = { 174 };
static const unsigned int sdc4_data_pins[] = { 175 };
static const unsigned int sdc3_clk_pins[] = { 176 };
static const unsigned int sdc3_cmd_pins[] = { 177 };
static const unsigned int sdc3_data_pins[] = { 178 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7, \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x400 + 0x4 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 1, \
}
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
.oe_bit = -1, \
.in_bit = -1, \
.out_bit = -1, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
enum msm8660_functions {
MSM_MUX_gpio,
MSM_MUX_cam_mclk,
MSM_MUX_dsub,
MSM_MUX_ext_gps,
MSM_MUX_gp_clk_0a,
MSM_MUX_gp_clk_0b,
MSM_MUX_gp_clk_1a,
MSM_MUX_gp_clk_1b,
MSM_MUX_gp_clk_2a,
MSM_MUX_gp_clk_2b,
MSM_MUX_gp_mn,
MSM_MUX_gsbi1,
MSM_MUX_gsbi1_spi_cs1_n,
MSM_MUX_gsbi1_spi_cs2a_n,
MSM_MUX_gsbi1_spi_cs2b_n,
MSM_MUX_gsbi1_spi_cs3_n,
MSM_MUX_gsbi2,
MSM_MUX_gsbi2_spi_cs1_n,
MSM_MUX_gsbi2_spi_cs2_n,
MSM_MUX_gsbi2_spi_cs3_n,
MSM_MUX_gsbi3,
MSM_MUX_gsbi3_spi_cs1_n,
MSM_MUX_gsbi3_spi_cs2_n,
MSM_MUX_gsbi3_spi_cs3_n,
MSM_MUX_gsbi4,
MSM_MUX_gsbi5,
MSM_MUX_gsbi6,
MSM_MUX_gsbi7,
MSM_MUX_gsbi8,
MSM_MUX_gsbi9,
MSM_MUX_gsbi10,
MSM_MUX_gsbi11,
MSM_MUX_gsbi12,
MSM_MUX_hdmi,
MSM_MUX_i2s,
MSM_MUX_lcdc,
MSM_MUX_mdp_vsync,
MSM_MUX_mi2s,
MSM_MUX_pcm,
MSM_MUX_ps_hold,
MSM_MUX_sdc1,
MSM_MUX_sdc2,
MSM_MUX_sdc5,
MSM_MUX_tsif1,
MSM_MUX_tsif2,
MSM_MUX_usb_fs1,
MSM_MUX_usb_fs1_oe_n,
MSM_MUX_usb_fs2,
MSM_MUX_usb_fs2_oe_n,
MSM_MUX_vfe,
MSM_MUX_vsens_alarm,
MSM_MUX__,
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
"gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
"gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
"gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
"gpio171", "gpio172"
};
static const char * const cam_mclk_groups[] = {
"gpio32"
};
static const char * const dsub_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27"
};
static const char * const ext_gps_groups[] = {
"gpio66", "gpio67", "gpio68", "gpio69"
};
static const char * const gp_clk_0a_groups[] = {
"gpio30"
};
static const char * const gp_clk_0b_groups[] = {
"gpio115"
};
static const char * const gp_clk_1a_groups[] = {
"gpio31"
};
static const char * const gp_clk_1b_groups[] = {
"gpio122"
};
static const char * const gp_clk_2a_groups[] = {
"gpio103"
};
static const char * const gp_clk_2b_groups[] = {
"gpio70"
};
static const char * const gp_mn_groups[] = {
"gpio29"
};
static const char * const gsbi1_groups[] = {
"gpio33", "gpio34", "gpio35", "gpio36"
};
static const char * const gsbi1_spi_cs1_n_groups[] = {
};
static const char * const gsbi1_spi_cs2a_n_groups[] = {
};
static const char * const gsbi1_spi_cs2b_n_groups[] = {
};
static const char * const gsbi1_spi_cs3_n_groups[] = {
};
static const char * const gsbi2_groups[] = {
"gpio37", "gpio38", "gpio39", "gpio40"
};
static const char * const gsbi2_spi_cs1_n_groups[] = {
"gpio123"
};
static const char * const gsbi2_spi_cs2_n_groups[] = {
"gpio124"
};
static const char * const gsbi2_spi_cs3_n_groups[] = {
"gpio125"
};
static const char * const gsbi3_groups[] = {
"gpio41", "gpio42", "gpio43", "gpio44"
};
static const char * const gsbi3_spi_cs1_n_groups[] = {
"gpio62"
};
static const char * const gsbi3_spi_cs2_n_groups[] = {
"gpio45"
};
static const char * const gsbi3_spi_cs3_n_groups[] = {
"gpio46"
};
static const char * const gsbi4_groups[] = {
"gpio45", "gpio56", "gpio47", "gpio48"
};
static const char * const gsbi5_groups[] = {
"gpio49", "gpio50", "gpio51", "gpio52"
};
static const char * const gsbi6_groups[] = {
"gpio53", "gpio54", "gpio55", "gpio56"
};
static const char * const gsbi7_groups[] = {
"gpio57", "gpio58", "gpio59", "gpio60"
};
static const char * const gsbi8_groups[] = {
"gpio62", "gpio63", "gpio64", "gpio65"
};
static const char * const gsbi9_groups[] = {
"gpio66", "gpio67", "gpio68", "gpio69"
};
static const char * const gsbi10_groups[] = {
"gpio70", "gpio71", "gpio72", "gpio73"
};
static const char * const gsbi11_groups[] = {
"gpio103", "gpio104", "gpio105", "gpio106"
};
static const char * const gsbi12_groups[] = {
"gpio115", "gpio116", "gpio117", "gpio118"
};
static const char * const hdmi_groups[] = {
"gpio169", "gpio170", "gpio171", "gpio172"
};
static const char * const i2s_groups[] = {
"gpio108", "gpio109", "gpio110", "gpio115", "gpio116", "gpio117",
"gpio118", "gpio119", "gpio120", "gpio121", "gpio122"
};
static const char * const lcdc_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27"
};
static const char * const mdp_vsync_groups[] = {
"gpio28", "gpio39", "gpio41"
};
static const char * const mi2s_groups[] = {
"gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
"gpio107"
};
static const char * const pcm_groups[] = {
"gpio111", "gpio112", "gpio113", "gpio114"
};
static const char * const ps_hold_groups[] = {
"gpio92"
};
static const char * const sdc1_groups[] = {
"gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
"gpio165", "gpio166", "gpio167", "gpio168"
};
static const char * const sdc2_groups[] = {
"gpio143", "gpio144", "gpio145", "gpio146", "gpio147", "gpio148",
"gpio149", "gpio150", "gpio151", "gpio152"
};
static const char * const sdc5_groups[] = {
"gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100"
};
static const char * const tsif1_groups[] = {
"gpio93", "gpio94", "gpio95", "gpio96"
};
static const char * const tsif2_groups[] = {
"gpio97", "gpio98", "gpio99", "gpio100"
};
static const char * const usb_fs1_groups[] = {
"gpio49", "gpio50", "gpio51"
};
static const char * const usb_fs1_oe_n_groups[] = {
"gpio51"
};
static const char * const usb_fs2_groups[] = {
"gpio71", "gpio72", "gpio73"
};
static const char * const usb_fs2_oe_n_groups[] = {
"gpio73"
};
static const char * const vfe_groups[] = {
"gpio29", "gpio30", "gpio31", "gpio42", "gpio46", "gpio105", "gpio106",
"gpio117"
};
static const char * const vsens_alarm_groups[] = {
"gpio127"
};
static const struct msm_function msm8660_functions[] = {
FUNCTION(gpio),
FUNCTION(cam_mclk),
FUNCTION(dsub),
FUNCTION(ext_gps),
FUNCTION(gp_clk_0a),
FUNCTION(gp_clk_0b),
FUNCTION(gp_clk_1a),
FUNCTION(gp_clk_1b),
FUNCTION(gp_clk_2a),
FUNCTION(gp_clk_2b),
FUNCTION(gp_mn),
FUNCTION(gsbi1),
FUNCTION(gsbi1_spi_cs1_n),
FUNCTION(gsbi1_spi_cs2a_n),
FUNCTION(gsbi1_spi_cs2b_n),
FUNCTION(gsbi1_spi_cs3_n),
FUNCTION(gsbi2),
FUNCTION(gsbi2_spi_cs1_n),
FUNCTION(gsbi2_spi_cs2_n),
FUNCTION(gsbi2_spi_cs3_n),
FUNCTION(gsbi3),
FUNCTION(gsbi3_spi_cs1_n),
FUNCTION(gsbi3_spi_cs2_n),
FUNCTION(gsbi3_spi_cs3_n),
FUNCTION(gsbi4),
FUNCTION(gsbi5),
FUNCTION(gsbi6),
FUNCTION(gsbi7),
FUNCTION(gsbi8),
FUNCTION(gsbi9),
FUNCTION(gsbi10),
FUNCTION(gsbi11),
FUNCTION(gsbi12),
FUNCTION(hdmi),
FUNCTION(i2s),
FUNCTION(lcdc),
FUNCTION(mdp_vsync),
FUNCTION(mi2s),
FUNCTION(pcm),
FUNCTION(ps_hold),
FUNCTION(sdc1),
FUNCTION(sdc2),
FUNCTION(sdc5),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(usb_fs1),
FUNCTION(usb_fs1_oe_n),
FUNCTION(usb_fs2),
FUNCTION(usb_fs2_oe_n),
FUNCTION(vfe),
FUNCTION(vsens_alarm),
};
static const struct msm_pingroup msm8660_groups[] = {
PINGROUP(0, lcdc, dsub, _, _, _, _, _),
PINGROUP(1, lcdc, dsub, _, _, _, _, _),
PINGROUP(2, lcdc, dsub, _, _, _, _, _),
PINGROUP(3, lcdc, dsub, _, _, _, _, _),
PINGROUP(4, lcdc, dsub, _, _, _, _, _),
PINGROUP(5, lcdc, dsub, _, _, _, _, _),
PINGROUP(6, lcdc, dsub, _, _, _, _, _),
PINGROUP(7, lcdc, dsub, _, _, _, _, _),
PINGROUP(8, lcdc, dsub, _, _, _, _, _),
PINGROUP(9, lcdc, dsub, _, _, _, _, _),
PINGROUP(10, lcdc, dsub, _, _, _, _, _),
PINGROUP(11, lcdc, dsub, _, _, _, _, _),
PINGROUP(12, lcdc, dsub, _, _, _, _, _),
PINGROUP(13, lcdc, dsub, _, _, _, _, _),
PINGROUP(14, lcdc, dsub, _, _, _, _, _),
PINGROUP(15, lcdc, dsub, _, _, _, _, _),
PINGROUP(16, lcdc, dsub, _, _, _, _, _),
PINGROUP(17, lcdc, dsub, _, _, _, _, _),
PINGROUP(18, lcdc, dsub, _, _, _, _, _),
PINGROUP(19, lcdc, dsub, _, _, _, _, _),
PINGROUP(20, lcdc, dsub, _, _, _, _, _),
PINGROUP(21, lcdc, dsub, _, _, _, _, _),
PINGROUP(22, lcdc, dsub, _, _, _, _, _),
PINGROUP(23, lcdc, dsub, _, _, _, _, _),
PINGROUP(24, lcdc, dsub, _, _, _, _, _),
PINGROUP(25, lcdc, dsub, _, _, _, _, _),
PINGROUP(26, lcdc, dsub, _, _, _, _, _),
PINGROUP(27, lcdc, dsub, _, _, _, _, _),
PINGROUP(28, mdp_vsync, _, _, _, _, _, _),
PINGROUP(29, vfe, gp_mn, _, _, _, _, _),
PINGROUP(30, vfe, gp_clk_0a, _, _, _, _, _),
PINGROUP(31, vfe, gp_clk_1a, _, _, _, _, _),
PINGROUP(32, cam_mclk, _, _, _, _, _, _),
PINGROUP(33, gsbi1, _, _, _, _, _, _),
PINGROUP(34, gsbi1, _, _, _, _, _, _),
PINGROUP(35, gsbi1, _, _, _, _, _, _),
PINGROUP(36, gsbi1, _, _, _, _, _, _),
PINGROUP(37, gsbi2, _, _, _, _, _, _),
PINGROUP(38, gsbi2, _, _, _, _, _, _),
PINGROUP(39, gsbi2, _, mdp_vsync, _, _, _, _),
PINGROUP(40, gsbi2, _, _, _, _, _, _),
PINGROUP(41, gsbi3, mdp_vsync, _, _, _, _, _),
PINGROUP(42, gsbi3, vfe, _, _, _, _, _),
PINGROUP(43, gsbi3, _, _, _, _, _, _),
PINGROUP(44, gsbi3, _, _, _, _, _, _),
PINGROUP(45, gsbi4, gsbi3_spi_cs2_n, _, _, _, _, _),
PINGROUP(46, gsbi4, gsbi3_spi_cs3_n, vfe, _, _, _, _),
PINGROUP(47, gsbi4, _, _, _, _, _, _),
PINGROUP(48, gsbi4, _, _, _, _, _, _),
PINGROUP(49, gsbi5, usb_fs1, _, _, _, _, _),
PINGROUP(50, gsbi5, usb_fs1, _, _, _, _, _),
PINGROUP(51, gsbi5, usb_fs1, usb_fs1_oe_n, _, _, _, _),
PINGROUP(52, gsbi5, _, _, _, _, _, _),
PINGROUP(53, gsbi6, _, _, _, _, _, _),
PINGROUP(54, gsbi6, _, _, _, _, _, _),
PINGROUP(55, gsbi6, _, _, _, _, _, _),
PINGROUP(56, gsbi6, _, _, _, _, _, _),
PINGROUP(57, gsbi7, _, _, _, _, _, _),
PINGROUP(58, gsbi7, _, _, _, _, _, _),
PINGROUP(59, gsbi7, _, _, _, _, _, _),
PINGROUP(60, gsbi7, _, _, _, _, _, _),
PINGROUP(61, _, _, _, _, _, _, _),
PINGROUP(62, gsbi8, gsbi3_spi_cs1_n, gsbi1_spi_cs2a_n, _, _, _, _),
PINGROUP(63, gsbi8, gsbi1_spi_cs1_n, _, _, _, _, _),
PINGROUP(64, gsbi8, gsbi1_spi_cs2b_n, _, _, _, _, _),
PINGROUP(65, gsbi8, gsbi1_spi_cs3_n, _, _, _, _, _),
PINGROUP(66, gsbi9, ext_gps, _, _, _, _, _),
PINGROUP(67, gsbi9, ext_gps, _, _, _, _, _),
PINGROUP(68, gsbi9, ext_gps, _, _, _, _, _),
PINGROUP(69, gsbi9, ext_gps, _, _, _, _, _),
PINGROUP(70, gsbi10, gp_clk_2b, _, _, _, _, _),
PINGROUP(71, gsbi10, usb_fs2, _, _, _, _, _),
PINGROUP(72, gsbi10, usb_fs2, _, _, _, _, _),
PINGROUP(73, gsbi10, usb_fs2, usb_fs2_oe_n, _, _, _, _),
PINGROUP(74, _, _, _, _, _, _, _),
PINGROUP(75, _, _, _, _, _, _, _),
PINGROUP(76, _, _, _, _, _, _, _),
PINGROUP(77, _, _, _, _, _, _, _),
PINGROUP(78, _, _, _, _, _, _, _),
PINGROUP(79, _, _, _, _, _, _, _),
PINGROUP(80, _, _, _, _, _, _, _),
PINGROUP(81, _, _, _, _, _, _, _),
PINGROUP(82, _, _, _, _, _, _, _),
PINGROUP(83, _, _, _, _, _, _, _),
PINGROUP(84, _, _, _, _, _, _, _),
PINGROUP(85, _, _, _, _, _, _, _),
PINGROUP(86, _, _, _, _, _, _, _),
PINGROUP(87, _, _, _, _, _, _, _),
PINGROUP(88, _, _, _, _, _, _, _),
PINGROUP(89, _, _, _, _, _, _, _),
PINGROUP(90, _, _, _, _, _, _, _),
PINGROUP(91, _, _, _, _, _, _, _),
PINGROUP(92, ps_hold, _, _, _, _, _, _),
PINGROUP(93, tsif1, _, _, _, _, _, _),
PINGROUP(94, tsif1, _, _, _, _, _, _),
PINGROUP(95, tsif1, sdc5, _, _, _, _, _),
PINGROUP(96, tsif1, sdc5, _, _, _, _, _),
PINGROUP(97, tsif2, sdc5, _, _, _, _, _),
PINGROUP(98, tsif2, sdc5, _, _, _, _, _),
PINGROUP(99, tsif2, sdc5, _, _, _, _, _),
PINGROUP(100, tsif2, sdc5, _, _, _, _, _),
PINGROUP(101, mi2s, _, _, _, _, _, _),
PINGROUP(102, mi2s, _, _, _, _, _, _),
PINGROUP(103, mi2s, gsbi11, gp_clk_2a, _, _, _, _),
PINGROUP(104, mi2s, gsbi11, _, _, _, _, _),
PINGROUP(105, mi2s, gsbi11, vfe, _, _, _, _),
PINGROUP(106, mi2s, gsbi11, vfe, _, _, _, _),
PINGROUP(107, mi2s, _, _, _, _, _, _),
PINGROUP(108, i2s, _, _, _, _, _, _),
PINGROUP(109, i2s, _, _, _, _, _, _),
PINGROUP(110, i2s, _, _, _, _, _, _),
PINGROUP(111, pcm, _, _, _, _, _, _),
PINGROUP(112, pcm, _, _, _, _, _, _),
PINGROUP(113, pcm, _, _, _, _, _, _),
PINGROUP(114, pcm, _, _, _, _, _, _),
PINGROUP(115, i2s, gsbi12, gp_clk_0b, _, _, _, _),
PINGROUP(116, i2s, gsbi12, _, _, _, _, _),
PINGROUP(117, i2s, gsbi12, vfe, _, _, _, _),
PINGROUP(118, i2s, gsbi12, _, _, _, _, _),
PINGROUP(119, i2s, _, _, _, _, _, _),
PINGROUP(120, i2s, _, _, _, _, _, _),
PINGROUP(121, i2s, _, _, _, _, _, _),
PINGROUP(122, i2s, gp_clk_1b, _, _, _, _, _),
PINGROUP(123, _, gsbi2_spi_cs1_n, _, _, _, _, _),
PINGROUP(124, _, gsbi2_spi_cs2_n, _, _, _, _, _),
PINGROUP(125, _, gsbi2_spi_cs3_n, _, _, _, _, _),
PINGROUP(126, _, _, _, _, _, _, _),
PINGROUP(127, _, vsens_alarm, _, _, _, _, _),
PINGROUP(128, _, _, _, _, _, _, _),
PINGROUP(129, _, _, _, _, _, _, _),
PINGROUP(130, _, _, _, _, _, _, _),
PINGROUP(131, _, _, _, _, _, _, _),
PINGROUP(132, _, _, _, _, _, _, _),
PINGROUP(133, _, _, _, _, _, _, _),
PINGROUP(134, _, _, _, _, _, _, _),
PINGROUP(135, _, _, _, _, _, _, _),
PINGROUP(136, _, _, _, _, _, _, _),
PINGROUP(137, _, _, _, _, _, _, _),
PINGROUP(138, _, _, _, _, _, _, _),
PINGROUP(139, _, _, _, _, _, _, _),
PINGROUP(140, _, _, _, _, _, _, _),
PINGROUP(141, _, _, _, _, _, _, _),
PINGROUP(142, _, _, _, _, _, _, _),
PINGROUP(143, _, sdc2, _, _, _, _, _),
PINGROUP(144, _, sdc2, _, _, _, _, _),
PINGROUP(145, _, sdc2, _, _, _, _, _),
PINGROUP(146, _, sdc2, _, _, _, _, _),
PINGROUP(147, _, sdc2, _, _, _, _, _),
PINGROUP(148, _, sdc2, _, _, _, _, _),
PINGROUP(149, _, sdc2, _, _, _, _, _),
PINGROUP(150, _, sdc2, _, _, _, _, _),
PINGROUP(151, _, sdc2, _, _, _, _, _),
PINGROUP(152, _, sdc2, _, _, _, _, _),
PINGROUP(153, _, _, _, _, _, _, _),
PINGROUP(154, _, _, _, _, _, _, _),
PINGROUP(155, _, _, _, _, _, _, _),
PINGROUP(156, _, _, _, _, _, _, _),
PINGROUP(157, _, _, _, _, _, _, _),
PINGROUP(158, _, _, _, _, _, _, _),
PINGROUP(159, sdc1, _, _, _, _, _, _),
PINGROUP(160, sdc1, _, _, _, _, _, _),
PINGROUP(161, sdc1, _, _, _, _, _, _),
PINGROUP(162, sdc1, _, _, _, _, _, _),
PINGROUP(163, sdc1, _, _, _, _, _, _),
PINGROUP(164, sdc1, _, _, _, _, _, _),
PINGROUP(165, sdc1, _, _, _, _, _, _),
PINGROUP(166, sdc1, _, _, _, _, _, _),
PINGROUP(167, sdc1, _, _, _, _, _, _),
PINGROUP(168, sdc1, _, _, _, _, _, _),
PINGROUP(169, hdmi, _, _, _, _, _, _),
PINGROUP(170, hdmi, _, _, _, _, _, _),
PINGROUP(171, hdmi, _, _, _, _, _, _),
PINGROUP(172, hdmi, _, _, _, _, _, _),
SDC_PINGROUP(sdc4_clk, 0x20a0, -1, 6),
SDC_PINGROUP(sdc4_cmd, 0x20a0, 11, 3),
SDC_PINGROUP(sdc4_data, 0x20a0, 9, 0),
SDC_PINGROUP(sdc3_clk, 0x20a4, -1, 6),
SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3),
SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0),
};
#define NUM_GPIO_PINGROUPS 173
static const struct msm_pinctrl_soc_data msm8660_pinctrl = {
.pins = msm8660_pins,
.npins = ARRAY_SIZE(msm8660_pins),
.functions = msm8660_functions,
.nfunctions = ARRAY_SIZE(msm8660_functions),
.groups = msm8660_groups,
.ngroups = ARRAY_SIZE(msm8660_groups),
.ngpios = NUM_GPIO_PINGROUPS,
};
static int msm8660_pinctrl_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &msm8660_pinctrl);
}
static const struct of_device_id msm8660_pinctrl_of_match[] = {
{ .compatible = "qcom,msm8660-pinctrl", },
{ },
};
static struct platform_driver msm8660_pinctrl_driver = {
.driver = {
.name = "msm8660-pinctrl",
.of_match_table = msm8660_pinctrl_of_match,
},
.probe = msm8660_pinctrl_probe,
.remove = msm_pinctrl_remove,
};
static int __init msm8660_pinctrl_init(void)
{
return platform_driver_register(&msm8660_pinctrl_driver);
}
arch_initcall(msm8660_pinctrl_init);
static void __exit msm8660_pinctrl_exit(void)
{
platform_driver_unregister(&msm8660_pinctrl_driver);
}
module_exit(msm8660_pinctrl_exit);
MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match);

4
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -778,8 +778,8 @@ static int pmic_gpio_probe(struct platform_device *pdev)
state->chip.can_sleep = false;
state->ctrl = pinctrl_register(pctrldesc, dev, state);
if (!state->ctrl)
return -ENODEV;
if (IS_ERR(state->ctrl))
return PTR_ERR(state->ctrl);
ret = gpiochip_add(&state->chip);
if (ret) {

4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
View File

@ -892,8 +892,8 @@ static int pmic_mpp_probe(struct platform_device *pdev)
state->chip.can_sleep = false;
state->ctrl = pinctrl_register(pctrldesc, dev, state);
if (!state->ctrl)
return -ENODEV;
if (IS_ERR(state->ctrl))
return PTR_ERR(state->ctrl);
ret = gpiochip_add(&state->chip);
if (ret) {

4
drivers/pinctrl/samsung/pinctrl-exynos5440.c
View File

@ -822,9 +822,9 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev,
return ret;
pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
if (!pctl_dev) {
if (IS_ERR(pctl_dev)) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(pctl_dev);
}
grange.name = "exynos5440-pctrl-gpio-range";

6
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -806,7 +806,7 @@ static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt);
if (IS_ERR(functions)) {
dev_err(dev, "failed to parse pin functions\n");
return PTR_ERR(groups);
return PTR_ERR(functions);
}
drvdata->pin_groups = groups;
@ -873,9 +873,9 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
return ret;
drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata);
if (!drvdata->pctl_dev) {
if (IS_ERR(drvdata->pctl_dev)) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
return -EINVAL;
return PTR_ERR(drvdata->pctl_dev);
}
for (bank = 0; bank < drvdata->nr_banks; ++bank) {

10
drivers/pinctrl/sh-pfc/Kconfig
View File

@ -55,6 +55,16 @@ config PINCTRL_PFC_R8A7791
depends on ARCH_R8A7791
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7793
def_bool y
depends on ARCH_R8A7793
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7794
def_bool y
depends on ARCH_R8A7794
select PINCTRL_SH_PFC
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203

2
drivers/pinctrl/sh-pfc/Makefile
View File

@ -10,6 +10,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

15
drivers/pinctrl/sh-pfc/core.c
View File

@ -481,6 +481,18 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7791_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7793
{
.compatible = "renesas,pfc-r8a7793",
.data = &r8a7793_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7794
{
.compatible = "renesas,pfc-r8a7794",
.data = &r8a7794_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
{
.compatible = "renesas,pfc-sh73a0",
@ -579,9 +591,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
}
static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif

2
drivers/pinctrl/sh-pfc/core.h
View File

@ -71,6 +71,8 @@ extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;

4
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View File

@ -21,10 +21,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#ifndef CONFIG_ARCH_MULTIPLATFORM
#include <mach/irqs.h>
#endif
#include "core.h"
#include "sh_pfc.h"

2
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -258,7 +258,7 @@ enum {
/* SCIFA7 */
SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
/* SCIFAB */
/* SCIFB */
SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
SCIFB_RXD_PORT191_MARK,
SCIFB_TXD_PORT192_MARK,

101
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
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@ -2664,6 +2664,61 @@ static const unsigned int msiof3_tx_b_pins[] = {
static const unsigned int msiof3_tx_b_mux[] = {
MSIOF3_TXD_B_MARK,
};
/* - PWM -------------------------------------------------------------------- */
static const unsigned int pwm0_pins[] = {
RCAR_GP_PIN(5, 29),
};
static const unsigned int pwm0_mux[] = {
PWM0_MARK,
};
static const unsigned int pwm0_b_pins[] = {
RCAR_GP_PIN(4, 30),
};
static const unsigned int pwm0_b_mux[] = {
PWM0_B_MARK,
};
static const unsigned int pwm1_pins[] = {
RCAR_GP_PIN(5, 30),
};
static const unsigned int pwm1_mux[] = {
PWM1_MARK,
};
static const unsigned int pwm1_b_pins[] = {
RCAR_GP_PIN(4, 31),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
static const unsigned int pwm2_pins[] = {
RCAR_GP_PIN(5, 31),
};
static const unsigned int pwm2_mux[] = {
PWM2_MARK,
};
static const unsigned int pwm3_pins[] = {
RCAR_GP_PIN(0, 16),
};
static const unsigned int pwm3_mux[] = {
PWM3_MARK,
};
static const unsigned int pwm4_pins[] = {
RCAR_GP_PIN(0, 17),
};
static const unsigned int pwm4_mux[] = {
PWM4_MARK,
};
static const unsigned int pwm5_pins[] = {
RCAR_GP_PIN(0, 18),
};
static const unsigned int pwm5_mux[] = {
PWM5_MARK,
};
static const unsigned int pwm6_pins[] = {
RCAR_GP_PIN(0, 19),
};
static const unsigned int pwm6_mux[] = {
PWM6_MARK,
};
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins[] = {
/* SPCLK, SSL */
@ -4008,6 +4063,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof3_sync_b),
SH_PFC_PIN_GROUP(msiof3_rx_b),
SH_PFC_PIN_GROUP(msiof3_tx_b),
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm1),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm2),
SH_PFC_PIN_GROUP(pwm3),
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
@ -4364,6 +4428,36 @@ static const char * const msiof3_groups[] = {
"msiof3_tx_b",
};
static const char * const pwm0_groups[] = {
"pwm0",
"pwm0_b",
};
static const char * const pwm1_groups[] = {
"pwm1",
"pwm1_b",
};
static const char * const pwm2_groups[] = {
"pwm2",
};
static const char * const pwm3_groups[] = {
"pwm3",
};
static const char * const pwm4_groups[] = {
"pwm4",
};
static const char * const pwm5_groups[] = {
"pwm5",
};
static const char * const pwm6_groups[] = {
"pwm6",
};
static const char * const qspi_groups[] = {
"qspi_ctrl",
"qspi_data2",
@ -4621,6 +4715,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),

186
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -2928,6 +2928,79 @@ static const unsigned int msiof2_tx_e_pins[] = {
static const unsigned int msiof2_tx_e_mux[] = {
MSIOF2_TXD_E_MARK,
};
/* - PWM -------------------------------------------------------------------- */
static const unsigned int pwm0_pins[] = {
RCAR_GP_PIN(6, 14),
};
static const unsigned int pwm0_mux[] = {
PWM0_MARK,
};
static const unsigned int pwm0_b_pins[] = {
RCAR_GP_PIN(5, 30),
};
static const unsigned int pwm0_b_mux[] = {
PWM0_B_MARK,
};
static const unsigned int pwm1_pins[] = {
RCAR_GP_PIN(1, 17),
};
static const unsigned int pwm1_mux[] = {
PWM1_MARK,
};
static const unsigned int pwm1_b_pins[] = {
RCAR_GP_PIN(6, 15),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
static const unsigned int pwm2_pins[] = {
RCAR_GP_PIN(1, 18),
};
static const unsigned int pwm2_mux[] = {
PWM2_MARK,
};
static const unsigned int pwm2_b_pins[] = {
RCAR_GP_PIN(0, 16),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
static const unsigned int pwm3_pins[] = {
RCAR_GP_PIN(1, 24),
};
static const unsigned int pwm3_mux[] = {
PWM3_MARK,
};
static const unsigned int pwm4_pins[] = {
RCAR_GP_PIN(3, 26),
};
static const unsigned int pwm4_mux[] = {
PWM4_MARK,
};
static const unsigned int pwm4_b_pins[] = {
RCAR_GP_PIN(3, 31),
};
static const unsigned int pwm4_b_mux[] = {
PWM4_B_MARK,
};
static const unsigned int pwm5_pins[] = {
RCAR_GP_PIN(7, 21),
};
static const unsigned int pwm5_mux[] = {
PWM5_MARK,
};
static const unsigned int pwm5_b_pins[] = {
RCAR_GP_PIN(7, 20),
};
static const unsigned int pwm5_b_mux[] = {
PWM5_B_MARK,
};
static const unsigned int pwm6_pins[] = {
RCAR_GP_PIN(7, 22),
};
static const unsigned int pwm6_mux[] = {
PWM6_MARK,
};
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins[] = {
/* SPCLK, SSL */
@ -4348,6 +4421,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof2_sync_e),
SH_PFC_PIN_GROUP(msiof2_rx_e),
SH_PFC_PIN_GROUP(msiof2_tx_e),
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm1),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm2),
SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(pwm3),
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
@ -4745,6 +4830,39 @@ static const char * const msiof2_groups[] = {
"msiof2_tx_e",
};
static const char * const pwm0_groups[] = {
"pwm0",
"pwm0_b",
};
static const char * const pwm1_groups[] = {
"pwm1",
"pwm1_b",
};
static const char * const pwm2_groups[] = {
"pwm2",
"pwm2_b",
};
static const char * const pwm3_groups[] = {
"pwm3",
};
static const char * const pwm4_groups[] = {
"pwm4",
"pwm4_b",
};
static const char * const pwm5_groups[] = {
"pwm5",
"pwm5_b",
};
static const char * const pwm6_groups[] = {
"pwm6",
};
static const char * const qspi_groups[] = {
"qspi_ctrl",
"qspi_data2",
@ -4989,6 +5107,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
@ -6000,7 +6125,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
3, 2, 2, 2, 1, 2, 2, 2) {
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_SCIF1 [2] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
@ -6027,11 +6152,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
0, 0, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_VI1 [2] */
FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_TMU [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
@ -6049,7 +6174,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
0, 0, 0,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_SCIF [1] */
FN_SEL_SCIF_0, FN_SEL_SCIF_1,
@ -6059,13 +6184,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
/* SEL_CAN1 [2] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_SCIFA2 [1] */
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
/* SEL_SCIF4 [2] */
FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_ADG [1] */
FN_SEL_ADG_0, FN_SEL_ADG_1,
@ -6075,7 +6200,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* SEL_SCIFA5 [2] */
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
@ -6085,7 +6210,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
/* SEL_SIM [1] */
FN_SEL_SIM_0, FN_SEL_SIM_1,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_SSI8 [1] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
@ -6115,7 +6240,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_MMC_0, FN_SEL_MMC_1,
/* SEL_SCIF5 [1] */
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_IIC2 [2] */
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
@ -6125,11 +6250,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* SEL_IIC0 [2] */
FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0, }
},
{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
@ -6143,7 +6268,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
/* SEL_DIS [2] */
FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_RAD [1] */
FN_SEL_RAD_0, FN_SEL_RAD_1,
@ -6155,15 +6280,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
0, 0, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* SEL_SOF2 [3] */
FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
FN_SEL_SOF2_3, FN_SEL_SOF2_4,
0, 0, 0,
/* RESEVED [1] */
/* RESERVED [1] */
0, 0,
/* SEL_SSI1 [1] */
FN_SEL_SSI1_0, FN_SEL_SSI1_1,
@ -6171,16 +6296,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_SSI0_0, FN_SEL_SSI0_1,
/* SEL_SSP [2] */
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0,
/* RESEVED [2] */
/* RESERVED [2] */
0, 0, 0, 0, }
},
{ },
};
#ifdef CONFIG_PINCTRL_PFC_R8A7791
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
.name = "r8a77910_pfc",
.unlock_reg = 0xe6060000, /* PMMR */
@ -6199,3 +6325,25 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7793
const struct sh_pfc_soc_info r8a7793_pinmux_info = {
.name = "r8a77930_pfc",
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
#endif

4207
drivers/pinctrl/sh-pfc/pfc-r8a7794.c Normal file
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File diff suppressed because it is too large Load Diff

4
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -625,8 +625,8 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pctl_desc.npins = pfc->info->nr_pins;
pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
if (pmx->pctl == NULL)
return -EINVAL;
if (IS_ERR(pmx->pctl))
return PTR_ERR(pmx->pctl);
return 0;
}

1
drivers/pinctrl/sirf/Makefile
View File

@ -3,3 +3,4 @@
obj-y += pinctrl-sirf.o
obj-y += pinctrl-prima2.o
obj-y += pinctrl-atlas6.o
obj-y += pinctrl-atlas7.o

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