nvmem: qfprom: Add fuse blowing support
This patch adds support for blowing fuses to the qfprom driver if the required properties are defined in the device tree. [Srini: Fixed merge conflict with AUTO ID] Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20200722100705.7772-12-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ravi Kumar Bokka
Greg Kroah-Hartman
parent
a37a15f748
commit
93b4e49f8c
@ -3,58 +3,350 @@
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* Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/io.h>
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#include <linux/nvmem-provider.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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struct qfprom_priv {
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void __iomem *base;
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/* Blow timer clock frequency in Mhz */
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#define QFPROM_BLOW_TIMER_OFFSET 0x03c
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/* Amount of time required to hold charge to blow fuse in micro-seconds */
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#define QFPROM_FUSE_BLOW_POLL_US 100
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#define QFPROM_FUSE_BLOW_TIMEOUT_US 1000
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#define QFPROM_BLOW_STATUS_OFFSET 0x048
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#define QFPROM_BLOW_STATUS_BUSY 0x1
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#define QFPROM_BLOW_STATUS_READY 0x0
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#define QFPROM_ACCEL_OFFSET 0x044
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#define QFPROM_VERSION_OFFSET 0x0
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#define QFPROM_MAJOR_VERSION_SHIFT 28
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#define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
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#define QFPROM_MINOR_VERSION_SHIFT 16
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#define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)
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static bool read_raw_data;
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module_param(read_raw_data, bool, 0644);
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MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");
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/**
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* struct qfprom_soc_data - config that varies from SoC to SoC.
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*
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* @accel_value: Should contain qfprom accel value.
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* @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
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* @qfprom_blow_set_freq: The frequency required to set when we start the
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* fuse blowing.
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*/
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struct qfprom_soc_data {
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u32 accel_value;
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u32 qfprom_blow_timer_value;
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u32 qfprom_blow_set_freq;
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};
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/**
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* struct qfprom_priv - structure holding qfprom attributes
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*
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* @qfpraw: iomapped memory space for qfprom-efuse raw address space.
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* @qfpconf: iomapped memory space for qfprom-efuse configuration address
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* space.
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* @qfpcorrected: iomapped memory space for qfprom corrected address space.
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* @qfpsecurity: iomapped memory space for qfprom security control space.
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* @dev: qfprom device structure.
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* @secclk: Clock supply.
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* @vcc: Regulator supply.
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* @soc_data: Data that for things that varies from SoC to SoC.
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*/
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struct qfprom_priv {
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void __iomem *qfpraw;
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void __iomem *qfpconf;
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void __iomem *qfpcorrected;
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void __iomem *qfpsecurity;
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struct device *dev;
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struct clk *secclk;
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struct regulator *vcc;
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const struct qfprom_soc_data *soc_data;
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};
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/**
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* struct qfprom_touched_values - saved values to restore after blowing
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*
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* @clk_rate: The rate the clock was at before blowing.
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* @accel_val: The value of the accel reg before blowing.
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* @timer_val: The value of the timer before blowing.
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*/
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struct qfprom_touched_values {
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unsigned long clk_rate;
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u32 accel_val;
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u32 timer_val;
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};
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/**
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* qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
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* @priv: Our driver data.
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* @old: The data that was stashed from before fuse blowing.
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*
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* Resets the value of the blow timer, accel register and the clock
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* and voltage settings.
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*
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* Prints messages if there are errors but doesn't return an error code
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* since there's not much we can do upon failure.
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*/
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static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
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const struct qfprom_touched_values *old)
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{
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int ret;
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ret = regulator_disable(priv->vcc);
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if (ret)
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dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");
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ret = clk_set_rate(priv->secclk, old->clk_rate);
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if (ret)
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dev_warn(priv->dev,
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"Failed to set clock rate for disable (ignoring)\n");
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clk_disable_unprepare(priv->secclk);
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writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
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writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
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}
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/**
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* qfprom_enable_fuse_blowing() - Enable fuse blowing.
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* @priv: Our driver data.
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* @old: We'll stash stuff here to use when disabling.
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*
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* Sets the value of the blow timer, accel register and the clock
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* and voltage settings.
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*
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* Prints messages if there are errors so caller doesn't need to.
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*
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* Return: 0 or -err.
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*/
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static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
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struct qfprom_touched_values *old)
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{
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int ret;
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ret = clk_prepare_enable(priv->secclk);
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if (ret) {
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dev_err(priv->dev, "Failed to enable clock\n");
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return ret;
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}
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old->clk_rate = clk_get_rate(priv->secclk);
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ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
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if (ret) {
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dev_err(priv->dev, "Failed to set clock rate for enable\n");
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goto err_clk_prepared;
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}
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ret = regulator_enable(priv->vcc);
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if (ret) {
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dev_err(priv->dev, "Failed to enable regulator\n");
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goto err_clk_rate_set;
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}
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old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
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old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
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writel(priv->soc_data->qfprom_blow_timer_value,
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priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
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writel(priv->soc_data->accel_value,
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priv->qfpconf + QFPROM_ACCEL_OFFSET);
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return 0;
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err_clk_rate_set:
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clk_set_rate(priv->secclk, old->clk_rate);
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err_clk_prepared:
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clk_disable_unprepare(priv->secclk);
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return ret;
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}
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/**
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* qfprom_efuse_reg_write() - Write to fuses.
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* @context: Our driver data.
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* @reg: The offset to write at.
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* @_val: Pointer to data to write.
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* @bytes: The number of bytes to write.
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*
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* Writes to fuses. WARNING: THIS IS PERMANENT.
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*
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* Return: 0 or -err.
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*/
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static int qfprom_reg_write(void *context, unsigned int reg, void *_val,
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size_t bytes)
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{
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struct qfprom_priv *priv = context;
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struct qfprom_touched_values old;
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int words = bytes / 4;
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u32 *value = _val;
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u32 blow_status;
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int ret;
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int i;
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dev_dbg(priv->dev,
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"Writing to raw qfprom region : %#010x of size: %zu\n",
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reg, bytes);
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/*
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* The hardware only allows us to write word at a time, but we can
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* read byte at a time. Until the nvmem framework allows a separate
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* word_size and stride for reading vs. writing, we'll enforce here.
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*/
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if (bytes % 4) {
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dev_err(priv->dev,
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"%zu is not an integral number of words\n", bytes);
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return -EINVAL;
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}
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if (reg % 4) {
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dev_err(priv->dev,
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"Invalid offset: %#x. Must be word aligned\n", reg);
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return -EINVAL;
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}
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ret = qfprom_enable_fuse_blowing(priv, &old);
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if (ret)
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return ret;
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ret = readl_relaxed_poll_timeout(
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priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
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blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
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QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
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if (ret) {
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dev_err(priv->dev,
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"Timeout waiting for initial ready; aborting.\n");
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goto exit_enabled_fuse_blowing;
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}
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for (i = 0; i < words; i++)
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writel(value[i], priv->qfpraw + reg + (i * 4));
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ret = readl_relaxed_poll_timeout(
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priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
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blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
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QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
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/* Give an error, but not much we can do in this case */
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if (ret)
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dev_err(priv->dev, "Timeout waiting for finish.\n");
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exit_enabled_fuse_blowing:
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qfprom_disable_fuse_blowing(priv, &old);
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return ret;
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}
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static int qfprom_reg_read(void *context,
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unsigned int reg, void *_val, size_t bytes)
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{
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struct qfprom_priv *priv = context;
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u8 *val = _val;
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int i = 0, words = bytes;
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void __iomem *base = priv->qfpcorrected;
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if (read_raw_data && priv->qfpraw)
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base = priv->qfpraw;
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while (words--)
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*val++ = readb(priv->base + reg + i++);
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*val++ = readb(base + reg + i++);
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return 0;
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}
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static struct nvmem_config econfig = {
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.name = "qfprom",
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.stride = 1,
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.word_size = 1,
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.id = NVMEM_DEVID_AUTO,
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.reg_read = qfprom_reg_read,
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static const struct qfprom_soc_data qfprom_7_8_data = {
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.accel_value = 0xD10,
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.qfprom_blow_timer_value = 25,
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.qfprom_blow_set_freq = 4800000,
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};
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static int qfprom_probe(struct platform_device *pdev)
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{
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struct nvmem_config econfig = {
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.name = "qfprom",
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.stride = 1,
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.word_size = 1,
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.id = NVMEM_DEVID_AUTO,
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.reg_read = qfprom_reg_read,
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};
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct nvmem_device *nvmem;
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struct qfprom_priv *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* The corrected section is always provided */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->qfpcorrected = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->qfpcorrected))
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return PTR_ERR(priv->qfpcorrected);
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econfig.size = resource_size(res);
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econfig.dev = dev;
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econfig.priv = priv;
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priv->dev = dev;
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/*
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* If more than one region is provided then the OS has the ability
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* to write.
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*/
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (res) {
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u32 version;
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int major_version, minor_version;
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priv->qfpraw = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->qfpraw))
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return PTR_ERR(priv->qfpraw);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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priv->qfpconf = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->qfpconf))
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return PTR_ERR(priv->qfpconf);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
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priv->qfpsecurity = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->qfpsecurity))
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return PTR_ERR(priv->qfpsecurity);
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version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
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major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
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QFPROM_MAJOR_VERSION_SHIFT;
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minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
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QFPROM_MINOR_VERSION_SHIFT;
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if (major_version == 7 && minor_version == 8)
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priv->soc_data = &qfprom_7_8_data;
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priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
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if (IS_ERR(priv->vcc))
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return PTR_ERR(priv->vcc);
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priv->secclk = devm_clk_get(dev, "core");
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if (IS_ERR(priv->secclk)) {
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ret = PTR_ERR(priv->secclk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Error getting clock: %d\n", ret);
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return ret;
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}
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/* Only enable writing if we have SoC data. */
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if (priv->soc_data)
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econfig.reg_write = qfprom_reg_write;
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}
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nvmem = devm_nvmem_register(dev, &econfig);
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return PTR_ERR_OR_ZERO(nvmem);
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