ASoC: nau8822: add MCLK support
This change adds MCLK clock handling directly within driver. When used in combination with simple-audio-card, and mclk-fs is set, simple-audio-card will change MCLK frequency before configuring PLL. In some cases, however, MCLK reference clock should be static (see [1]), which means it needs to be moved away from simple-audio-card. [1]: https://lore.kernel.org/all/ZfBdxrzX3EnPuGOn@ediswmail9.ad.cirrus.com/ Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Link: https://msgid.link/r/20240613084652.13113-4-andrejs.cainikovs@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -14,6 +14,7 @@
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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@ -773,11 +774,26 @@ static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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{
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struct snd_soc_component *component = dai->component;
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struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
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unsigned long mclk_freq;
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nau8822->div_id = clk_id;
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nau8822->sysclk = freq;
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if (nau8822->mclk) {
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mclk_freq = clk_get_rate(nau8822->mclk);
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if (mclk_freq != freq) {
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int ret = nau8822_set_pll(dai, NAU8822_CLK_MCLK,
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NAU8822_CLK_MCLK, mclk_freq, freq);
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if (ret) {
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dev_err(component->dev, "Failed to set PLL\n");
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return ret;
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}
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nau8822->div_id = NAU8822_CLK_PLL;
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}
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}
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dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
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clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
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nau8822->div_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
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return 0;
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}
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@ -848,7 +864,7 @@ static int nau8822_hw_params(struct snd_pcm_substream *substream,
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{
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struct snd_soc_component *component = dai->component;
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struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
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int val_len = 0, val_rate = 0;
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int div = 0, val_len = 0, val_rate = 0;
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unsigned int ctrl_val, bclk_fs, bclk_div;
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/* make BCLK and LRC divide configuration if the codec as master. */
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@ -915,8 +931,10 @@ static int nau8822_hw_params(struct snd_pcm_substream *substream,
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/* If the master clock is from MCLK, provide the runtime FS for driver
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* to get the master clock prescaler configuration.
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*/
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if (nau8822->div_id == NAU8822_CLK_MCLK)
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nau8822_config_clkdiv(dai, 0, params_rate(params));
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if (nau8822->div_id != NAU8822_CLK_MCLK)
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div = nau8822->pll.mclk_scaler;
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nau8822_config_clkdiv(dai, div, params_rate(params));
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return 0;
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}
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@ -940,17 +958,34 @@ static int nau8822_mute(struct snd_soc_dai *dai, int mute, int direction)
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static int nau8822_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
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switch (level) {
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case SND_SOC_BIAS_ON:
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break;
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case SND_SOC_BIAS_PREPARE:
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if (nau8822->mclk &&
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snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON) {
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int ret = clk_prepare_enable(nau8822->mclk);
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if (ret) {
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dev_err(component->dev,
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"Failed to enable MCLK: %d\n", ret);
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return ret;
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}
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}
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snd_soc_component_update_bits(component,
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NAU8822_REG_POWER_MANAGEMENT_1,
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NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
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break;
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case SND_SOC_BIAS_STANDBY:
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if (nau8822->mclk &&
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snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_OFF)
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clk_disable_unprepare(nau8822->mclk);
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snd_soc_component_update_bits(component,
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NAU8822_REG_POWER_MANAGEMENT_1,
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NAU8822_IOBUF_EN | NAU8822_ABIAS_EN,
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@ -1127,6 +1162,11 @@ static int nau8822_i2c_probe(struct i2c_client *i2c)
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}
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i2c_set_clientdata(i2c, nau8822);
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nau8822->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
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if (IS_ERR(nau8822->mclk))
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return dev_err_probe(&i2c->dev, PTR_ERR(nau8822->mclk),
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"Error getting mclk\n");
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nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
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if (IS_ERR(nau8822->regmap)) {
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ret = PTR_ERR(nau8822->regmap);
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@ -215,6 +215,7 @@ struct nau8822_pll {
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struct nau8822 {
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struct device *dev;
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struct regmap *regmap;
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struct clk *mclk;
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struct nau8822_pll pll;
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int sysclk;
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int div_id;
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