ARM: p2v: reduce p2v alignment requirement to 2 MiB
The ARM kernel's linear map starts at PAGE_OFFSET, which maps to a physical address (PHYS_OFFSET) that is platform specific, and is discovered at boot. Since we don't want to slow down translations between physical and virtual addresses by keeping the offset in a variable in memory, we implement this by patching the code performing the translation, and putting the offset between PAGE_OFFSET and the start of physical RAM directly into the instruction opcodes. As we only patch up to 8 bits of offset, yielding 4 GiB >> 8 == 16 MiB of granularity, we have to round up PHYS_OFFSET to the next multiple if the start of physical RAM is not a multiple of 16 MiB. This wastes some physical RAM, since the memory that was skipped will now live below PAGE_OFFSET, making it inaccessible to the kernel. We can improve this by changing the patchable sequences and the patching logic to carry more bits of offset: 11 bits gives us 4 GiB >> 11 == 2 MiB of granularity, and so we will never waste more than that amount by rounding up the physical start of DRAM to the next multiple of 2 MiB. (Note that 2 MiB granularity guarantees that the linear mapping can be created efficiently, whereas less than 2 MiB may result in the linear mapping needing another level of page tables) This helps Zhen Lei's scenario, where the start of DRAM is known to be occupied. It also helps EFI boot, which relies on the firmware's page allocator to allocate space for the decompressed kernel as low as possible. And if the KASLR patches ever land for 32-bit, it will give us 3 more bits of randomization of the placement of the kernel inside the linear region. For the ARM code path, it simply comes down to using two add/sub instructions instead of one for the carryless version, and patching each of them with the correct immediate depending on the rotation field. For the LPAE calculation, which has to deal with a carry, it patches the MOVW instruction with up to 12 bits of offset (but we only need 11 bits anyway) For the Thumb2 code path, patching more than 11 bits of displacement would be somewhat cumbersome, but the 11 bits we need fit nicely into the second word of the u16[2] opcode, so we simply update the immediate assignment and the left shift to create an addend of the right magnitude. Suggested-by: Zhen Lei <thunder.leizhen@huawei.com> Acked-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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Ard Biesheuvel
parent
e8e00f5afb
commit
9443076e43
@ -243,7 +243,7 @@ config ARM_PATCH_PHYS_VIRT
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kernel in system memory.
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This can only be used with non-XIP MMU kernels where the base
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of physical memory is at a 16MB boundary.
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of physical memory is at a 2 MiB boundary.
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Only disable this option if you know that you do not require
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this feature (eg, building a kernel for a single machine) and
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@ -173,6 +173,7 @@ extern unsigned long vectors_base;
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* so that all we need to do is modify the 8-bit constant field.
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*/
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#define __PV_BITS_31_24 0x81000000
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#define __PV_BITS_23_16 0x810000
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#define __PV_BITS_7_0 0x81
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extern unsigned long __pv_phys_pfn_offset;
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@ -187,16 +188,18 @@ extern const void *__pv_table_begin, *__pv_table_end;
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#define __pv_stub(from,to,instr) \
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__asm__("@ __pv_stub\n" \
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"1: " instr " %0, %1, %2\n" \
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"2: " instr " %0, %0, %3\n" \
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" .pushsection .pv_table,\"a\"\n" \
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" .long 1b - .\n" \
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" .long 1b - ., 2b - .\n" \
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" .popsection\n" \
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: "=r" (to) \
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: "r" (from), "I" (__PV_BITS_31_24))
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: "r" (from), "I" (__PV_BITS_31_24), \
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"I"(__PV_BITS_23_16))
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#define __pv_add_carry_stub(x, y) \
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__asm__("@ __pv_add_carry_stub\n" \
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"0: movw %R0, #0\n" \
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" adds %Q0, %1, %R0, lsl #24\n" \
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" adds %Q0, %1, %R0, lsl #20\n" \
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"1: mov %R0, %2\n" \
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" adc %R0, %R0, #0\n" \
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" .pushsection .pv_table,\"a\"\n" \
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@ -210,7 +213,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
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#define __pv_stub(from,to,instr) \
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__asm__("@ __pv_stub\n" \
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"0: movw %0, #0\n" \
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" lsl %0, #24\n" \
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" lsl %0, #21\n" \
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" " instr " %0, %1, %0\n" \
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" .pushsection .pv_table,\"a\"\n" \
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" .long 0b - .\n" \
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@ -221,7 +224,7 @@ extern const void *__pv_table_begin, *__pv_table_end;
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#define __pv_add_carry_stub(x, y) \
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__asm__("@ __pv_add_carry_stub\n" \
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"0: movw %R0, #0\n" \
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" lsls %R0, #24\n" \
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" lsls %R0, #21\n" \
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" adds %Q0, %1, %R0\n" \
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"1: mvn %R0, #0\n" \
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" adc %R0, %R0, #0\n" \
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@ -21,7 +21,7 @@
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/*
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* __fixup_pv_table - patch the stub instructions with the delta between
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* PHYS_OFFSET and PAGE_OFFSET, which is assumed to be
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* 16MiB aligned.
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* 2 MiB aligned.
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*
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* Called from head.S, which expects the following registers to be preserved:
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* r1 = machine no, r2 = atags or dtb,
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@ -38,8 +38,8 @@ ENTRY(__fixup_pv_table)
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strcc ip, [r0, #HIGH_OFFSET] @ save to __pv_offset high bits
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str r3, [r0, #LOW_OFFSET] @ save to __pv_offset low bits
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mov r0, r3, lsr #24 @ constant for add/sub instructions
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teq r3, r0, lsl #24 @ must be 16MiB aligned
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mov r0, r3, lsr #21 @ constant for add/sub instructions
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teq r3, r0, lsl #21 @ must be 2 MiB aligned
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bne 0f
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adr_l r4, __pv_table_begin
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@ -55,22 +55,21 @@ __fixup_a_pv_table:
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adr_l r6, __pv_offset
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ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
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ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
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mov r6, r6, lsr #24
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cmn r0, #1
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#ifdef CONFIG_THUMB2_KERNEL
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@
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@ The Thumb-2 versions of the patchable sequences are
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@
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@ phys-to-virt: movw <reg>, #offset<31:24>
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@ lsl <reg>, #24
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@ phys-to-virt: movw <reg>, #offset<31:21>
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@ lsl <reg>, #21
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@ sub <VA>, <PA>, <reg>
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@
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@ virt-to-phys (non-LPAE): movw <reg>, #offset<31:24>
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@ lsl <reg>, #24
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@ virt-to-phys (non-LPAE): movw <reg>, #offset<31:21>
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@ lsl <reg>, #21
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@ add <PA>, <VA>, <reg>
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@
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@ virt-to-phys (LPAE): movw <reg>, #offset<31:24>
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@ lsl <reg>, #24
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@ virt-to-phys (LPAE): movw <reg>, #offset<31:21>
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@ lsl <reg>, #21
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@ adds <PAlo>, <VA>, <reg>
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@ mov <PAhi>, #offset<39:32>
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@ adc <PAhi>, <PAhi>, #0
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@ -102,6 +101,9 @@ __fixup_a_pv_table:
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@ +-----------+---+---------------------++---+------+----+------+
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@
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moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
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lsrs r3, r6, #29 @ isolate top 3 bits of displacement
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ubfx r6, r6, #21, #8 @ put bits 28:21 into the MOVW imm8 field
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bfi r6, r3, #12, #3 @ put bits 31:29 into the MOVW imm3 field
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b .Lnext
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.Lloop: add r7, r4
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adds r4, #4 @ clears Z flag
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@ -129,20 +131,24 @@ ARM_BE8(rev16 ip, ip)
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@ in BE8, we load data in BE, but instructions still in LE
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#define PV_BIT24 0x00000001
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#define PV_IMM8_MASK 0xff000000
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#define PV_IMMR_MSB 0x00080000
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#else
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#define PV_BIT24 0x01000000
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#define PV_IMM8_MASK 0x000000ff
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#define PV_IMMR_MSB 0x00000800
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#endif
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@
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@ The ARM versions of the patchable sequences are
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@
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@ phys-to-virt: sub <VA>, <PA>, #offset<31:24>, lsl #24
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@ sub <VA>, <PA>, #offset<23:16>, lsl #16
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@
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@ virt-to-phys (non-LPAE): add <PA>, <VA>, #offset<31:24>, lsl #24
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@ add <PA>, <VA>, #offset<23:16>, lsl #16
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@
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@ virt-to-phys (LPAE): movw <reg>, #offset<31:24>
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@ adds <PAlo>, <VA>, <reg>, lsl #24
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@ virt-to-phys (LPAE): movw <reg>, #offset<31:20>
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@ adds <PAlo>, <VA>, <reg>, lsl #20
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@ mov <PAhi>, #offset<39:32>
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@ adc <PAhi>, <PAhi>, #0
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@
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@ -174,6 +180,9 @@ ARM_BE8(rev16 ip, ip)
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@ +------+-----------------+------+------+-------+
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@
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moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
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mov r3, r6, lsr #16 @ put offset bits 31-16 into r3
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mov r6, r6, lsr #24 @ put offset bits 31-24 into r6
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and r3, r3, #0xf0 @ only keep offset bits 23-20 in r3
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b .Lnext
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.Lloop: ldr ip, [r7, r4]
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#ifdef CONFIG_ARM_LPAE
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@ -183,14 +192,17 @@ ARM_BE8(rev ip, ip)
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tst ip, #0xc00000 @ MOVW has bits 23:22 clear
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bic ip, ip, #0x400000 @ clear bit 22
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bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction
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orreq ip, ip, r6 @ MOVW -> mask in offset bits 31-24
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orreq ip, ip, r6, lsl #4 @ MOVW -> mask in offset bits 31-24
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orreq ip, ip, r3, lsr #4 @ MOVW -> mask in offset bits 23-20
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orrne ip, ip, r0 @ MOV -> mask in offset bits 7-0 (or bit 22)
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ARM_BE8(rev ip, ip)
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b 2f
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1:
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#endif
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tst ip, #PV_IMMR_MSB @ rotation value >= 16 ?
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bic ip, ip, #PV_IMM8_MASK
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orr ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24
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orreq ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24
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orrne ip, ip, r3 ARM_BE8(, lsl #24) @ mask in offset bits 23-20
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2:
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str ip, [r7, r4]
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add r4, r4, #4
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