iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/xe/rtp: Split action and entry flags

Browse Source 
Entry flags is meant for the whole entry, including the rule
evaluation. Action flags are for flags applied to the register or
action being taken. Since there's only one action per entry, the
distinction was not important and a u8 was spared. However more and more
workarounds are needing multiple actions. This prepares for multiple
action support.

Right now there are these action flags:

 - XE_RTP_ACTION_FLAG_MASKED_REG: register in the action is a masked
   register
 - XE_RTP_ACTION_FLAG_ENGINE_BASE: the engine base should be added to
   the register in order to form the real address

And this entry flag:

 - XE_RTP_ENTRY_FLAG_FOREACH_ENGINE: the rules should be evaluated for
   each engine on the gt. It also automatically implies
   XE_RTP_ACTION_FLAG_ENGINE_BASE.

Since there are likely not that many rules, reduce n_rules to u8 so the
overall entry size doesn't increase more than needed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-01-25 16:40:02 -08:00 committed by Rodrigo Vivi
parent 3747c88428
commit 944a5e993a
5 changed files with 80 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/xe/xe_reg_whitelist.c
View File

@ -42,7 +42,7 @@ static const struct xe_rtp_entry register_whitelist[] = {
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
XE_WHITELIST_REGISTER(RING_CTX_TIMESTAMP(0),
RING_FORCE_TO_NONPRIV_ACCESS_RD,
XE_RTP_FLAG(ENGINE_BASE))
XE_RTP_ACTION_FLAG(ENGINE_BASE))
},
{ XE_RTP_NAME("16014440446_part_1"),
XE_RTP_RULES(PLATFORM(PVC)),

38
drivers/gpu/drm/xe/xe_rtp.c
View File

@ -96,13 +96,30 @@ static void rtp_add_sr_entry(const struct xe_rtp_entry *entry,
.clr_bits = entry->action.clr_bits,
.set_bits = entry->action.set_bits,
.read_mask = entry->action.read_mask,
.masked_reg = entry->action.flags & XE_RTP_FLAG_MASKED_REG,
.masked_reg = entry->action.flags & XE_RTP_ACTION_FLAG_MASKED_REG,
.reg_type = entry->action.reg_type,
};
xe_reg_sr_add(sr, reg, &sr_entry);
}
static void rtp_process_one(const struct xe_rtp_entry *entry, struct xe_gt *gt,
struct xe_hw_engine *hwe, struct xe_reg_sr *sr)
{
u32 mmio_base;
if (!rule_matches(gt, hwe, entry))
return;
if ((entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) ||
(entry->action.flags & XE_RTP_ACTION_FLAG_ENGINE_BASE))
mmio_base = hwe->mmio_base;
else
mmio_base = 0;
rtp_add_sr_entry(entry, gt, mmio_base, sr);
}
/**
* xe_rtp_process - Process all rtp @entries, adding the matching ones to @sr
* @entries: Table with RTP definitions
@ -122,23 +139,14 @@ void xe_rtp_process(const struct xe_rtp_entry *entries, struct xe_reg_sr *sr,
const struct xe_rtp_entry *entry;
for (entry = entries; entry && entry->name; entry++) {
u32 mmio_base = 0;
if (entry->action.flags & XE_RTP_FLAG_FOREACH_ENGINE) {
if (entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {
struct xe_hw_engine *each_hwe;
enum xe_hw_engine_id id;
for_each_hw_engine(each_hwe, gt, id) {
mmio_base = each_hwe->mmio_base;
if (rule_matches(gt, each_hwe, entry))
rtp_add_sr_entry(entry, gt, mmio_base, sr);
}
} else if (rule_matches(gt, hwe, entry)) {
if (entry->action.flags & XE_RTP_FLAG_ENGINE_BASE)
mmio_base = hwe->mmio_base;
rtp_add_sr_entry(entry, gt, mmio_base, sr);
for_each_hw_engine(each_hwe, gt, id)
rtp_process_one(entry, gt, each_hwe, sr);
} else {
rtp_process_one(entry, gt, hwe, sr);
}
}
}

41
drivers/gpu/drm/xe/xe_rtp.h
View File

@ -53,7 +53,8 @@ struct xe_reg_sr;
* Helper macros for concatenating prefix - do not use them directly outside
* this header
*/
#define __ADD_XE_RTP_FLAG_PREFIX(x) CONCATENATE(XE_RTP_FLAG_, x) |
#define __ADD_XE_RTP_ENTRY_FLAG_PREFIX(x) CONCATENATE(XE_RTP_ENTRY_FLAG_, x) |
#define __ADD_XE_RTP_ACTION_FLAG_PREFIX(x) CONCATENATE(XE_RTP_ACTION_FLAG_, x) |
#define __ADD_XE_RTP_RULE_PREFIX(x) CONCATENATE(XE_RTP_RULE_, x) ,
/*
@ -287,26 +288,50 @@ struct xe_reg_sr;
#define XE_RTP_NAME(s_) .name = (s_)
/**
* XE_RTP_FLAG - Helper to add multiple flags to a struct xe_rtp_action entry
* @f1_: Last part of a ``XE_RTP_FLAG_*``
* XE_RTP_ENTRY_FLAG - Helper to add multiple flags to a struct xe_rtp_entry
* @f1_: Last part of a ``XE_RTP_ENTRY_FLAG_*``
* @...: Additional flags, defined like @f1_
*
* Helper to automatically add a ``XE_RTP_FLAG_`` prefix to @f1_ so it can be
* easily used to define struct xe_rtp_action entries. Example:
* Helper to automatically add a ``XE_RTP_ENTRY_FLAG_`` prefix to @f1_ so it can
* be easily used to define struct xe_rtp_action entries. Example:
*
* .. code-block:: c
*
* const struct xe_rtp_entry wa_entries[] = {
* ...
* { XE_RTP_NAME("test-entry"),
* XE_RTP_FLAG(FOREACH_ENGINE, MASKED_REG),
* ...
* XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
* ...
* },
* ...
* };
*/
#define XE_RTP_FLAG(f1_, ...) \
.flags = (CALL_FOR_EACH(__ADD_XE_RTP_FLAG_PREFIX, f1_, ##__VA_ARGS__) 0)
#define XE_RTP_ENTRY_FLAG(f1_, ...) \
.flags = (CALL_FOR_EACH(__ADD_XE_RTP_ENTRY_FLAG_PREFIX, f1_, ##__VA_ARGS__) 0)
/**
* XE_RTP_ACTION_FLAG - Helper to add multiple flags to a struct xe_rtp_action
* @f1_: Last part of a ``XE_RTP_ENTRY_*``
* @...: Additional flags, defined like @f1_
*
* Helper to automatically add a ``XE_RTP_ACTION_FLAG_`` prefix to @f1_ so it
* can be easily used to define struct xe_rtp_action entries. Example:
*
* .. code-block:: c
*
* const struct xe_rtp_entry wa_entries[] = {
* ...
* { XE_RTP_NAME("test-entry"),
* ...
* XE_RTP_SET(..., XE_RTP_ACTION_FLAG(FOREACH_ENGINE)),
* ...
* },
* ...
* };
*/
#define XE_RTP_ACTION_FLAG(f1_, ...) \
.flags = (CALL_FOR_EACH(__ADD_XE_RTP_ACTION_FLAG_PREFIX, f1_, ##__VA_ARGS__) 0)
/**
* XE_RTP_RULES - Helper to set multiple rules to a struct xe_rtp_entry entry

9
drivers/gpu/drm/xe/xe_rtp_types.h
View File

@ -34,9 +34,8 @@ struct xe_rtp_action {
#define XE_RTP_NOCHECK .read_mask = 0
/** @read_mask: mask for bits to consider when reading value back */
u32 read_mask;
#define XE_RTP_FLAG_FOREACH_ENGINE BIT(0)
#define XE_RTP_FLAG_MASKED_REG BIT(1)
#define XE_RTP_FLAG_ENGINE_BASE BIT(2)
#define XE_RTP_ACTION_FLAG_MASKED_REG BIT(0)
#define XE_RTP_ACTION_FLAG_ENGINE_BASE BIT(1)
/** @flags: flags to apply on rule evaluation or action */
u8 flags;
/** @reg_type: register type, see ``XE_RTP_REG_*`` */
@ -98,7 +97,9 @@ struct xe_rtp_entry {
const char *name;
const struct xe_rtp_action action;
const struct xe_rtp_rule *rules;
unsigned int n_rules;
u8 n_rules;
#define XE_RTP_ENTRY_FLAG_FOREACH_ENGINE BIT(0)
u8 flags;
};
#endif

36
drivers/gpu/drm/xe/xe_wa.c
View File

@ -103,15 +103,15 @@ static const struct xe_rtp_entry gt_was[] = {
XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
ENGINE_CLASS(VIDEO_DECODE),
FUNC(match_14011060649)),
XE_RTP_SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS,
XE_RTP_FLAG(FOREACH_ENGINE))
XE_RTP_SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS),
XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
},
{ XE_RTP_NAME("16010515920"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10),
STEP(A0, B0),
ENGINE_CLASS(VIDEO_DECODE)),
XE_RTP_SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS,
XE_RTP_FLAG(FOREACH_ENGINE))
XE_RTP_SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS),
XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
},
{ XE_RTP_NAME("22010523718"),
XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
@ -191,12 +191,12 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("14015227452"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("1606931601"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
XE_RTP_SET(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
@ -205,47 +205,47 @@ static const struct xe_rtp_entry engine_was[] = {
{ XE_RTP_NAME("14010826681, 1606700617, 22010271021"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
XE_RTP_SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("18019627453"),
XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
XE_RTP_SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("1409804808"),
XE_RTP_RULES(GRAPHICS_VERSION(1200),
ENGINE_CLASS(RENDER),
IS_INTEGRATED),
XE_RTP_SET(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("14010229206, 1409085225"),
XE_RTP_RULES(GRAPHICS_VERSION(1200),
ENGINE_CLASS(RENDER),
IS_INTEGRATED),
XE_RTP_SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
XE_RTP_SET(RING_PSMI_CTL(RENDER_RING_BASE),
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
GEN8_RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_FLAG(MASKED_REG))
GEN8_RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
XE_RTP_SET(RING_PSMI_CTL(RENDER_RING_BASE),
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
GEN8_RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_FLAG(MASKED_REG))
GEN8_RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("1406941453"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
XE_RTP_SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL, XE_RTP_FLAG(MASKED_REG))
XE_RTP_SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL, XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
XE_RTP_SET(GEN7_FF_SLICE_CS_CHICKEN1, GEN9_FFSC_PERCTX_PREEMPT_CTRL,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{}
};
@ -255,13 +255,13 @@ static const struct xe_rtp_entry lrc_was[] = {
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
XE_RTP_SET(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
XE_RTP_FIELD_SET(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("16011163337"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
@ -273,13 +273,13 @@ static const struct xe_rtp_entry lrc_was[] = {
XE_RTP_RULES(PLATFORM(DG1)),
XE_RTP_CLR(GEN11_COMMON_SLICE_CHICKEN3,
DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{ XE_RTP_NAME("22010493298"),
XE_RTP_RULES(PLATFORM(DG1)),
XE_RTP_SET(HIZ_CHICKEN,
DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
XE_RTP_FLAG(MASKED_REG))
XE_RTP_ACTION_FLAG(MASKED_REG))
},
{}
};