Merge git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
* git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog: [WATCHDOG] orion5x_wdt.c: add spinlocking [WATCHDOG] Orion: add hardware watchdog support [WATCHDOG] omap_wdt.c: cleanup a bit omap_wdt.c [WATCHDOG] omap_wdt.c: another ioremap() fix [WATCHDOG] omap_wdt.c: sync linux-omap changes [WATCHDOG] Add AT91SAM9X watchdog [WATCHDOG] Add driver for winbond w83697ug/uf watchdog feature [WATCHDOG] add watchdog driver IT8716 IT8726 IT8712J/K
This commit is contained in:
Linus Torvalds
commit
94a9f8ad33
@ -157,9 +157,11 @@
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#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
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#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
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#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
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#define WDT_RESET 0x0002
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#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
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#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
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#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
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#define WDT_INT_REQ 0x0008
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#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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@ -441,16 +441,8 @@ static inline void omap_init_uwire(void) {}
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#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
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#ifdef CONFIG_ARCH_OMAP24XX
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#define OMAP_WDT_BASE 0x48022000
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#else
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#define OMAP_WDT_BASE 0xfffeb000
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#endif
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static struct resource wdt_resources[] = {
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{
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.start = OMAP_WDT_BASE,
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.end = OMAP_WDT_BASE + 0x4f,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -464,6 +456,19 @@ static struct platform_device omap_wdt_device = {
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static void omap_init_wdt(void)
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{
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if (cpu_is_omap16xx())
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wdt_resources[0].start = 0xfffeb000;
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else if (cpu_is_omap2420())
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wdt_resources[0].start = 0x48022000; /* WDT2 */
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else if (cpu_is_omap2430())
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wdt_resources[0].start = 0x49016000; /* WDT2 */
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else if (cpu_is_omap343x())
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wdt_resources[0].start = 0x48314000; /* WDT2 */
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else
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return;
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wdt_resources[0].end = wdt_resources[0].start + 0x4f;
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(void) platform_device_register(&omap_wdt_device);
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}
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#else
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@ -66,6 +66,13 @@ config AT91RM9200_WATCHDOG
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Watchdog timer embedded into AT91RM9200 chips. This will reboot your
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system when the timeout is reached.
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config AT91SAM9X_WATCHDOG
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tristate "AT91SAM9X watchdog"
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depends on WATCHDOG && (ARCH_AT91SAM9260 || ARCH_AT91SAM9261)
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help
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Watchdog timer embedded into AT91SAM9X chips. This will reboot your
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system when the timeout is reached.
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config 21285_WATCHDOG
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tristate "DC21285 watchdog"
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depends on FOOTBRIDGE
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@ -217,6 +224,15 @@ config DAVINCI_WATCHDOG
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NOTE: once enabled, this timer cannot be disabled.
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Say N if you are unsure.
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config ORION5X_WATCHDOG
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tristate "Orion5x watchdog"
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depends on ARCH_ORION5X
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help
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Say Y here if to include support for the watchdog timer
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in the Orion5x ARM SoCs.
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To compile this driver as a module, choose M here: the
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module will be called orion5x_wdt.
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# ARM26 Architecture
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# AVR32 Architecture
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@ -416,6 +432,18 @@ config IT8712F_WDT
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To compile this driver as a module, choose M here: the
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module will be called it8712f_wdt.
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config IT87_WDT
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tristate "IT87 Watchdog Timer"
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depends on X86 && EXPERIMENTAL
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---help---
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This is the driver for the hardware watchdog on the ITE IT8716,
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IT8718, IT8726, IT8712(Version J,K) Super I/O chips. This watchdog
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simply watches your kernel to make sure it doesn't freeze, and if
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it does, it reboots your computer after a certain amount of time.
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To compile this driver as a module, choose M here: the module will
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be called it87_wdt.
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config HP_WATCHDOG
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tristate "HP Proliant iLO 2 Hardware Watchdog Timer"
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depends on X86
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@ -573,6 +601,21 @@ config W83697HF_WDT
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Most people will say N.
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config W83697UG_WDT
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tristate "W83697UG/W83697UF Watchdog Timer"
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depends on X86
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---help---
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This is the driver for the hardware watchdog on the W83697UG/UF
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chipset as used in MSI Fuzzy CX700 VIA motherboards (and likely others).
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This watchdog simply watches your kernel to make sure it doesn't
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freeze, and if it does, it reboots your computer after a certain
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amount of time.
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To compile this driver as a module, choose M here: the
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module will be called w83697ug_wdt.
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Most people will say N.
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config W83877F_WDT
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tristate "W83877F (EMACS) Watchdog Timer"
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depends on X86
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@ -26,6 +26,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
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# ARM Architecture
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obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
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obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
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obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
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obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
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obj-$(CONFIG_977_WATCHDOG) += wdt977.o
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@ -39,6 +40,7 @@ obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
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obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
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obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
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obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
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obj-$(CONFIG_ORION5X_WATCHDOG) += orion5x_wdt.o
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# ARM26 Architecture
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@ -71,6 +73,7 @@ ifeq ($(CONFIG_ITCO_VENDOR_SUPPORT),y)
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obj-$(CONFIG_ITCO_WDT) += iTCO_vendor_support.o
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endif
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obj-$(CONFIG_IT8712F_WDT) += it8712f_wdt.o
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obj-$(CONFIG_IT87_WDT) += it87_wdt.o
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obj-$(CONFIG_HP_WATCHDOG) += hpwdt.o
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obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
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obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
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@ -83,6 +86,7 @@ obj-$(CONFIG_CPU5_WDT) += cpu5wdt.o
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obj-$(CONFIG_SMSC37B787_WDT) += smsc37b787_wdt.o
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obj-$(CONFIG_W83627HF_WDT) += w83627hf_wdt.o
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obj-$(CONFIG_W83697HF_WDT) += w83697hf_wdt.o
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obj-$(CONFIG_W83697UG_WDT) += w83697ug_wdt.o
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obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
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obj-$(CONFIG_W83977F_WDT) += w83977f_wdt.o
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obj-$(CONFIG_MACHZ_WDT) += machzwd.o
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328
drivers/watchdog/at91sam9_wdt.c
Normal file
328
drivers/watchdog/at91sam9_wdt.c
Normal file
@ -0,0 +1,328 @@
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/*
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* Watchdog driver for Atmel AT91SAM9x processors.
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*
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* Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/*
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* The Watchdog Timer Mode Register can be only written to once. If the
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* timeout need to be set from Linux, be sure that the bootstrap or the
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* bootloader doesn't write to this register.
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*/
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#include <linux/errno.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#include <linux/jiffies.h>
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#include <linux/timer.h>
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#include <linux/bitops.h>
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#include <linux/uaccess.h>
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#include <asm/arch/at91_wdt.h>
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#define DRV_NAME "AT91SAM9 Watchdog"
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/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
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* use this to convert a watchdog
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* value from/to milliseconds.
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*/
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#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
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#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
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/* Hardware timeout in seconds */
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#define WDT_HW_TIMEOUT 2
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/* Timer heartbeat (500ms) */
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#define WDT_TIMEOUT (HZ/2)
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/* User land timeout */
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#define WDT_HEARTBEAT 15
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static int heartbeat = WDT_HEARTBEAT;
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
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"(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");
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static int nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, int, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
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"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static void at91_ping(unsigned long data);
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static struct {
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unsigned long next_heartbeat; /* the next_heartbeat for the timer */
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unsigned long open;
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char expect_close;
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struct timer_list timer; /* The timer that pings the watchdog */
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} at91wdt_private;
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/* ......................................................................... */
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/*
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* Reload the watchdog timer. (ie, pat the watchdog)
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*/
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static inline void at91_wdt_reset(void)
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{
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at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
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}
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/*
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* Timer tick
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*/
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static void at91_ping(unsigned long data)
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{
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if (time_before(jiffies, at91wdt_private.next_heartbeat) ||
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(!nowayout && !at91wdt_private.open)) {
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at91_wdt_reset();
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mod_timer(&at91wdt_private.timer, jiffies + WDT_TIMEOUT);
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} else
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printk(KERN_CRIT DRV_NAME": I will reset your machine !\n");
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}
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/*
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* Watchdog device is opened, and watchdog starts running.
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*/
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static int at91_wdt_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(0, &at91wdt_private.open))
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return -EBUSY;
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at91wdt_private.next_heartbeat = jiffies + heartbeat * HZ;
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mod_timer(&at91wdt_private.timer, jiffies + WDT_TIMEOUT);
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return nonseekable_open(inode, file);
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}
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/*
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* Close the watchdog device.
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*/
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static int at91_wdt_close(struct inode *inode, struct file *file)
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{
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clear_bit(0, &at91wdt_private.open);
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/* stop internal ping */
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if (!at91wdt_private.expect_close)
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del_timer(&at91wdt_private.timer);
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at91wdt_private.expect_close = 0;
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return 0;
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}
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/*
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* Set the watchdog time interval in 1/256Hz (write-once)
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* Counter is 12 bit.
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*/
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static int at91_wdt_settimeout(unsigned int timeout)
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{
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unsigned int reg;
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unsigned int mr;
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/* Check if disabled */
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mr = at91_sys_read(AT91_WDT_MR);
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if (mr & AT91_WDT_WDDIS) {
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printk(KERN_ERR DRV_NAME": sorry, watchdog is disabled\n");
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return -EIO;
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}
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/*
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* All counting occurs at SLOW_CLOCK / 128 = 256 Hz
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*
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* Since WDV is a 12-bit counter, the maximum period is
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* 4096 / 256 = 16 seconds.
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*/
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reg = AT91_WDT_WDRSTEN /* causes watchdog reset */
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/* | AT91_WDT_WDRPROC causes processor reset only */
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| AT91_WDT_WDDBGHLT /* disabled in debug mode */
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| AT91_WDT_WDD /* restart at any time */
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| (timeout & AT91_WDT_WDV); /* timer value */
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at91_sys_write(AT91_WDT_MR, reg);
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return 0;
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}
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static const struct watchdog_info at91_wdt_info = {
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.identity = DRV_NAME,
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
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};
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/*
|
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* Handle commands from user-space.
|
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*/
|
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static long at91_wdt_ioctl(struct file *file,
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unsigned int cmd, unsigned long arg)
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{
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void __user *argp = (void __user *)arg;
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int __user *p = argp;
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int new_value;
|
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switch (cmd) {
|
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case WDIOC_GETSUPPORT:
|
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return copy_to_user(argp, &at91_wdt_info,
|
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sizeof(at91_wdt_info)) ? -EFAULT : 0;
|
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|
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case WDIOC_GETSTATUS:
|
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case WDIOC_GETBOOTSTATUS:
|
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return put_user(0, p);
|
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|
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case WDIOC_KEEPALIVE:
|
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at91wdt_private.next_heartbeat = jiffies + heartbeat * HZ;
|
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return 0;
|
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|
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case WDIOC_SETTIMEOUT:
|
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if (get_user(new_value, p))
|
||||
return -EFAULT;
|
||||
|
||||
heartbeat = new_value;
|
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at91wdt_private.next_heartbeat = jiffies + heartbeat * HZ;
|
||||
|
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return put_user(new_value, p); /* return current value */
|
||||
|
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case WDIOC_GETTIMEOUT:
|
||||
return put_user(heartbeat, p);
|
||||
}
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
/*
|
||||
* Pat the watchdog whenever device is written to.
|
||||
*/
|
||||
static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len,
|
||||
loff_t *ppos)
|
||||
{
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
/* Scan for magic character */
|
||||
if (!nowayout) {
|
||||
size_t i;
|
||||
|
||||
at91wdt_private.expect_close = 0;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
char c;
|
||||
if (get_user(c, data + i))
|
||||
return -EFAULT;
|
||||
if (c == 'V') {
|
||||
at91wdt_private.expect_close = 42;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
at91wdt_private.next_heartbeat = jiffies + heartbeat * HZ;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/* ......................................................................... */
|
||||
|
||||
static const struct file_operations at91wdt_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = no_llseek,
|
||||
.unlocked_ioctl = at91_wdt_ioctl,
|
||||
.open = at91_wdt_open,
|
||||
.release = at91_wdt_close,
|
||||
.write = at91_wdt_write,
|
||||
};
|
||||
|
||||
static struct miscdevice at91wdt_miscdev = {
|
||||
.minor = WATCHDOG_MINOR,
|
||||
.name = "watchdog",
|
||||
.fops = &at91wdt_fops,
|
||||
};
|
||||
|
||||
static int __init at91wdt_probe(struct platform_device *pdev)
|
||||
{
|
||||
int res;
|
||||
|
||||
if (at91wdt_miscdev.parent)
|
||||
return -EBUSY;
|
||||
at91wdt_miscdev.parent = &pdev->dev;
|
||||
|
||||
/* Set watchdog */
|
||||
res = at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
res = misc_register(&at91wdt_miscdev);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
at91wdt_private.next_heartbeat = jiffies + heartbeat * HZ;
|
||||
setup_timer(&at91wdt_private.timer, at91_ping, 0);
|
||||
mod_timer(&at91wdt_private.timer, jiffies + WDT_TIMEOUT);
|
||||
|
||||
printk(KERN_INFO DRV_NAME " enabled (heartbeat=%d sec, nowayout=%d)\n",
|
||||
heartbeat, nowayout);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __exit at91wdt_remove(struct platform_device *pdev)
|
||||
{
|
||||
int res;
|
||||
|
||||
res = misc_deregister(&at91wdt_miscdev);
|
||||
if (!res)
|
||||
at91wdt_miscdev.parent = NULL;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int at91wdt_suspend(struct platform_device *pdev, pm_message_t message)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int at91wdt_resume(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#define at91wdt_suspend NULL
|
||||
#define at91wdt_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver at91wdt_driver = {
|
||||
.remove = __exit_p(at91wdt_remove),
|
||||
.suspend = at91wdt_suspend,
|
||||
.resume = at91wdt_resume,
|
||||
.driver = {
|
||||
.name = "at91_wdt",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init at91sam_wdt_init(void)
|
||||
{
|
||||
return platform_driver_probe(&at91wdt_driver, at91wdt_probe);
|
||||
}
|
||||
|
||||
static void __exit at91sam_wdt_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&at91wdt_driver);
|
||||
}
|
||||
|
||||
module_init(at91sam_wdt_init);
|
||||
module_exit(at91sam_wdt_exit);
|
||||
|
||||
MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
|
||||
MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
725
drivers/watchdog/it87_wdt.c
Normal file
725
drivers/watchdog/it87_wdt.c
Normal file
@ -0,0 +1,725 @@
|
||||
/*
|
||||
* Watchdog Timer Driver
|
||||
* for ITE IT87xx Environment Control - Low Pin Count Input / Output
|
||||
*
|
||||
* (c) Copyright 2007 Oliver Schuster <olivers137@aol.com>
|
||||
*
|
||||
* Based on softdog.c by Alan Cox,
|
||||
* 83977f_wdt.c by Jose Goncalves,
|
||||
* it87.c by Chris Gauthron, Jean Delvare
|
||||
*
|
||||
* Data-sheets: Publicly available at the ITE website
|
||||
* http://www.ite.com.tw/
|
||||
*
|
||||
* Support of the watchdog timers, which are available on
|
||||
* IT8716, IT8718, IT8726 and IT8712 (J,K version).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/watchdog.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
|
||||
#define WATCHDOG_VERSION "1.12"
|
||||
#define WATCHDOG_NAME "IT87 WDT"
|
||||
#define PFX WATCHDOG_NAME ": "
|
||||
#define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n"
|
||||
#define WD_MAGIC 'V'
|
||||
|
||||
/* Defaults for Module Parameter */
|
||||
#define DEFAULT_NOGAMEPORT 0
|
||||
#define DEFAULT_EXCLUSIVE 1
|
||||
#define DEFAULT_TIMEOUT 60
|
||||
#define DEFAULT_TESTMODE 0
|
||||
#define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT
|
||||
|
||||
/* IO Ports */
|
||||
#define REG 0x2e
|
||||
#define VAL 0x2f
|
||||
|
||||
/* Logical device Numbers LDN */
|
||||
#define GPIO 0x07
|
||||
#define GAMEPORT 0x09
|
||||
#define CIR 0x0a
|
||||
|
||||
/* Configuration Registers and Functions */
|
||||
#define LDNREG 0x07
|
||||
#define CHIPID 0x20
|
||||
#define CHIPREV 0x22
|
||||
#define ACTREG 0x30
|
||||
#define BASEREG 0x60
|
||||
|
||||
/* Chip Id numbers */
|
||||
#define NO_DEV_ID 0xffff
|
||||
#define IT8705_ID 0x8705
|
||||
#define IT8712_ID 0x8712
|
||||
#define IT8716_ID 0x8716
|
||||
#define IT8718_ID 0x8718
|
||||
#define IT8726_ID 0x8726 /* the data sheet suggest wrongly 0x8716 */
|
||||
|
||||
/* GPIO Configuration Registers LDN=0x07 */
|
||||
#define WDTCTRL 0x71
|
||||
#define WDTCFG 0x72
|
||||
#define WDTVALLSB 0x73
|
||||
#define WDTVALMSB 0x74
|
||||
|
||||
/* GPIO Bits WDTCTRL */
|
||||
#define WDT_CIRINT 0x80
|
||||
#define WDT_MOUSEINT 0x40
|
||||
#define WDT_KYBINT 0x20
|
||||
#define WDT_GAMEPORT 0x10 /* not it8718 */
|
||||
#define WDT_FORCE 0x02
|
||||
#define WDT_ZERO 0x01
|
||||
|
||||
/* GPIO Bits WDTCFG */
|
||||
#define WDT_TOV1 0x80
|
||||
#define WDT_KRST 0x40
|
||||
#define WDT_TOVE 0x20
|
||||
#define WDT_PWROK 0x10
|
||||
#define WDT_INT_MASK 0x0f
|
||||
|
||||
/* CIR Configuration Register LDN=0x0a */
|
||||
#define CIR_ILS 0x70
|
||||
|
||||
/* The default Base address is not always available, we use this */
|
||||
#define CIR_BASE 0x0208
|
||||
|
||||
/* CIR Controller */
|
||||
#define CIR_DR(b) (b)
|
||||
#define CIR_IER(b) (b + 1)
|
||||
#define CIR_RCR(b) (b + 2)
|
||||
#define CIR_TCR1(b) (b + 3)
|
||||
#define CIR_TCR2(b) (b + 4)
|
||||
#define CIR_TSR(b) (b + 5)
|
||||
#define CIR_RSR(b) (b + 6)
|
||||
#define CIR_BDLR(b) (b + 5)
|
||||
#define CIR_BDHR(b) (b + 6)
|
||||
#define CIR_IIR(b) (b + 7)
|
||||
|
||||
/* Default Base address of Game port */
|
||||
#define GP_BASE_DEFAULT 0x0201
|
||||
|
||||
/* wdt_status */
|
||||
#define WDTS_TIMER_RUN 0
|
||||
#define WDTS_DEV_OPEN 1
|
||||
#define WDTS_KEEPALIVE 2
|
||||
#define WDTS_LOCKED 3
|
||||
#define WDTS_USE_GP 4
|
||||
#define WDTS_EXPECTED 5
|
||||
|
||||
static unsigned int base, gpact, ciract;
|
||||
static unsigned long wdt_status;
|
||||
static DEFINE_SPINLOCK(spinlock);
|
||||
|
||||
static int nogameport = DEFAULT_NOGAMEPORT;
|
||||
static int exclusive = DEFAULT_EXCLUSIVE;
|
||||
static int timeout = DEFAULT_TIMEOUT;
|
||||
static int testmode = DEFAULT_TESTMODE;
|
||||
static int nowayout = DEFAULT_NOWAYOUT;
|
||||
|
||||
module_param(nogameport, int, 0);
|
||||
MODULE_PARM_DESC(nogameport, "Forbid the activation of game port, default="
|
||||
__MODULE_STRING(DEFAULT_NOGAMEPORT));
|
||||
module_param(exclusive, int, 0);
|
||||
MODULE_PARM_DESC(exclusive, "Watchdog exclusive device open, default="
|
||||
__MODULE_STRING(DEFAULT_EXCLUSIVE));
|
||||
module_param(timeout, int, 0);
|
||||
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default="
|
||||
__MODULE_STRING(DEFAULT_TIMEOUT));
|
||||
module_param(testmode, int, 0);
|
||||
MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default="
|
||||
__MODULE_STRING(DEFAULT_TESTMODE));
|
||||
module_param(nowayout, int, 0);
|
||||
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default="
|
||||
__MODULE_STRING(WATCHDOG_NOWAYOUT));
|
||||
|
||||
/* Superio Chip */
|
||||
|
||||
static inline void superio_enter(void)
|
||||
{
|
||||
outb(0x87, REG);
|
||||
outb(0x01, REG);
|
||||
outb(0x55, REG);
|
||||
outb(0x55, REG);
|
||||
}
|
||||
|
||||
static inline void superio_exit(void)
|
||||
{
|
||||
outb(0x02, REG);
|
||||
outb(0x02, VAL);
|
||||
}
|
||||
|
||||
static inline void superio_select(int ldn)
|
||||
{
|
||||
outb(LDNREG, REG);
|
||||
outb(ldn, VAL);
|
||||
}
|
||||
|
||||
static inline int superio_inb(int reg)
|
||||
{
|
||||
outb(reg, REG);
|
||||
return inb(VAL);
|
||||
}
|
||||
|
||||
static inline void superio_outb(int val, int reg)
|
||||
{
|
||||
outb(reg, REG);
|
||||
outb(val, VAL);
|
||||
}
|
||||
|
||||
static inline int superio_inw(int reg)
|
||||
{
|
||||
int val;
|
||||
outb(reg++, REG);
|
||||
val = inb(VAL) << 8;
|
||||
outb(reg, REG);
|
||||
val |= inb(VAL);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void superio_outw(int val, int reg)
|
||||
{
|
||||
outb(reg++, REG);
|
||||
outb(val >> 8, VAL);
|
||||
outb(reg, REG);
|
||||
outb(val, VAL);
|
||||
}
|
||||
|
||||
/* watchdog timer handling */
|
||||
|
||||
static void wdt_keepalive(void)
|
||||
{
|
||||
if (test_bit(WDTS_USE_GP, &wdt_status))
|
||||
inb(base);
|
||||
else
|
||||
/* The timer reloads with around 5 msec delay */
|
||||
outb(0x55, CIR_DR(base));
|
||||
set_bit(WDTS_KEEPALIVE, &wdt_status);
|
||||
}
|
||||
|
||||
static void wdt_start(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
|
||||
superio_select(GPIO);
|
||||
if (test_bit(WDTS_USE_GP, &wdt_status))
|
||||
superio_outb(WDT_GAMEPORT, WDTCTRL);
|
||||
else
|
||||
superio_outb(WDT_CIRINT, WDTCTRL);
|
||||
if (!testmode)
|
||||
superio_outb(WDT_TOV1 | WDT_KRST | WDT_PWROK, WDTCFG);
|
||||
else
|
||||
superio_outb(WDT_TOV1, WDTCFG);
|
||||
superio_outb(timeout>>8, WDTVALMSB);
|
||||
superio_outb(timeout, WDTVALLSB);
|
||||
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
|
||||
static void wdt_stop(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
|
||||
superio_select(GPIO);
|
||||
superio_outb(0x00, WDTCTRL);
|
||||
superio_outb(WDT_TOV1, WDTCFG);
|
||||
superio_outb(0x00, WDTVALMSB);
|
||||
superio_outb(0x00, WDTVALLSB);
|
||||
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* wdt_set_timeout - set a new timeout value with watchdog ioctl
|
||||
* @t: timeout value in seconds
|
||||
*
|
||||
* The hardware device has a 16 bit watchdog timer, thus the
|
||||
* timeout time ranges between 1 and 65535 seconds.
|
||||
*
|
||||
* Used within WDIOC_SETTIMEOUT watchdog device ioctl.
|
||||
*/
|
||||
|
||||
static int wdt_set_timeout(int t)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (t < 1 || t > 65535)
|
||||
return -EINVAL;
|
||||
|
||||
timeout = t;
|
||||
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
if (test_bit(WDTS_TIMER_RUN, &wdt_status)) {
|
||||
superio_enter();
|
||||
|
||||
superio_select(GPIO);
|
||||
superio_outb(t>>8, WDTVALMSB);
|
||||
superio_outb(t, WDTVALLSB);
|
||||
|
||||
superio_exit();
|
||||
}
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* wdt_get_status - determines the status supported by watchdog ioctl
|
||||
* @status: status returned to user space
|
||||
*
|
||||
* The status bit of the device does not allow to distinguish
|
||||
* between a regular system reset and a watchdog forced reset.
|
||||
* But, in test mode it is useful, so it is supported through
|
||||
* WDIOC_GETSTATUS watchdog ioctl. Additionally the driver
|
||||
* reports the keepalive signal and the acception of the magic.
|
||||
*
|
||||
* Used within WDIOC_GETSTATUS watchdog device ioctl.
|
||||
*/
|
||||
|
||||
static int wdt_get_status(int *status)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
*status = 0;
|
||||
if (testmode) {
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
superio_select(GPIO);
|
||||
if (superio_inb(WDTCTRL) & WDT_ZERO) {
|
||||
superio_outb(0x00, WDTCTRL);
|
||||
clear_bit(WDTS_TIMER_RUN, &wdt_status);
|
||||
*status |= WDIOF_CARDRESET;
|
||||
}
|
||||
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
if (test_and_clear_bit(WDTS_KEEPALIVE, &wdt_status))
|
||||
*status |= WDIOF_KEEPALIVEPING;
|
||||
if (test_bit(WDTS_EXPECTED, &wdt_status))
|
||||
*status |= WDIOF_MAGICCLOSE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* /dev/watchdog handling */
|
||||
|
||||
/**
|
||||
* wdt_open - watchdog file_operations .open
|
||||
* @inode: inode of the device
|
||||
* @file: file handle to the device
|
||||
*
|
||||
* The watchdog timer starts by opening the device.
|
||||
*
|
||||
* Used within the file operation of the watchdog device.
|
||||
*/
|
||||
|
||||
static int wdt_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (exclusive && test_and_set_bit(WDTS_DEV_OPEN, &wdt_status))
|
||||
return -EBUSY;
|
||||
if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) {
|
||||
if (nowayout && !test_and_set_bit(WDTS_LOCKED, &wdt_status))
|
||||
__module_get(THIS_MODULE);
|
||||
wdt_start();
|
||||
}
|
||||
return nonseekable_open(inode, file);
|
||||
}
|
||||
|
||||
/**
|
||||
* wdt_release - watchdog file_operations .release
|
||||
* @inode: inode of the device
|
||||
* @file: file handle to the device
|
||||
*
|
||||
* Closing the watchdog device either stops the watchdog timer
|
||||
* or in the case, that nowayout is set or the magic character
|
||||
* wasn't written, a critical warning about an running watchdog
|
||||
* timer is given.
|
||||
*
|
||||
* Used within the file operation of the watchdog device.
|
||||
*/
|
||||
|
||||
static int wdt_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (test_bit(WDTS_TIMER_RUN, &wdt_status)) {
|
||||
if (test_and_clear_bit(WDTS_EXPECTED, &wdt_status)) {
|
||||
wdt_stop();
|
||||
clear_bit(WDTS_TIMER_RUN, &wdt_status);
|
||||
} else {
|
||||
wdt_keepalive();
|
||||
printk(KERN_CRIT PFX
|
||||
"unexpected close, not stopping watchdog!\n");
|
||||
}
|
||||
}
|
||||
clear_bit(WDTS_DEV_OPEN, &wdt_status);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* wdt_write - watchdog file_operations .write
|
||||
* @file: file handle to the watchdog
|
||||
* @buf: buffer to write
|
||||
* @count: count of bytes
|
||||
* @ppos: pointer to the position to write. No seeks allowed
|
||||
*
|
||||
* A write to a watchdog device is defined as a keepalive signal. Any
|
||||
* write of data will do, as we don't define content meaning.
|
||||
*
|
||||
* Used within the file operation of the watchdog device.
|
||||
*/
|
||||
|
||||
static ssize_t wdt_write(struct file *file, const char __user *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
if (count) {
|
||||
clear_bit(WDTS_EXPECTED, &wdt_status);
|
||||
wdt_keepalive();
|
||||
}
|
||||
if (!nowayout) {
|
||||
size_t ofs;
|
||||
|
||||
/* note: just in case someone wrote the magic character long ago */
|
||||
for (ofs = 0; ofs != count; ofs++) {
|
||||
char c;
|
||||
if (get_user(c, buf + ofs))
|
||||
return -EFAULT;
|
||||
if (c == WD_MAGIC)
|
||||
set_bit(WDTS_EXPECTED, &wdt_status);
|
||||
}
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static struct watchdog_info ident = {
|
||||
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
|
||||
.firmware_version = 1,
|
||||
.identity = WATCHDOG_NAME,
|
||||
};
|
||||
|
||||
/**
|
||||
* wdt_ioctl - watchdog file_operations .unlocked_ioctl
|
||||
* @file: file handle to the device
|
||||
* @cmd: watchdog command
|
||||
* @arg: argument pointer
|
||||
*
|
||||
* The watchdog API defines a common set of functions for all watchdogs
|
||||
* according to their available features.
|
||||
*
|
||||
* Used within the file operation of the watchdog device.
|
||||
*/
|
||||
|
||||
static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int rc = 0, status, new_options, new_timeout;
|
||||
union {
|
||||
struct watchdog_info __user *ident;
|
||||
int __user *i;
|
||||
} uarg;
|
||||
|
||||
uarg.i = (int __user *)arg;
|
||||
|
||||
switch (cmd) {
|
||||
case WDIOC_GETSUPPORT:
|
||||
return copy_to_user(uarg.ident,
|
||||
&ident, sizeof(ident)) ? -EFAULT : 0;
|
||||
|
||||
case WDIOC_GETSTATUS:
|
||||
wdt_get_status(&status);
|
||||
return put_user(status, uarg.i);
|
||||
|
||||
case WDIOC_GETBOOTSTATUS:
|
||||
return put_user(0, uarg.i);
|
||||
|
||||
case WDIOC_KEEPALIVE:
|
||||
wdt_keepalive();
|
||||
return 0;
|
||||
|
||||
case WDIOC_SETOPTIONS:
|
||||
if (get_user(new_options, uarg.i))
|
||||
return -EFAULT;
|
||||
|
||||
switch (new_options) {
|
||||
case WDIOS_DISABLECARD:
|
||||
if (test_bit(WDTS_TIMER_RUN, &wdt_status))
|
||||
wdt_stop();
|
||||
clear_bit(WDTS_TIMER_RUN, &wdt_status);
|
||||
return 0;
|
||||
|
||||
case WDIOS_ENABLECARD:
|
||||
if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status))
|
||||
wdt_start();
|
||||
return 0;
|
||||
|
||||
default:
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
case WDIOC_SETTIMEOUT:
|
||||
if (get_user(new_timeout, uarg.i))
|
||||
return -EFAULT;
|
||||
rc = wdt_set_timeout(new_timeout);
|
||||
case WDIOC_GETTIMEOUT:
|
||||
if (put_user(timeout, uarg.i))
|
||||
return -EFAULT;
|
||||
return rc;
|
||||
|
||||
default:
|
||||
return -ENOTTY;
|
||||
}
|
||||
}
|
||||
|
||||
static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
|
||||
void *unused)
|
||||
{
|
||||
if (code == SYS_DOWN || code == SYS_HALT)
|
||||
wdt_stop();
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static const struct file_operations wdt_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = no_llseek,
|
||||
.write = wdt_write,
|
||||
.unlocked_ioctl = wdt_ioctl,
|
||||
.open = wdt_open,
|
||||
.release = wdt_release,
|
||||
};
|
||||
|
||||
static struct miscdevice wdt_miscdev = {
|
||||
.minor = WATCHDOG_MINOR,
|
||||
.name = "watchdog",
|
||||
.fops = &wdt_fops,
|
||||
};
|
||||
|
||||
static struct notifier_block wdt_notifier = {
|
||||
.notifier_call = wdt_notify_sys,
|
||||
};
|
||||
|
||||
static int __init it87_wdt_init(void)
|
||||
{
|
||||
int rc = 0;
|
||||
u16 chip_type;
|
||||
u8 chip_rev;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
chip_type = superio_inw(CHIPID);
|
||||
chip_rev = superio_inb(CHIPREV) & 0x0f;
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
|
||||
switch (chip_type) {
|
||||
case IT8716_ID:
|
||||
case IT8718_ID:
|
||||
case IT8726_ID:
|
||||
break;
|
||||
case IT8712_ID:
|
||||
if (chip_rev > 7)
|
||||
break;
|
||||
case IT8705_ID:
|
||||
printk(KERN_ERR PFX
|
||||
"Unsupported Chip found, Chip %04x Revision %02x\n",
|
||||
chip_type, chip_rev);
|
||||
return -ENODEV;
|
||||
case NO_DEV_ID:
|
||||
printk(KERN_ERR PFX "no device\n");
|
||||
return -ENODEV;
|
||||
default:
|
||||
printk(KERN_ERR PFX
|
||||
"Unknown Chip found, Chip %04x Revision %04x\n",
|
||||
chip_type, chip_rev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
|
||||
superio_select(GPIO);
|
||||
superio_outb(WDT_TOV1, WDTCFG);
|
||||
superio_outb(0x00, WDTCTRL);
|
||||
|
||||
/* First try to get Gameport support */
|
||||
if (chip_type != IT8718_ID && !nogameport) {
|
||||
superio_select(GAMEPORT);
|
||||
base = superio_inw(BASEREG);
|
||||
if (!base) {
|
||||
base = GP_BASE_DEFAULT;
|
||||
superio_outw(base, BASEREG);
|
||||
}
|
||||
gpact = superio_inb(ACTREG);
|
||||
superio_outb(0x01, ACTREG);
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
if (request_region(base, 1, WATCHDOG_NAME))
|
||||
set_bit(WDTS_USE_GP, &wdt_status);
|
||||
else
|
||||
rc = -EIO;
|
||||
} else {
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
|
||||
/* If we haven't Gameport support, try to get CIR support */
|
||||
if (!test_bit(WDTS_USE_GP, &wdt_status)) {
|
||||
if (!request_region(CIR_BASE, 8, WATCHDOG_NAME)) {
|
||||
if (rc == -EIO)
|
||||
printk(KERN_ERR PFX
|
||||
"I/O Address 0x%04x and 0x%04x"
|
||||
" already in use\n", base, CIR_BASE);
|
||||
else
|
||||
printk(KERN_ERR PFX
|
||||
"I/O Address 0x%04x already in use\n",
|
||||
CIR_BASE);
|
||||
rc = -EIO;
|
||||
goto err_out;
|
||||
}
|
||||
base = CIR_BASE;
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
|
||||
superio_select(CIR);
|
||||
superio_outw(base, BASEREG);
|
||||
superio_outb(0x00, CIR_ILS);
|
||||
ciract = superio_inb(ACTREG);
|
||||
superio_outb(0x01, ACTREG);
|
||||
if (rc == -EIO) {
|
||||
superio_select(GAMEPORT);
|
||||
superio_outb(gpact, ACTREG);
|
||||
}
|
||||
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
|
||||
if (timeout < 1 || timeout > 65535) {
|
||||
timeout = DEFAULT_TIMEOUT;
|
||||
printk(KERN_WARNING PFX
|
||||
"Timeout value out of range, use default %d sec\n",
|
||||
DEFAULT_TIMEOUT);
|
||||
}
|
||||
|
||||
rc = register_reboot_notifier(&wdt_notifier);
|
||||
if (rc) {
|
||||
printk(KERN_ERR PFX
|
||||
"Cannot register reboot notifier (err=%d)\n", rc);
|
||||
goto err_out_region;
|
||||
}
|
||||
|
||||
rc = misc_register(&wdt_miscdev);
|
||||
if (rc) {
|
||||
printk(KERN_ERR PFX
|
||||
"Cannot register miscdev on minor=%d (err=%d)\n",
|
||||
wdt_miscdev.minor, rc);
|
||||
goto err_out_reboot;
|
||||
}
|
||||
|
||||
/* Initialize CIR to use it as keepalive source */
|
||||
if (!test_bit(WDTS_USE_GP, &wdt_status)) {
|
||||
outb(0x00, CIR_RCR(base));
|
||||
outb(0xc0, CIR_TCR1(base));
|
||||
outb(0x5c, CIR_TCR2(base));
|
||||
outb(0x10, CIR_IER(base));
|
||||
outb(0x00, CIR_BDHR(base));
|
||||
outb(0x01, CIR_BDLR(base));
|
||||
outb(0x09, CIR_IER(base));
|
||||
}
|
||||
|
||||
printk(KERN_INFO PFX "Chip it%04x revision %d initialized. "
|
||||
"timeout=%d sec (nowayout=%d testmode=%d exclusive=%d "
|
||||
"nogameport=%d)\n", chip_type, chip_rev, timeout,
|
||||
nowayout, testmode, exclusive, nogameport);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out_reboot:
|
||||
unregister_reboot_notifier(&wdt_notifier);
|
||||
err_out_region:
|
||||
release_region(base, test_bit(WDTS_USE_GP, &wdt_status) ? 1 : 8);
|
||||
if (!test_bit(WDTS_USE_GP, &wdt_status)) {
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
superio_select(CIR);
|
||||
superio_outb(ciract, ACTREG);
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
err_out:
|
||||
if (chip_type != IT8718_ID && !nogameport) {
|
||||
spin_lock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
superio_select(GAMEPORT);
|
||||
superio_outb(gpact, ACTREG);
|
||||
superio_exit();
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __exit it87_wdt_exit(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
int nolock;
|
||||
|
||||
nolock = !spin_trylock_irqsave(&spinlock, flags);
|
||||
superio_enter();
|
||||
superio_select(GPIO);
|
||||
superio_outb(0x00, WDTCTRL);
|
||||
superio_outb(0x00, WDTCFG);
|
||||
superio_outb(0x00, WDTVALMSB);
|
||||
superio_outb(0x00, WDTVALLSB);
|
||||
if (test_bit(WDTS_USE_GP, &wdt_status)) {
|
||||
superio_select(GAMEPORT);
|
||||
superio_outb(gpact, ACTREG);
|
||||
} else {
|
||||
superio_select(CIR);
|
||||
superio_outb(ciract, ACTREG);
|
||||
}
|
||||
superio_exit();
|
||||
if (!nolock)
|
||||
spin_unlock_irqrestore(&spinlock, flags);
|
||||
|
||||
misc_deregister(&wdt_miscdev);
|
||||
unregister_reboot_notifier(&wdt_notifier);
|
||||
release_region(base, test_bit(WDTS_USE_GP, &wdt_status) ? 1 : 8);
|
||||
}
|
||||
|
||||
module_init(it87_wdt_init);
|
||||
module_exit(it87_wdt_exit);
|
||||
|
||||
MODULE_AUTHOR("Oliver Schuster");
|
||||
MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* linux/drivers/char/watchdog/omap_wdt.c
|
||||
* omap_wdt.c
|
||||
*
|
||||
* Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
|
||||
* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
|
||||
*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* <gdavis@mvista.com> or <source@mvista.com>
|
||||
@ -47,50 +47,68 @@
|
||||
|
||||
#include "omap_wdt.h"
|
||||
|
||||
static struct platform_device *omap_wdt_dev;
|
||||
|
||||
static unsigned timer_margin;
|
||||
module_param(timer_margin, uint, 0);
|
||||
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
|
||||
|
||||
static int omap_wdt_users;
|
||||
static struct clk *armwdt_ck;
|
||||
static struct clk *mpu_wdt_ick;
|
||||
static struct clk *mpu_wdt_fck;
|
||||
|
||||
static unsigned int wdt_trgr_pattern = 0x1234;
|
||||
static spinlock_t wdt_lock;
|
||||
|
||||
static void omap_wdt_ping(void)
|
||||
struct omap_wdt_dev {
|
||||
void __iomem *base; /* physical */
|
||||
struct device *dev;
|
||||
int omap_wdt_users;
|
||||
struct clk *armwdt_ck;
|
||||
struct clk *mpu_wdt_ick;
|
||||
struct clk *mpu_wdt_fck;
|
||||
struct resource *mem;
|
||||
struct miscdevice omap_wdt_miscdev;
|
||||
};
|
||||
|
||||
static void omap_wdt_ping(struct omap_wdt_dev *wdev)
|
||||
{
|
||||
void __iomem *base = wdev->base;
|
||||
|
||||
/* wait for posted write to complete */
|
||||
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
|
||||
while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
|
||||
cpu_relax();
|
||||
|
||||
wdt_trgr_pattern = ~wdt_trgr_pattern;
|
||||
omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
|
||||
__raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
|
||||
|
||||
/* wait for posted write to complete */
|
||||
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
|
||||
while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
|
||||
cpu_relax();
|
||||
/* reloaded WCRR from WLDR */
|
||||
}
|
||||
|
||||
static void omap_wdt_enable(void)
|
||||
static void omap_wdt_enable(struct omap_wdt_dev *wdev)
|
||||
{
|
||||
void __iomem *base = wdev->base;
|
||||
|
||||
/* Sequence to enable the watchdog */
|
||||
omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
|
||||
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
|
||||
__raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
|
||||
while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
|
||||
cpu_relax();
|
||||
omap_writel(0x4444, OMAP_WATCHDOG_SPR);
|
||||
while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
|
||||
|
||||
__raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
|
||||
while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static void omap_wdt_disable(void)
|
||||
static void omap_wdt_disable(struct omap_wdt_dev *wdev)
|
||||
{
|
||||
void __iomem *base = wdev->base;
|
||||
|
||||
/* sequence required to disable watchdog */
|
||||
omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
|
||||
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
|
||||
__raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
|
||||
cpu_relax();
|
||||
omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
|
||||
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
|
||||
|
||||
__raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
@ -103,83 +121,90 @@ static void omap_wdt_adjust_timeout(unsigned new_timeout)
|
||||
timer_margin = new_timeout;
|
||||
}
|
||||
|
||||
static void omap_wdt_set_timeout(void)
|
||||
static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
|
||||
{
|
||||
u32 pre_margin = GET_WLDR_VAL(timer_margin);
|
||||
void __iomem *base = wdev->base;
|
||||
|
||||
/* just count up at 32 KHz */
|
||||
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
|
||||
cpu_relax();
|
||||
omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
|
||||
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
|
||||
|
||||
__raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/*
|
||||
* Allow only one task to hold it open
|
||||
*/
|
||||
|
||||
static int omap_wdt_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
|
||||
struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
|
||||
void __iomem *base = wdev->base;
|
||||
|
||||
if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
|
||||
return -EBUSY;
|
||||
|
||||
if (cpu_is_omap16xx())
|
||||
clk_enable(armwdt_ck); /* Enable the clock */
|
||||
clk_enable(wdev->armwdt_ck); /* Enable the clock */
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
clk_enable(mpu_wdt_ick); /* Enable the interface clock */
|
||||
clk_enable(mpu_wdt_fck); /* Enable the functional clock */
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
||||
clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */
|
||||
clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */
|
||||
}
|
||||
|
||||
/* initialize prescaler */
|
||||
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
|
||||
cpu_relax();
|
||||
omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
|
||||
while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
|
||||
cpu_relax();
|
||||
|
||||
omap_wdt_set_timeout();
|
||||
omap_wdt_enable();
|
||||
__raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
|
||||
while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
|
||||
cpu_relax();
|
||||
|
||||
file->private_data = (void *) wdev;
|
||||
|
||||
omap_wdt_set_timeout(wdev);
|
||||
omap_wdt_enable(wdev);
|
||||
|
||||
return nonseekable_open(inode, file);
|
||||
}
|
||||
|
||||
static int omap_wdt_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct omap_wdt_dev *wdev = file->private_data;
|
||||
|
||||
/*
|
||||
* Shut off the timer unless NOWAYOUT is defined.
|
||||
*/
|
||||
#ifndef CONFIG_WATCHDOG_NOWAYOUT
|
||||
omap_wdt_disable();
|
||||
|
||||
if (cpu_is_omap16xx()) {
|
||||
clk_disable(armwdt_ck); /* Disable the clock */
|
||||
clk_put(armwdt_ck);
|
||||
armwdt_ck = NULL;
|
||||
}
|
||||
omap_wdt_disable(wdev);
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
clk_disable(mpu_wdt_ick); /* Disable the clock */
|
||||
clk_disable(mpu_wdt_fck); /* Disable the clock */
|
||||
clk_put(mpu_wdt_ick);
|
||||
clk_put(mpu_wdt_fck);
|
||||
mpu_wdt_ick = NULL;
|
||||
mpu_wdt_fck = NULL;
|
||||
if (cpu_is_omap16xx())
|
||||
clk_disable(wdev->armwdt_ck); /* Disable the clock */
|
||||
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
||||
clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */
|
||||
clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */
|
||||
}
|
||||
#else
|
||||
printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
|
||||
#endif
|
||||
omap_wdt_users = 0;
|
||||
wdev->omap_wdt_users = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t omap_wdt_write(struct file *file, const char __user *data,
|
||||
size_t len, loff_t *ppos)
|
||||
{
|
||||
struct omap_wdt_dev *wdev = file->private_data;
|
||||
|
||||
/* Refresh LOAD_TIME. */
|
||||
if (len) {
|
||||
spin_lock(&wdt_lock);
|
||||
omap_wdt_ping();
|
||||
omap_wdt_ping(wdev);
|
||||
spin_unlock(&wdt_lock);
|
||||
}
|
||||
return len;
|
||||
@ -188,6 +213,7 @@ static ssize_t omap_wdt_write(struct file *file, const char __user *data,
|
||||
static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct omap_wdt_dev *wdev;
|
||||
int new_margin;
|
||||
static const struct watchdog_info ident = {
|
||||
.identity = "OMAP Watchdog",
|
||||
@ -195,6 +221,8 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
.firmware_version = 0,
|
||||
};
|
||||
|
||||
wdev = file->private_data;
|
||||
|
||||
switch (cmd) {
|
||||
case WDIOC_GETSUPPORT:
|
||||
return copy_to_user((struct watchdog_info __user *)arg, &ident,
|
||||
@ -203,14 +231,14 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
return put_user(0, (int __user *)arg);
|
||||
case WDIOC_GETBOOTSTATUS:
|
||||
if (cpu_is_omap16xx())
|
||||
return put_user(omap_readw(ARM_SYSST),
|
||||
return put_user(__raw_readw(ARM_SYSST),
|
||||
(int __user *)arg);
|
||||
if (cpu_is_omap24xx())
|
||||
return put_user(omap_prcm_get_reset_sources(),
|
||||
(int __user *)arg);
|
||||
case WDIOC_KEEPALIVE:
|
||||
spin_lock(&wdt_lock);
|
||||
omap_wdt_ping();
|
||||
omap_wdt_ping(wdev);
|
||||
spin_unlock(&wdt_lock);
|
||||
return 0;
|
||||
case WDIOC_SETTIMEOUT:
|
||||
@ -219,11 +247,11 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
omap_wdt_adjust_timeout(new_margin);
|
||||
|
||||
spin_lock(&wdt_lock);
|
||||
omap_wdt_disable();
|
||||
omap_wdt_set_timeout();
|
||||
omap_wdt_enable();
|
||||
omap_wdt_disable(wdev);
|
||||
omap_wdt_set_timeout(wdev);
|
||||
omap_wdt_enable(wdev);
|
||||
|
||||
omap_wdt_ping();
|
||||
omap_wdt_ping(wdev);
|
||||
spin_unlock(&wdt_lock);
|
||||
/* Fall */
|
||||
case WDIOC_GETTIMEOUT:
|
||||
@ -241,96 +269,173 @@ static const struct file_operations omap_wdt_fops = {
|
||||
.release = omap_wdt_release,
|
||||
};
|
||||
|
||||
static struct miscdevice omap_wdt_miscdev = {
|
||||
.minor = WATCHDOG_MINOR,
|
||||
.name = "watchdog",
|
||||
.fops = &omap_wdt_fops,
|
||||
};
|
||||
|
||||
static int __init omap_wdt_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res, *mem;
|
||||
struct omap_wdt_dev *wdev;
|
||||
int ret;
|
||||
|
||||
/* reserve static register mappings */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENOENT;
|
||||
if (!res) {
|
||||
ret = -ENOENT;
|
||||
goto err_get_resource;
|
||||
}
|
||||
|
||||
if (omap_wdt_dev) {
|
||||
ret = -EBUSY;
|
||||
goto err_busy;
|
||||
}
|
||||
|
||||
mem = request_mem_region(res->start, res->end - res->start + 1,
|
||||
pdev->name);
|
||||
if (mem == NULL)
|
||||
return -EBUSY;
|
||||
if (!mem) {
|
||||
ret = -EBUSY;
|
||||
goto err_busy;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, mem);
|
||||
wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
|
||||
if (!wdev) {
|
||||
ret = -ENOMEM;
|
||||
goto err_kzalloc;
|
||||
}
|
||||
|
||||
omap_wdt_users = 0;
|
||||
wdev->omap_wdt_users = 0;
|
||||
wdev->mem = mem;
|
||||
|
||||
if (cpu_is_omap16xx()) {
|
||||
armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
|
||||
if (IS_ERR(armwdt_ck)) {
|
||||
ret = PTR_ERR(armwdt_ck);
|
||||
armwdt_ck = NULL;
|
||||
goto fail;
|
||||
wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
|
||||
if (IS_ERR(wdev->armwdt_ck)) {
|
||||
ret = PTR_ERR(wdev->armwdt_ck);
|
||||
wdev->armwdt_ck = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
|
||||
if (IS_ERR(mpu_wdt_ick)) {
|
||||
ret = PTR_ERR(mpu_wdt_ick);
|
||||
mpu_wdt_ick = NULL;
|
||||
goto fail;
|
||||
wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
|
||||
if (IS_ERR(wdev->mpu_wdt_ick)) {
|
||||
ret = PTR_ERR(wdev->mpu_wdt_ick);
|
||||
wdev->mpu_wdt_ick = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
|
||||
if (IS_ERR(mpu_wdt_fck)) {
|
||||
ret = PTR_ERR(mpu_wdt_fck);
|
||||
mpu_wdt_fck = NULL;
|
||||
goto fail;
|
||||
wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
|
||||
if (IS_ERR(wdev->mpu_wdt_fck)) {
|
||||
ret = PTR_ERR(wdev->mpu_wdt_fck);
|
||||
wdev->mpu_wdt_fck = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
}
|
||||
|
||||
omap_wdt_disable();
|
||||
if (cpu_is_omap34xx()) {
|
||||
wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick");
|
||||
if (IS_ERR(wdev->mpu_wdt_ick)) {
|
||||
ret = PTR_ERR(wdev->mpu_wdt_ick);
|
||||
wdev->mpu_wdt_ick = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck");
|
||||
if (IS_ERR(wdev->mpu_wdt_fck)) {
|
||||
ret = PTR_ERR(wdev->mpu_wdt_fck);
|
||||
wdev->mpu_wdt_fck = NULL;
|
||||
goto err_clk;
|
||||
}
|
||||
}
|
||||
wdev->base = ioremap(res->start, res->end - res->start + 1);
|
||||
if (!wdev->base) {
|
||||
ret = -ENOMEM;
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, wdev);
|
||||
|
||||
omap_wdt_disable(wdev);
|
||||
omap_wdt_adjust_timeout(timer_margin);
|
||||
|
||||
omap_wdt_miscdev.parent = &pdev->dev;
|
||||
ret = misc_register(&omap_wdt_miscdev);
|
||||
if (ret)
|
||||
goto fail;
|
||||
wdev->omap_wdt_miscdev.parent = &pdev->dev;
|
||||
wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
|
||||
wdev->omap_wdt_miscdev.name = "watchdog";
|
||||
wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
|
||||
|
||||
pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
|
||||
ret = misc_register(&(wdev->omap_wdt_miscdev));
|
||||
if (ret)
|
||||
goto err_misc;
|
||||
|
||||
pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
|
||||
__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
|
||||
timer_margin);
|
||||
|
||||
/* autogate OCP interface clock */
|
||||
omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
|
||||
__raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
|
||||
|
||||
omap_wdt_dev = pdev;
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (armwdt_ck)
|
||||
clk_put(armwdt_ck);
|
||||
if (mpu_wdt_ick)
|
||||
clk_put(mpu_wdt_ick);
|
||||
if (mpu_wdt_fck)
|
||||
clk_put(mpu_wdt_fck);
|
||||
release_resource(mem);
|
||||
err_misc:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
iounmap(wdev->base);
|
||||
|
||||
err_ioremap:
|
||||
wdev->base = NULL;
|
||||
|
||||
err_clk:
|
||||
if (wdev->armwdt_ck)
|
||||
clk_put(wdev->armwdt_ck);
|
||||
if (wdev->mpu_wdt_ick)
|
||||
clk_put(wdev->mpu_wdt_ick);
|
||||
if (wdev->mpu_wdt_fck)
|
||||
clk_put(wdev->mpu_wdt_fck);
|
||||
kfree(wdev);
|
||||
|
||||
err_kzalloc:
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
|
||||
err_busy:
|
||||
err_get_resource:
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void omap_wdt_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
omap_wdt_disable();
|
||||
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
|
||||
|
||||
if (wdev->omap_wdt_users)
|
||||
omap_wdt_disable(wdev);
|
||||
}
|
||||
|
||||
static int omap_wdt_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *mem = platform_get_drvdata(pdev);
|
||||
misc_deregister(&omap_wdt_miscdev);
|
||||
release_resource(mem);
|
||||
if (armwdt_ck)
|
||||
clk_put(armwdt_ck);
|
||||
if (mpu_wdt_ick)
|
||||
clk_put(mpu_wdt_ick);
|
||||
if (mpu_wdt_fck)
|
||||
clk_put(mpu_wdt_fck);
|
||||
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
if (!res)
|
||||
return -ENOENT;
|
||||
|
||||
misc_deregister(&(wdev->omap_wdt_miscdev));
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
if (wdev->armwdt_ck) {
|
||||
clk_put(wdev->armwdt_ck);
|
||||
wdev->armwdt_ck = NULL;
|
||||
}
|
||||
|
||||
if (wdev->mpu_wdt_ick) {
|
||||
clk_put(wdev->mpu_wdt_ick);
|
||||
wdev->mpu_wdt_ick = NULL;
|
||||
}
|
||||
|
||||
if (wdev->mpu_wdt_fck) {
|
||||
clk_put(wdev->mpu_wdt_fck);
|
||||
wdev->mpu_wdt_fck = NULL;
|
||||
}
|
||||
iounmap(wdev->base);
|
||||
|
||||
kfree(wdev);
|
||||
omap_wdt_dev = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -344,17 +449,23 @@ static int omap_wdt_remove(struct platform_device *pdev)
|
||||
|
||||
static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
if (omap_wdt_users)
|
||||
omap_wdt_disable();
|
||||
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
|
||||
|
||||
if (wdev->omap_wdt_users)
|
||||
omap_wdt_disable(wdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_wdt_resume(struct platform_device *pdev)
|
||||
{
|
||||
if (omap_wdt_users) {
|
||||
omap_wdt_enable();
|
||||
omap_wdt_ping();
|
||||
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
|
||||
|
||||
if (wdev->omap_wdt_users) {
|
||||
omap_wdt_enable(wdev);
|
||||
omap_wdt_ping(wdev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -30,25 +30,15 @@
|
||||
#ifndef _OMAP_WATCHDOG_H
|
||||
#define _OMAP_WATCHDOG_H
|
||||
|
||||
#define OMAP1610_WATCHDOG_BASE 0xfffeb000
|
||||
#define OMAP2420_WATCHDOG_BASE 0x48022000 /*WDT Timer 2 */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
#define OMAP_WATCHDOG_BASE OMAP2420_WATCHDOG_BASE
|
||||
#else
|
||||
#define OMAP_WATCHDOG_BASE OMAP1610_WATCHDOG_BASE
|
||||
#define RM_RSTST_WKUP 0
|
||||
#endif
|
||||
|
||||
#define OMAP_WATCHDOG_REV (OMAP_WATCHDOG_BASE + 0x00)
|
||||
#define OMAP_WATCHDOG_SYS_CONFIG (OMAP_WATCHDOG_BASE + 0x10)
|
||||
#define OMAP_WATCHDOG_STATUS (OMAP_WATCHDOG_BASE + 0x14)
|
||||
#define OMAP_WATCHDOG_CNTRL (OMAP_WATCHDOG_BASE + 0x24)
|
||||
#define OMAP_WATCHDOG_CRR (OMAP_WATCHDOG_BASE + 0x28)
|
||||
#define OMAP_WATCHDOG_LDR (OMAP_WATCHDOG_BASE + 0x2c)
|
||||
#define OMAP_WATCHDOG_TGR (OMAP_WATCHDOG_BASE + 0x30)
|
||||
#define OMAP_WATCHDOG_WPS (OMAP_WATCHDOG_BASE + 0x34)
|
||||
#define OMAP_WATCHDOG_SPR (OMAP_WATCHDOG_BASE + 0x48)
|
||||
#define OMAP_WATCHDOG_REV (0x00)
|
||||
#define OMAP_WATCHDOG_SYS_CONFIG (0x10)
|
||||
#define OMAP_WATCHDOG_STATUS (0x14)
|
||||
#define OMAP_WATCHDOG_CNTRL (0x24)
|
||||
#define OMAP_WATCHDOG_CRR (0x28)
|
||||
#define OMAP_WATCHDOG_LDR (0x2c)
|
||||
#define OMAP_WATCHDOG_TGR (0x30)
|
||||
#define OMAP_WATCHDOG_WPS (0x34)
|
||||
#define OMAP_WATCHDOG_SPR (0x48)
|
||||
|
||||
/* Using the prescaler, the OMAP watchdog could go for many
|
||||
* months before firing. These limits work without scaling,
|
||||
|
||||
245
drivers/watchdog/orion5x_wdt.c
Normal file
245
drivers/watchdog/orion5x_wdt.c
Normal file
@ -0,0 +1,245 @@
|
||||
/*
|
||||
* drivers/watchdog/orion5x_wdt.c
|
||||
*
|
||||
* Watchdog driver for Orion5x processors
|
||||
*
|
||||
* Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/watchdog.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
/*
|
||||
* Watchdog timer block registers.
|
||||
*/
|
||||
#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
|
||||
#define WDT_EN 0x0010
|
||||
#define WDT_VAL (TIMER_VIRT_BASE + 0x0024)
|
||||
|
||||
#define WDT_MAX_DURATION (0xffffffff / ORION5X_TCLK)
|
||||
#define WDT_IN_USE 0
|
||||
#define WDT_OK_TO_CLOSE 1
|
||||
|
||||
static int nowayout = WATCHDOG_NOWAYOUT;
|
||||
static int heartbeat = WDT_MAX_DURATION; /* (seconds) */
|
||||
static unsigned long wdt_status;
|
||||
static spinlock_t wdt_lock;
|
||||
|
||||
static void wdt_enable(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
spin_lock(&wdt_lock);
|
||||
|
||||
/* Set watchdog duration */
|
||||
writel(ORION5X_TCLK * heartbeat, WDT_VAL);
|
||||
|
||||
/* Clear watchdog timer interrupt */
|
||||
reg = readl(BRIDGE_CAUSE);
|
||||
reg &= ~WDT_INT_REQ;
|
||||
writel(reg, BRIDGE_CAUSE);
|
||||
|
||||
/* Enable watchdog timer */
|
||||
reg = readl(TIMER_CTRL);
|
||||
reg |= WDT_EN;
|
||||
writel(reg, TIMER_CTRL);
|
||||
|
||||
/* Enable reset on watchdog */
|
||||
reg = readl(CPU_RESET_MASK);
|
||||
reg |= WDT_RESET;
|
||||
writel(reg, CPU_RESET_MASK);
|
||||
|
||||
spin_unlock(&wdt_lock);
|
||||
}
|
||||
|
||||
static void wdt_disable(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
spin_lock(&wdt_lock);
|
||||
|
||||
/* Disable reset on watchdog */
|
||||
reg = readl(CPU_RESET_MASK);
|
||||
reg &= ~WDT_RESET;
|
||||
writel(reg, CPU_RESET_MASK);
|
||||
|
||||
/* Disable watchdog timer */
|
||||
reg = readl(TIMER_CTRL);
|
||||
reg &= ~WDT_EN;
|
||||
writel(reg, TIMER_CTRL);
|
||||
|
||||
spin_unlock(&wdt_lock);
|
||||
}
|
||||
|
||||
static int orion5x_wdt_get_timeleft(int *time_left)
|
||||
{
|
||||
spin_lock(&wdt_lock);
|
||||
*time_left = readl(WDT_VAL) / ORION5X_TCLK;
|
||||
spin_unlock(&wdt_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int orion5x_wdt_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (test_and_set_bit(WDT_IN_USE, &wdt_status))
|
||||
return -EBUSY;
|
||||
clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
|
||||
wdt_enable();
|
||||
return nonseekable_open(inode, file);
|
||||
}
|
||||
|
||||
static ssize_t orion5x_wdt_write(struct file *file, const char *data,
|
||||
size_t len, loff_t *ppos)
|
||||
{
|
||||
if (len) {
|
||||
if (!nowayout) {
|
||||
size_t i;
|
||||
|
||||
clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
|
||||
for (i = 0; i != len; i++) {
|
||||
char c;
|
||||
|
||||
if (get_user(c, data + i))
|
||||
return -EFAULT;
|
||||
if (c == 'V')
|
||||
set_bit(WDT_OK_TO_CLOSE, &wdt_status);
|
||||
}
|
||||
}
|
||||
wdt_enable();
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
static struct watchdog_info ident = {
|
||||
.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT |
|
||||
WDIOF_KEEPALIVEPING,
|
||||
.identity = "Orion5x Watchdog",
|
||||
};
|
||||
|
||||
|
||||
static long orion5x_wdt_ioctl(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
int ret = -ENOTTY;
|
||||
int time;
|
||||
|
||||
switch (cmd) {
|
||||
case WDIOC_GETSUPPORT:
|
||||
ret = copy_to_user((struct watchdog_info *)arg, &ident,
|
||||
sizeof(ident)) ? -EFAULT : 0;
|
||||
break;
|
||||
|
||||
case WDIOC_GETSTATUS:
|
||||
case WDIOC_GETBOOTSTATUS:
|
||||
ret = put_user(0, (int *)arg);
|
||||
break;
|
||||
|
||||
case WDIOC_KEEPALIVE:
|
||||
wdt_enable();
|
||||
ret = 0;
|
||||
break;
|
||||
|
||||
case WDIOC_SETTIMEOUT:
|
||||
ret = get_user(time, (int *)arg);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
if (time <= 0 || time > WDT_MAX_DURATION) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
heartbeat = time;
|
||||
wdt_enable();
|
||||
/* Fall through */
|
||||
|
||||
case WDIOC_GETTIMEOUT:
|
||||
ret = put_user(heartbeat, (int *)arg);
|
||||
break;
|
||||
|
||||
case WDIOC_GETTIMELEFT:
|
||||
if (orion5x_wdt_get_timeleft(&time)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
ret = put_user(time, (int *)arg);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int orion5x_wdt_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (test_bit(WDT_OK_TO_CLOSE, &wdt_status))
|
||||
wdt_disable();
|
||||
else
|
||||
printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - "
|
||||
"timer will not stop\n");
|
||||
clear_bit(WDT_IN_USE, &wdt_status);
|
||||
clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct file_operations orion5x_wdt_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = no_llseek,
|
||||
.write = orion5x_wdt_write,
|
||||
.unlocked_ioctl = orion5x_wdt_ioctl,
|
||||
.open = orion5x_wdt_open,
|
||||
.release = orion5x_wdt_release,
|
||||
};
|
||||
|
||||
static struct miscdevice orion5x_wdt_miscdev = {
|
||||
.minor = WATCHDOG_MINOR,
|
||||
.name = "watchdog",
|
||||
.fops = &orion5x_wdt_fops,
|
||||
};
|
||||
|
||||
static int __init orion5x_wdt_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
spin_lock_init(&wdt_lock);
|
||||
|
||||
ret = misc_register(&orion5x_wdt_miscdev);
|
||||
if (ret == 0)
|
||||
printk("Orion5x Watchdog Timer: heartbeat %d sec\n",
|
||||
heartbeat);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit orion5x_wdt_exit(void)
|
||||
{
|
||||
misc_deregister(&orion5x_wdt_miscdev);
|
||||
}
|
||||
|
||||
module_init(orion5x_wdt_init);
|
||||
module_exit(orion5x_wdt_exit);
|
||||
|
||||
MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>");
|
||||
MODULE_DESCRIPTION("Orion5x Processor Watchdog");
|
||||
|
||||
module_param(heartbeat, int, 0);
|
||||
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds (default is "
|
||||
__MODULE_STRING(WDT_MAX_DURATION) ")");
|
||||
|
||||
module_param(nowayout, int, 0);
|
||||
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
392
drivers/watchdog/w83697ug_wdt.c
Normal file
392
drivers/watchdog/w83697ug_wdt.c
Normal file
@ -0,0 +1,392 @@
|
||||
/*
|
||||
* w83697ug/uf WDT driver
|
||||
*
|
||||
* (c) Copyright 2008 Flemming Fransen <ff@nrvissing.net>
|
||||
* reused original code to supoprt w83697ug/uf.
|
||||
*
|
||||
* Based on w83627hf_wdt.c which is based on advantechwdt.c
|
||||
* which is based on wdt.c.
|
||||
* Original copyright messages:
|
||||
*
|
||||
* (c) Copyright 2007 Vlad Drukker <vlad@storewiz.com>
|
||||
* added support for W83627THF.
|
||||
*
|
||||
* (c) Copyright 2003 Pádraig Brady <P@draigBrady.com>
|
||||
*
|
||||
* (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
|
||||
*
|
||||
* (c) Copyright 1996 Alan Cox <alan@redhat.com>, All Rights Reserved.
|
||||
* http://www.redhat.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
|
||||
* warranty for any of this software. This material is provided
|
||||
* "AS-IS" and at no charge.
|
||||
*
|
||||
* (c) Copyright 1995 Alan Cox <alan@redhat.com>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/watchdog.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
|
||||
#define WATCHDOG_NAME "w83697ug/uf WDT"
|
||||
#define PFX WATCHDOG_NAME ": "
|
||||
#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
|
||||
|
||||
static unsigned long wdt_is_open;
|
||||
static char expect_close;
|
||||
static DEFINE_SPINLOCK(io_lock);
|
||||
|
||||
static int wdt_io = 0x2e;
|
||||
module_param(wdt_io, int, 0);
|
||||
MODULE_PARM_DESC(wdt_io, "w83697ug/uf WDT io port (default 0x2e)");
|
||||
|
||||
static int timeout = WATCHDOG_TIMEOUT; /* in seconds */
|
||||
module_param(timeout, int, 0);
|
||||
MODULE_PARM_DESC(timeout,
|
||||
"Watchdog timeout in seconds. 1<= timeout <=255 (default="
|
||||
__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
|
||||
|
||||
static int nowayout = WATCHDOG_NOWAYOUT;
|
||||
module_param(nowayout, int, 0);
|
||||
MODULE_PARM_DESC(nowayout,
|
||||
"Watchdog cannot be stopped once started (default="
|
||||
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
|
||||
|
||||
/*
|
||||
* Kernel methods.
|
||||
*/
|
||||
|
||||
#define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */
|
||||
#define WDT_EFIR (wdt_io+0) /* Extended Function Index Register
|
||||
(same as EFER) */
|
||||
#define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */
|
||||
|
||||
static void w83697ug_select_wd_register(void)
|
||||
{
|
||||
unsigned char c;
|
||||
unsigned char version;
|
||||
|
||||
outb_p(0x87, WDT_EFER); /* Enter extended function mode */
|
||||
outb_p(0x87, WDT_EFER); /* Again according to manual */
|
||||
|
||||
outb(0x20, WDT_EFER); /* check chip version */
|
||||
version = inb(WDT_EFDR);
|
||||
|
||||
if (version == 0x68) { /* W83697UG */
|
||||
printk(KERN_INFO PFX "Watchdog chip version 0x%02x = "
|
||||
"W83697UG/UF found at 0x%04x\n", version, wdt_io);
|
||||
|
||||
outb_p(0x2b, WDT_EFER);
|
||||
c = inb_p(WDT_EFDR); /* select WDT0 */
|
||||
c &= ~0x04;
|
||||
outb_p(0x2b, WDT_EFER);
|
||||
outb_p(c, WDT_EFDR); /* set pin118 to WDT0 */
|
||||
|
||||
} else {
|
||||
printk(KERN_ERR PFX "No W83697UG/UF could be found\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
outb_p(0x07, WDT_EFER); /* point to logical device number reg */
|
||||
outb_p(0x08, WDT_EFDR); /* select logical device 8 (GPIO2) */
|
||||
outb_p(0x30, WDT_EFER); /* select CR30 */
|
||||
c = inb_p(WDT_EFDR);
|
||||
outb_p(c || 0x01, WDT_EFDR); /* set bit 0 to activate GPIO2 */
|
||||
}
|
||||
|
||||
static void w83697ug_unselect_wd_register(void)
|
||||
{
|
||||
outb_p(0xAA, WDT_EFER); /* Leave extended function mode */
|
||||
}
|
||||
|
||||
static void w83697ug_init(void)
|
||||
{
|
||||
unsigned char t;
|
||||
|
||||
w83697ug_select_wd_register();
|
||||
|
||||
outb_p(0xF6, WDT_EFER); /* Select CRF6 */
|
||||
t = inb_p(WDT_EFDR); /* read CRF6 */
|
||||
if (t != 0) {
|
||||
printk(KERN_INFO PFX "Watchdog already running."
|
||||
" Resetting timeout to %d sec\n", timeout);
|
||||
outb_p(timeout, WDT_EFDR); /* Write back to CRF6 */
|
||||
}
|
||||
outb_p(0xF5, WDT_EFER); /* Select CRF5 */
|
||||
t = inb_p(WDT_EFDR); /* read CRF5 */
|
||||
t &= ~0x0C; /* set second mode &
|
||||
disable keyboard turning off watchdog */
|
||||
outb_p(t, WDT_EFDR); /* Write back to CRF5 */
|
||||
|
||||
w83697ug_unselect_wd_register();
|
||||
}
|
||||
|
||||
static void wdt_ctrl(int timeout)
|
||||
{
|
||||
spin_lock(&io_lock);
|
||||
|
||||
w83697ug_select_wd_register();
|
||||
|
||||
outb_p(0xF4, WDT_EFER); /* Select CRF4 */
|
||||
outb_p(timeout, WDT_EFDR); /* Write Timeout counter to CRF4 */
|
||||
|
||||
w83697ug_unselect_wd_register();
|
||||
|
||||
spin_unlock(&io_lock);
|
||||
}
|
||||
|
||||
static int wdt_ping(void)
|
||||
{
|
||||
wdt_ctrl(timeout);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wdt_disable(void)
|
||||
{
|
||||
wdt_ctrl(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wdt_set_heartbeat(int t)
|
||||
{
|
||||
if (t < 1 || t > 255)
|
||||
return -EINVAL;
|
||||
|
||||
timeout = t;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t wdt_write(struct file *file, const char __user *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
if (count) {
|
||||
if (!nowayout) {
|
||||
size_t i;
|
||||
|
||||
expect_close = 0;
|
||||
|
||||
for (i = 0; i != count; i++) {
|
||||
char c;
|
||||
if (get_user(c, buf + i))
|
||||
return -EFAULT;
|
||||
if (c == 'V')
|
||||
expect_close = 42;
|
||||
}
|
||||
}
|
||||
wdt_ping();
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
void __user *argp = (void __user *)arg;
|
||||
int __user *p = argp;
|
||||
int new_timeout;
|
||||
static const struct watchdog_info ident = {
|
||||
.options = WDIOF_KEEPALIVEPING |
|
||||
WDIOF_SETTIMEOUT |
|
||||
WDIOF_MAGICCLOSE,
|
||||
.firmware_version = 1,
|
||||
.identity = "W83697UG WDT",
|
||||
};
|
||||
|
||||
switch (cmd) {
|
||||
case WDIOC_GETSUPPORT:
|
||||
if (copy_to_user(argp, &ident, sizeof(ident)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
|
||||
case WDIOC_GETSTATUS:
|
||||
case WDIOC_GETBOOTSTATUS:
|
||||
return put_user(0, p);
|
||||
|
||||
case WDIOC_SETOPTIONS:
|
||||
{
|
||||
int options, retval = -EINVAL;
|
||||
|
||||
if (get_user(options, p))
|
||||
return -EFAULT;
|
||||
|
||||
if (options & WDIOS_DISABLECARD) {
|
||||
wdt_disable();
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
if (options & WDIOS_ENABLECARD) {
|
||||
wdt_ping();
|
||||
retval = 0;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
case WDIOC_KEEPALIVE:
|
||||
wdt_ping();
|
||||
break;
|
||||
|
||||
case WDIOC_SETTIMEOUT:
|
||||
if (get_user(new_timeout, p))
|
||||
return -EFAULT;
|
||||
if (wdt_set_heartbeat(new_timeout))
|
||||
return -EINVAL;
|
||||
wdt_ping();
|
||||
/* Fall */
|
||||
|
||||
case WDIOC_GETTIMEOUT:
|
||||
return put_user(timeout, p);
|
||||
|
||||
default:
|
||||
return -ENOTTY;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wdt_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (test_and_set_bit(0, &wdt_is_open))
|
||||
return -EBUSY;
|
||||
/*
|
||||
* Activate
|
||||
*/
|
||||
|
||||
wdt_ping();
|
||||
return nonseekable_open(inode, file);
|
||||
}
|
||||
|
||||
static int wdt_close(struct inode *inode, struct file *file)
|
||||
{
|
||||
if (expect_close == 42)
|
||||
wdt_disable();
|
||||
else {
|
||||
printk(KERN_CRIT PFX
|
||||
"Unexpected close, not stopping watchdog!\n");
|
||||
wdt_ping();
|
||||
}
|
||||
expect_close = 0;
|
||||
clear_bit(0, &wdt_is_open);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notifier for system down
|
||||
*/
|
||||
|
||||
static int wdt_notify_sys(struct notifier_block *this, unsigned long code,
|
||||
void *unused)
|
||||
{
|
||||
if (code == SYS_DOWN || code == SYS_HALT)
|
||||
wdt_disable(); /* Turn the WDT off */
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Kernel Interfaces
|
||||
*/
|
||||
|
||||
static const struct file_operations wdt_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = no_llseek,
|
||||
.write = wdt_write,
|
||||
.unlocked_ioctl = wdt_ioctl,
|
||||
.open = wdt_open,
|
||||
.release = wdt_close,
|
||||
};
|
||||
|
||||
static struct miscdevice wdt_miscdev = {
|
||||
.minor = WATCHDOG_MINOR,
|
||||
.name = "watchdog",
|
||||
.fops = &wdt_fops,
|
||||
};
|
||||
|
||||
/*
|
||||
* The WDT needs to learn about soft shutdowns in order to
|
||||
* turn the timebomb registers off.
|
||||
*/
|
||||
|
||||
static struct notifier_block wdt_notifier = {
|
||||
.notifier_call = wdt_notify_sys,
|
||||
};
|
||||
|
||||
static int __init wdt_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "WDT driver for the Winbond(TM) W83697UG/UF Super I/O chip initialising.\n");
|
||||
|
||||
if (wdt_set_heartbeat(timeout)) {
|
||||
wdt_set_heartbeat(WATCHDOG_TIMEOUT);
|
||||
printk(KERN_INFO PFX
|
||||
"timeout value must be 1<=timeout<=255, using %d\n",
|
||||
WATCHDOG_TIMEOUT);
|
||||
}
|
||||
|
||||
if (!request_region(wdt_io, 1, WATCHDOG_NAME)) {
|
||||
printk(KERN_ERR PFX "I/O address 0x%04x already in use\n",
|
||||
wdt_io);
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
w83697ug_init();
|
||||
|
||||
ret = register_reboot_notifier(&wdt_notifier);
|
||||
if (ret != 0) {
|
||||
printk(KERN_ERR PFX
|
||||
"cannot register reboot notifier (err=%d)\n", ret);
|
||||
goto unreg_regions;
|
||||
}
|
||||
|
||||
ret = misc_register(&wdt_miscdev);
|
||||
if (ret != 0) {
|
||||
printk(KERN_ERR PFX
|
||||
"cannot register miscdev on minor=%d (err=%d)\n",
|
||||
WATCHDOG_MINOR, ret);
|
||||
goto unreg_reboot;
|
||||
}
|
||||
|
||||
printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n",
|
||||
timeout, nowayout);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
unreg_reboot:
|
||||
unregister_reboot_notifier(&wdt_notifier);
|
||||
unreg_regions:
|
||||
release_region(wdt_io, 1);
|
||||
goto out;
|
||||
}
|
||||
|
||||
static void __exit wdt_exit(void)
|
||||
{
|
||||
misc_deregister(&wdt_miscdev);
|
||||
unregister_reboot_notifier(&wdt_notifier);
|
||||
release_region(wdt_io, 1);
|
||||
}
|
||||
|
||||
module_init(wdt_init);
|
||||
module_exit(wdt_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Flemming Frandsen <ff@nrvissing.net>");
|
||||
MODULE_DESCRIPTION("w83697ug/uf WDT driver");
|
||||
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
Loading…
Reference in New Issue
Block a user