dmaengine: mpc512x: Split device_control
Split the device_control callback of the Freescale MPC512x DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -800,79 +800,69 @@ err_prep:
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return NULL;
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}
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static int mpc_dma_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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static int mpc_dma_device_config(struct dma_chan *chan,
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struct dma_slave_config *cfg)
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{
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struct mpc_dma_chan *mchan;
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struct mpc_dma *mdma;
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struct dma_slave_config *cfg;
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
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unsigned long flags;
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mchan = dma_chan_to_mpc_dma_chan(chan);
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switch (cmd) {
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case DMA_TERMINATE_ALL:
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/* Disable channel requests */
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mdma = dma_chan_to_mpc_dma(chan);
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/*
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* Software constraints:
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* - only transfers between a peripheral device and
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* memory are supported;
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* - only peripheral devices with 4-byte FIFO access register
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* are supported;
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* - minimal transfer chunk is 4 bytes and consequently
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* source and destination addresses must be 4-byte aligned
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* and transfer size must be aligned on (4 * maxburst)
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* boundary;
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* - during the transfer RAM address is being incremented by
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* the size of minimal transfer chunk;
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* - peripheral port's address is constant during the transfer.
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*/
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spin_lock_irqsave(&mchan->lock, flags);
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out_8(&mdma->regs->dmacerq, chan->chan_id);
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list_splice_tail_init(&mchan->prepared, &mchan->free);
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list_splice_tail_init(&mchan->queued, &mchan->free);
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list_splice_tail_init(&mchan->active, &mchan->free);
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spin_unlock_irqrestore(&mchan->lock, flags);
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return 0;
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case DMA_SLAVE_CONFIG:
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/*
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* Software constraints:
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* - only transfers between a peripheral device and
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* memory are supported;
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* - only peripheral devices with 4-byte FIFO access register
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* are supported;
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* - minimal transfer chunk is 4 bytes and consequently
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* source and destination addresses must be 4-byte aligned
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* and transfer size must be aligned on (4 * maxburst)
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* boundary;
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* - during the transfer RAM address is being incremented by
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* the size of minimal transfer chunk;
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* - peripheral port's address is constant during the transfer.
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*/
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cfg = (void *)arg;
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if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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!IS_ALIGNED(cfg->src_addr, 4) ||
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!IS_ALIGNED(cfg->dst_addr, 4)) {
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return -EINVAL;
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}
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spin_lock_irqsave(&mchan->lock, flags);
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mchan->src_per_paddr = cfg->src_addr;
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mchan->src_tcd_nunits = cfg->src_maxburst;
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mchan->dst_per_paddr = cfg->dst_addr;
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mchan->dst_tcd_nunits = cfg->dst_maxburst;
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/* Apply defaults */
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if (mchan->src_tcd_nunits == 0)
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mchan->src_tcd_nunits = 1;
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if (mchan->dst_tcd_nunits == 0)
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mchan->dst_tcd_nunits = 1;
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spin_unlock_irqrestore(&mchan->lock, flags);
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return 0;
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default:
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/* Unknown command */
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break;
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if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES ||
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!IS_ALIGNED(cfg->src_addr, 4) ||
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!IS_ALIGNED(cfg->dst_addr, 4)) {
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return -EINVAL;
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}
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return -ENXIO;
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spin_lock_irqsave(&mchan->lock, flags);
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mchan->src_per_paddr = cfg->src_addr;
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mchan->src_tcd_nunits = cfg->src_maxburst;
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mchan->dst_per_paddr = cfg->dst_addr;
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mchan->dst_tcd_nunits = cfg->dst_maxburst;
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/* Apply defaults */
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if (mchan->src_tcd_nunits == 0)
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mchan->src_tcd_nunits = 1;
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if (mchan->dst_tcd_nunits == 0)
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mchan->dst_tcd_nunits = 1;
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spin_unlock_irqrestore(&mchan->lock, flags);
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return 0;
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}
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static int mpc_dma_device_terminate_all(struct dma_chan *chan)
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{
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
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struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
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unsigned long flags;
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/* Disable channel requests */
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spin_lock_irqsave(&mchan->lock, flags);
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out_8(&mdma->regs->dmacerq, chan->chan_id);
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list_splice_tail_init(&mchan->prepared, &mchan->free);
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list_splice_tail_init(&mchan->queued, &mchan->free);
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list_splice_tail_init(&mchan->active, &mchan->free);
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spin_unlock_irqrestore(&mchan->lock, flags);
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return 0;
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}
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static int mpc_dma_probe(struct platform_device *op)
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@ -963,7 +953,8 @@ static int mpc_dma_probe(struct platform_device *op)
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dma->device_tx_status = mpc_dma_tx_status;
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dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
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dma->device_prep_slave_sg = mpc_dma_prep_slave_sg;
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dma->device_control = mpc_dma_device_control;
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dma->device_config = mpc_dma_device_config;
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dma->device_terminate_all = mpc_dma_device_terminate_all;
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INIT_LIST_HEAD(&dma->channels);
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dma_cap_set(DMA_MEMCPY, dma->cap_mask);
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