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regulator: stm32-pwr: Fix regulator disabling

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The following shows up in the kernel log on systems using the STM32MP15xx USBPHYC:
"
regulator regulator.19: regulator disable timed out!
reg18: failed to disable: -ETIMEDOUT
"
This 'regulator.19' is 'pwr@50001000' 'reg18' in stm32mp151.dts DT, or
"Power control (PWR)" register "PWR_CR3" bits "REG18" on STM32MP15xx
reference manual.

The reason for the timeout seems to be the poll which this patch changes.
When turning this regulator OFF, PWR_CR3 reads 0xf0000000 , then REG18_EN
bit is cleared, and then this poll waits until REG18_RDY bit is cleared as
well, but that never happens, the PWR_CR3 keeps reading 0xe0000000 .

I am not sure whether this should happen, I suspect the 1V8 supply is
always READY when the 1V8 input is present, and the regulator can only
ever be enabled/disabled using the REG18_EN bit, but the REG18_READY
bit is never cleared again.

This patch adjusts the poll to check whether REG18_EN has been cleared
on regulator disable, but retains the check for REG18_READY in regulator
enable as there it makes sense to verify the regulator is really READY.

Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20230518023946.530381-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Marek Vasut 2023-05-18 04:39:46 +02:00 committed by Mark Brown
parent b8cabec75b
commit 959c34765c
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GPG Key ID: 24D68B725D5487D0
1 changed files with 1 additions and 1 deletions
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2
drivers/regulator/stm32-pwr.c
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@ -93,7 +93,7 @@ static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
writel_relaxed(val, priv->base + REG_PWR_CR3);
/* use an arbitrary timeout of 20ms */
ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
ret = readx_poll_timeout(stm32_pwr_reg_is_enabled, rdev, val, !val,
100, 20 * 1000);
if (ret)
dev_err(&rdev->dev, "regulator disable timed out!\n");