dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding
This patch adds bindings for i.MX8qm/qxp Control and Status Registers module. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220611141421.718743-14-victor.liu@nxp.com
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Liu Ying
Robert Foss
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192
Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
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Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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description: |
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As a system controller, the Freescale i.MX8qm/qxp Control and Status
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Registers(CSR) module represents a set of miscellaneous registers of a
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specific subsystem. It may provide control and/or status report interfaces
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to a mix of standalone hardware devices within that subsystem. One typical
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use-case is for some other nodes to acquire a reference to the syscon node
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by phandle, and the other typical use-case is that the operating system
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should consider all subnodes of the CSR module as separate child devices.
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properties:
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$nodename:
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pattern: "^syscon@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- fsl,imx8qxp-mipi-lvds-csr
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- fsl,imx8qm-lvds-csr
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: ipg
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patternProperties:
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"^(ldb|phy|pxl2dpi)$":
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type: object
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description: The possible child devices of the CSR module.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8qxp-mipi-lvds-csr
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then:
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required:
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- pxl2dpi
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- ldb
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8qm-lvds-csr
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then:
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required:
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- phy
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- ldb
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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mipi_lvds_0_csr: syscon@56221000 {
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compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
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reg = <0x56221000 0x1000>;
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clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
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clock-names = "ipg";
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mipi_lvds_0_pxl2dpi: pxl2dpi {
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compatible = "fsl,imx8qxp-pxl2dpi";
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fsl,sc-resource = <IMX_SC_R_MIPI_0>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
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};
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mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
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};
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mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
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};
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};
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};
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};
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mipi_lvds_0_ldb: ldb {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qxp-ldb";
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clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
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<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
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clock-names = "pixel", "bypass";
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power-domains = <&pd IMX_SC_R_LVDS_0>;
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channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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phys = <&mipi_lvds_0_phy>;
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phy-names = "lvds_phy";
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port@0 {
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reg = <0>;
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mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
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};
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};
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port@1 {
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reg = <1>;
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/* ... */
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};
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};
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channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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phys = <&mipi_lvds_0_phy>;
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phy-names = "lvds_phy";
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port@0 {
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reg = <0>;
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mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
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};
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};
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port@1 {
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reg = <1>;
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/* ... */
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};
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};
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};
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};
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mipi_lvds_0_phy: phy@56228300 {
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compatible = "fsl,imx8qxp-mipi-dphy";
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reg = <0x56228300 0x100>;
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clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
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clock-names = "phy_ref";
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#phy-cells = <0>;
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fsl,syscon = <&mipi_lvds_0_csr>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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};
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