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drm/xe: Fix platform order

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Platform order in enum xe_platform started to be used by some parts of
the code, like the GuC/HuC firmware loading logic. The order itself is
not very important, but it's better to follow a convention: as was
documented in the comment above the enum, reorder the platforms by
graphics version. While at it, remove the gen terminology.

v2:
  - Use "graphics version" instead of chronological order (Matt Roper)
  - Also change pciidlist to follow the same order
  - Remove "gen" from comments around enum xe_platform

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230331230902.1603294-1-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-03-31 16:09:02 -07:00 committed by Rodrigo Vivi
parent c33a721943
commit 96578d106b
3 changed files with 11 additions and 9 deletions
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4
drivers/gpu/drm/xe/xe_pci.c
View File

@ -281,11 +281,11 @@ static const struct xe_device_desc mtl_desc = {
*/
static const struct pci_device_id pciidlist[] = {
XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
{ }
};

12
drivers/gpu/drm/xe/xe_platform_types.h
View File

@ -6,27 +6,29 @@
#ifndef _XE_PLATFORM_INFO_TYPES_H_
#define _XE_PLATFORM_INFO_TYPES_H_
/* Keep in gen based order, and chronological order within a gen */
/*
* Keep this in graphics version based order and chronological order within a
* version
*/
enum xe_platform {
XE_PLATFORM_UNINITIALIZED = 0,
/* gen12 */
XE_TIGERLAKE,
XE_ROCKETLAKE,
XE_ALDERLAKE_S,
XE_ALDERLAKE_P,
XE_DG1,
XE_DG2,
XE_PVC,
XE_ALDERLAKE_S,
XE_ALDERLAKE_P,
XE_METEORLAKE,
};
enum xe_subplatform {
XE_SUBPLATFORM_UNINITIALIZED = 0,
XE_SUBPLATFORM_NONE,
XE_SUBPLATFORM_ADLP_RPLU,
XE_SUBPLATFORM_DG2_G10,
XE_SUBPLATFORM_DG2_G11,
XE_SUBPLATFORM_DG2_G12,
XE_SUBPLATFORM_ADLP_RPLU,
};
#endif

4
drivers/gpu/drm/xe/xe_uc_fw.c
View File

@ -43,11 +43,11 @@ static struct xe_device *uc_fw_to_xe(struct xe_uc_fw *uc_fw)
*/
#define XE_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
fw_def(METEORLAKE, guc_def(mtl, 70, 5, 2)) \
fw_def(ALDERLAKE_P, guc_def(adlp, 70, 5, 2)) \
fw_def(ALDERLAKE_S, guc_def(tgl, 70, 5, 2)) \
fw_def(PVC, guc_def(pvc, 70, 5, 2)) \
fw_def(DG2, guc_def(dg2, 70, 5, 2)) \
fw_def(DG1, guc_def(dg1, 70, 5, 2)) \
fw_def(ALDERLAKE_P, guc_def(adlp, 70, 5, 2)) \
fw_def(ALDERLAKE_S, guc_def(tgl, 70, 5, 2)) \
fw_def(TIGERLAKE, guc_def(tgl, 70, 5, 2))
#define XE_HUC_FIRMWARE_DEFS(fw_def, huc_def, huc_ver) \