perf vendor events intel: Update uncore event list for CascadeLake Server
Update JSON uncore events for CascadeLake Server. Based on JSON list v1.11: https://download.01.org/perfmon/CLX/ Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@intel.com> Cc: Linux-kernel@vger.kernel.org Cc: Peter Zijlstra <peterz@infradead.org> Link: https //lore.kernel.org/r/20210810020508.31261-3-yao.jin@linux.intel.com Signed-off-by: Jin Yao <yao.jin@linux.intel.com>
This commit is contained in:
Jin Yao
Arnaldo Carvalho de Melo
parent
e0ddfd8d50
commit
96fe584f99
@ -64,15 +64,6 @@
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"UMask": "0x4",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Pre-charge for writes",
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"Counter": "0,1,2,3",
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"EventCode": "0x2",
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"EventName": "UNC_M_PRE_COUNT.WR",
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"PerPkg": "1",
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"UMask": "0x8",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
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"Counter": "0,1,2,3",
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@ -90,32 +81,32 @@
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB). Derived from unc_m_pmm_rpq_inserts",
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"BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts",
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"Counter": "0,1,2,3",
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"EventCode": "0xE3",
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"EventName": "UNC_M_PMM_BANDWIDTH.READ",
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"PerPkg": "1",
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"ScaleUnit": "6.103515625E-5MB",
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"ScaleUnit": "6.103515625E-5MB/sec",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB). Derived from unc_m_pmm_wpq_inserts",
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"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
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"Counter": "0,1,2,3",
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"EventCode": "0xE7",
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"EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
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"PerPkg": "1",
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"ScaleUnit": "6.103515625E-5MB",
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"ScaleUnit": "6.103515625E-5MB/sec",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB). Derived from unc_m_pmm_rpq_inserts",
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"BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts",
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"Counter": "0,1,2,3",
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"EventCode": "0xE3",
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"EventName": "UNC_M_PMM_BANDWIDTH.TOTAL",
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"MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS",
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"MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL",
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"PerPkg": "1",
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"ScaleUnit": "6.103515625E-5MB",
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"ScaleUnit": "6.103515625E-5MB/sec",
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"Unit": "iMC"
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},
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{
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@ -103,15 +103,6 @@
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"UMask": "0x04",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "write requests from remote home agent",
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"Counter": "0,1,2,3",
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"EventCode": "0x50",
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"EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
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"PerPkg": "1",
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"UMask": "0x08",
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"Unit": "CHA"
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},
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{
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"BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
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"Counter": "0,1,2,3",
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@ -544,7 +535,7 @@
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"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
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"Filter": "config1=0x40433",
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"PerPkg": "1",
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"PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
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"PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
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"UMask": "0x21",
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"Unit": "CHA"
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},
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@ -567,6 +558,98 @@
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"PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
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"Counter": "0,1,2,3",
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"EventCode": "0xC2",
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"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
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"FCMask": "0x4",
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"PerPkg": "1",
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"PortMask": "0x01",
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"PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
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"UMask": "0x03",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
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"Counter": "0,1,2,3",
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"EventCode": "0xC2",
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"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
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"FCMask": "0x4",
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"PerPkg": "1",
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"PortMask": "0x02",
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"PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
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"UMask": "0x03",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
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"Counter": "0,1,2,3",
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"EventCode": "0xC2",
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"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
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"FCMask": "0x4",
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"PerPkg": "1",
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"PortMask": "0x04",
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"PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
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"UMask": "0x03",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
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"Counter": "0,1,2,3",
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"EventCode": "0xC2",
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"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
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"FCMask": "0x4",
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"PerPkg": "1",
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"PortMask": "0x08",
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"PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
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"UMask": "0x03",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
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"Counter": "2,3",
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"EventCode": "0xD5",
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"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
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"FCMask": "0x04",
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"PerPkg": "1",
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"PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
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"UMask": "0x01",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
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"Counter": "2,3",
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"EventCode": "0xD5",
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"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
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"FCMask": "0x04",
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"PerPkg": "1",
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"PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
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"UMask": "0x02",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
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"Counter": "2,3",
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"EventCode": "0xD5",
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"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
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"FCMask": "0x04",
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"PerPkg": "1",
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"PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
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"UMask": "0x04",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
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"Counter": "2,3",
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"EventCode": "0xD5",
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"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
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"FCMask": "0x04",
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"PerPkg": "1",
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"PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
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"UMask": "0x08",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
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"Counter": "2,3",
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@ -1239,6 +1322,64 @@
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"UMask": "0x02",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "Total IRP occupancy of inbound read and write requests.",
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"Counter": "0,1",
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"EventCode": "0xF",
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"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
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"PerPkg": "1",
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"PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.",
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"UMask": "0x4",
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"Unit": "IRP"
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},
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{
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"BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
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"Counter": "0,1",
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"EventCode": "0x10",
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"EventName": "UNC_I_COHERENT_OPS.PCITOM",
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"PerPkg": "1",
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"PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
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"UMask": "0x10",
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"Unit": "IRP"
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},
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{
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"BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
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"Counter": "0,1",
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"EventCode": "0x10",
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"EventName": "UNC_I_COHERENT_OPS.RFO",
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"PerPkg": "1",
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"PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
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"UMask": "0x8",
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"Unit": "IRP"
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},
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{
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"BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
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"Counter": "0,1",
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"EventCode": "0x18",
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"EventName": "UNC_I_FAF_INSERTS",
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"PerPkg": "1",
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"PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
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"Unit": "IRP"
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},
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{
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"BriefDescription": "Occupancy of the IRP FAF queue.",
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"Counter": "0,1",
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"EventCode": "0x19",
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"EventName": "UNC_I_FAF_OCCUPANCY",
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"PerPkg": "1",
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"PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
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"Unit": "IRP"
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},
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{
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"BriefDescription": "Inbound write (fast path) requests received by the IRP.",
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"Counter": "0,1",
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"EventCode": "0x11",
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"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
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"PerPkg": "1",
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"PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
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"UMask": "0x8",
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"Unit": "IRP"
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},
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{
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"BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
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"Counter": "0,1,2,3",
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