staging: sm750fb: Fix if/else/for/switch braces style
This patch fixes the checkpatch.pl errors:
ERROR: that open brace { should be on the previous line
ERROR: else should follow close brace '}'
WARNING: braces {} are not necessary for single statement blocks
ERROR: space required before the open brace '{'
Signed-off-by: Helen Fornazier <helen.fornazier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Helen Fornazier
Greg Kroah-Hartman
parent
569a6dcf3d
commit
9767fc5126
@ -21,21 +21,14 @@ logical_chip_type_t getChipType(void)
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physicalRev = revId750;
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if (physicalID == 0x718)
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{
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chip = SM718;
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}
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else if (physicalID == 0x750)
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{
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else if (physicalID == 0x750) {
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chip = SM750;
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/* SM750 and SM750LE are different in their revision ID only. */
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if (physicalRev == SM750LE_REVISION_ID){
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if (physicalRev == SM750LE_REVISION_ID)
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chip = SM750LE;
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}
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}
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else
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{
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} else
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chip = SM_UNKNOWN;
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}
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return chip;
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}
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@ -63,8 +56,7 @@ unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
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pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
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pPLL->clockType = clockType;
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switch (clockType)
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{
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switch (clockType) {
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case MXCLK_PLL:
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ulPllReg = PEEK32(MXCLK_PLL_CTRL);
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break;
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@ -118,8 +110,7 @@ void setChipClock(unsigned int frequency)
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return;
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#endif
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if (frequency != 0)
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{
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if (frequency != 0) {
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/*
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* Set up PLL, a structure to hold the value to be set in clocks.
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*/
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@ -148,8 +139,7 @@ void setMemoryClock(unsigned int frequency)
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if (getChipType() == SM750LE)
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return;
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#endif
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if (frequency != 0)
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{
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if (frequency != 0) {
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/* Set the frequency to the maximum frequency that the DDR Memory can take
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which is 336MHz. */
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if (frequency > MHz(336))
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@ -160,8 +150,7 @@ void setMemoryClock(unsigned int frequency)
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/* Set the corresponding divisor in the register. */
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ulReg = PEEK32(CURRENT_GATE);
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switch(divisor)
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{
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switch(divisor) {
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default:
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case 1:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1);
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@ -198,8 +187,7 @@ void setMasterClock(unsigned int frequency)
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if (getChipType() == SM750LE)
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return;
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#endif
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if (frequency != 0)
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{
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if (frequency != 0) {
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/* Set the frequency to the maximum frequency that the SM750 engine can
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run, which is about 190 MHz. */
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if (frequency > MHz(190))
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@ -210,8 +198,7 @@ void setMasterClock(unsigned int frequency)
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/* Set the corresponding divisor in the register. */
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ulReg = PEEK32(CURRENT_GATE);
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switch(divisor)
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{
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switch(divisor) {
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default:
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case 3:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
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@ -248,7 +235,7 @@ unsigned int ddk750_getVMSize(void)
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/* get frame buffer size from GPIO */
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reg = FIELD_GET(PEEK32(MISC_CTRL),MISC_CTRL,LOCALMEM_SIZE);
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switch(reg){
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switch(reg) {
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case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */
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@ -265,7 +252,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)
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unsigned int ulReg;
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#if 0
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//move the code to map regiter function.
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if(getChipType() == SM718){
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if(getChipType() == SM718) {
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/* turn on big endian bit*/
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ulReg = PEEK32(0x74);
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/* now consider register definition in a big endian pattern*/
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@ -285,13 +272,13 @@ int ddk750_initHw(initchip_param_t * pInitParam)
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ulReg = FIELD_SET(ulReg,CURRENT_GATE,LOCALMEM,ON);
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setCurrentGate(ulReg);
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if(getChipType() != SM750LE){
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if(getChipType() != SM750LE) {
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/* set panel pll and graphic mode via mmio_88 */
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ulReg = PEEK32(VGA_CONFIGURATION);
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ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,PLL,PANEL);
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ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,MODE,GRAPHIC);
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POKE32(VGA_CONFIGURATION,ulReg);
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}else{
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} else {
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#if defined(__i386__) || defined( __x86_64__)
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/* set graphic mode via IO method */
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outb_p(0x88,0x3d4);
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@ -313,8 +300,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)
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the system might hang when sw accesses the memory.
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The memory should be resetted after changing the MXCLK.
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*/
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if (pInitParam->resetMemory == 1)
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{
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if (pInitParam->resetMemory == 1) {
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ulReg = PEEK32(MISC_CTRL);
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ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, RESET);
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POKE32(MISC_CTRL, ulReg);
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@ -323,8 +309,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)
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POKE32(MISC_CTRL, ulReg);
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}
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if (pInitParam->setAllEngOff == 1)
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{
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if (pInitParam->setAllEngOff == 1) {
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enable2DEngine(0);
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/* Disable Overlay, if a former application left it on */
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@ -445,8 +430,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
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pllcalparam * xparm;
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#if 1
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if (getChipType() == SM750LE)
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{
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if (getChipType() == SM750LE) {
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/* SM750LE don't have prgrammable PLL and M/N values to work on.
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Just return the requested clock. */
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return request_orig;
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@ -460,36 +444,33 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
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/* for MXCLK register , no POD provided, so need be treated differently */
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if(pll->clockType != MXCLK_PLL){
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if(pll->clockType != MXCLK_PLL) {
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xparm = &xparm_PIXEL[0];
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xcnt = sizeof(xparm_PIXEL)/sizeof(xparm_PIXEL[0]);
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}else{
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} else {
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xparm = &xparm_MXCLK[0];
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xcnt = sizeof(xparm_MXCLK)/sizeof(xparm_MXCLK[0]);
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}
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for(N = 15;N>1;N--)
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{
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for(N = 15;N>1;N--) {
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/* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */
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RN = N * request;
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quo = RN / input;
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rem = RN % input;/* rem always small than 14318181 */
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fl_quo = (rem * 10000 /input);
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for(d = xcnt - 1;d >= 0;d--){
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for(d = xcnt - 1;d >= 0;d--) {
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X = xparm[d].value;
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M = quo*X;
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M += fl_quo * X / 10000;
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/* round step */
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M += (fl_quo*X % 10000)>5000?1:0;
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if(M < 256 && M > 0)
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{
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if(M < 256 && M > 0) {
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unsigned int diff;
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tmpClock = pll->inputFreq *M / N / X;
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diff = absDiff(tmpClock,request_orig);
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if(diff < miniDiff)
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{
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if(diff < miniDiff) {
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pll->M = M;
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pll->N = N;
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pll->OD = xparm[d].od;
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@ -541,8 +522,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
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podPower = twoToPowerOfx(POD);
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/* OD has only 2 bits [15:14] and its value must between 0 to 3 */
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for (OD=0; OD<=3; OD++)
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{
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for (OD=0; OD<=3; OD++) {
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/* Work out 2 to the power of OD */
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odPower = twoToPowerOfx(OD);
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@ -555,8 +535,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
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/* N has 4 bits [11:8] and its value must between 2 and 15.
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The N == 1 will behave differently --> Result is not correct. */
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for (N=2; N<=15; N++)
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{
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for (N=2; N<=15; N++) {
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/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)
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In the following steps, we try to work out a best M value given the others are known.
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To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
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@ -565,16 +544,14 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
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M = roundedDiv(M, 1000);
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/* M field has only 8 bits, reject value bigger than 8 bits */
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if (M < 256)
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{
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if (M < 256) {
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/* Calculate the actual clock for a given M & N */
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pllClk = pPLL->inputFreq * M / N / odPower / podPower;
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/* How much are we different from the requirement */
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diff = absDiff(pllClk, ulRequestClk);
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if (diff < bestDiff)
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{
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if (diff < bestDiff) {
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bestDiff = diff;
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/* Store M and N values */
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