drm/amd/display: disable clock gating logic reversed bug fix
[Why] disable clock gating logic reversed bug fix Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1018,8 +1018,8 @@ void hubbub31_init(struct hubbub *hubbub)
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/*done in hwseq*/
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/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/
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REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
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DISPCLK_R_DCHUBBUB_GATE_DIS, 0,
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DCFCLK_R_DCHUBBUB_GATE_DIS, 0);
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DISPCLK_R_DCHUBBUB_GATE_DIS, 1,
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DCFCLK_R_DCHUBBUB_GATE_DIS, 1);
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}
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/*
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@ -955,8 +955,8 @@ void hubbub32_init(struct hubbub *hubbub)
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/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/
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REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
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DISPCLK_R_DCHUBBUB_GATE_DIS, 0,
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DCFCLK_R_DCHUBBUB_GATE_DIS, 0);
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DISPCLK_R_DCHUBBUB_GATE_DIS, 1,
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DCFCLK_R_DCHUBBUB_GATE_DIS, 1);
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}
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/*
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ignore the "df_pre_cstate_req" from the SDP port control.
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