ARCv2: boot log: detect newer/upconing HS3x/HS4x releases
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -58,10 +58,12 @@ static const struct id_to_str arc_legacy_rel[] = {
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{ 0x00, NULL }
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{ 0x00, NULL }
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};
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};
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static const struct id_to_str arc_cpu_rel[] = {
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static const struct id_to_str arc_hs_ver54_rel[] = {
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/* UARCH.MAJOR, Release */
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/* UARCH.MAJOR, Release */
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{ 0, "R3.10a"},
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{ 0, "R3.10a"},
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{ 1, "R3.50a"},
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{ 1, "R3.50a"},
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{ 2, "R3.60a"},
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{ 3, "R4.00a"},
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{ 0xFF, NULL }
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{ 0xFF, NULL }
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};
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};
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@ -117,12 +119,6 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
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struct bcr_uarch_build_arcv2 uarch;
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struct bcr_uarch_build_arcv2 uarch;
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const struct id_to_str *tbl;
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const struct id_to_str *tbl;
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/*
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* Up until (including) the first core4 release (0x54) things were
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* simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
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* and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
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*/
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if (cpu->core.family < 0x54) { /* includes arc700 */
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if (cpu->core.family < 0x54) { /* includes arc700 */
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for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
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for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
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@ -143,11 +139,10 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
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}
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}
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/*
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/*
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* However the subsequent HS release (same 0x54) allow HS38 or HS48
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* Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
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* configurations and encode this info in a different BCR.
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* ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
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* The BCR was introduced in 0x54 so can't be read unconditionally.
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* releases only update it.
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*/
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*/
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READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
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READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
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if (uarch.prod == 4) {
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if (uarch.prod == 4) {
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@ -158,7 +153,7 @@ static void decode_arc_core(struct cpuinfo_arc *cpu)
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cpu->name = "HS38";
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cpu->name = "HS38";
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}
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}
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for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
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for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
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if (uarch.maj == tbl->id) {
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if (uarch.maj == tbl->id) {
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cpu->release = tbl->str;
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cpu->release = tbl->str;
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break;
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break;
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